2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * This driver currently only supports the SSI running in I2S slave mode.
72 * The SSI has a limitation in that the samples must be in the same byte
73 * order as the host CPU. This is because when multiple bytes are written
74 * to the STX register, the bytes and bits must be written in the same
75 * order. The STX is a shift register, so all the bits need to be aligned
76 * (bit-endianness must match byte-endianness). Processors typically write
77 * the bits within a byte in the same order that the bytes of a word are
78 * written in. So if the host CPU is big-endian, then only big-endian
79 * samples will be written to STX properly.
82 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
83 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
84 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
86 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
87 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
88 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
91 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
92 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
93 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
94 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
95 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
96 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
105 struct fsl_ssi_reg_val
{
112 struct fsl_ssi_rxtx_reg_val
{
113 struct fsl_ssi_reg_val rx
;
114 struct fsl_ssi_reg_val tx
;
116 static const struct regmap_config fsl_ssi_regconfig
= {
117 .max_register
= CCSR_SSI_SACCDIS
,
121 .val_format_endian
= REGMAP_ENDIAN_NATIVE
,
124 struct fsl_ssi_soc_data
{
131 * fsl_ssi_private: per-SSI private data
133 * @reg: Pointer to the regmap registers
134 * @irq: IRQ of this SSI
135 * @cpu_dai_drv: CPU DAI driver for this device
137 * @dai_fmt: DAI configuration this device is currently used with
138 * @i2s_mode: i2s and network mode configuration of the device. Is used to
139 * switch between normal and i2s/network mode
140 * mode depending on the number of channels
141 * @use_dma: DMA is used or FIQ with stream filter
142 * @use_dual_fifo: DMA with support for both FIFOs used
143 * @fifo_deph: Depth of the SSI FIFOs
144 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
147 * @baudclk: SSI baud clock for master mode
148 * @baudclk_streams: Active streams that are using baudclk
149 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
151 * @dma_params_tx: DMA transmit parameters
152 * @dma_params_rx: DMA receive parameters
153 * @ssi_phys: physical address of the SSI registers
155 * @fiq_params: FIQ stream filtering parameters
157 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
159 * @dbg_stats: Debugging statistics
161 * @soc: SoC specifc data
163 struct fsl_ssi_private
{
166 struct snd_soc_dai_driver cpu_dai_drv
;
168 unsigned int dai_fmt
;
172 unsigned int fifo_depth
;
173 struct fsl_ssi_rxtx_reg_val rxtx_reg_val
;
177 unsigned int baudclk_streams
;
178 unsigned int bitclk_freq
;
181 struct snd_dmaengine_dai_dma_data dma_params_tx
;
182 struct snd_dmaengine_dai_dma_data dma_params_rx
;
185 /* params for non-dma FIQ stream filtered mode */
186 struct imx_pcm_fiq_params fiq_params
;
188 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
189 * should be replaced with simple-sound-card. */
190 struct platform_device
*pdev
;
192 struct fsl_ssi_dbg dbg_stats
;
194 const struct fsl_ssi_soc_data
*soc
;
198 * imx51 and later SoCs have a slightly different IP that allows the
199 * SSI configuration while the SSI unit is running.
201 * More important, it is necessary on those SoCs to configure the
202 * sperate TX/RX DMA bits just before starting the stream
203 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
204 * sends any DMA requests to the SDMA unit, otherwise it is not defined
205 * how the SDMA unit handles the DMA request.
207 * SDMA units are present on devices starting at imx35 but the imx35
208 * reference manual states that the DMA bits should not be changed
209 * while the SSI unit is running (SSIEN). So we support the necessary
210 * online configuration of fsl-ssi starting at imx51.
213 static struct fsl_ssi_soc_data fsl_ssi_mpc8610
= {
215 .offline_config
= true,
216 .sisr_write_mask
= CCSR_SSI_SISR_RFRC
| CCSR_SSI_SISR_TFRC
|
217 CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
218 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
221 static struct fsl_ssi_soc_data fsl_ssi_imx21
= {
223 .offline_config
= true,
224 .sisr_write_mask
= 0,
227 static struct fsl_ssi_soc_data fsl_ssi_imx35
= {
229 .offline_config
= true,
230 .sisr_write_mask
= CCSR_SSI_SISR_RFRC
| CCSR_SSI_SISR_TFRC
|
231 CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
232 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
235 static struct fsl_ssi_soc_data fsl_ssi_imx51
= {
237 .offline_config
= false,
238 .sisr_write_mask
= CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
239 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
242 static const struct of_device_id fsl_ssi_ids
[] = {
243 { .compatible
= "fsl,mpc8610-ssi", .data
= &fsl_ssi_mpc8610
},
244 { .compatible
= "fsl,imx51-ssi", .data
= &fsl_ssi_imx51
},
245 { .compatible
= "fsl,imx35-ssi", .data
= &fsl_ssi_imx35
},
246 { .compatible
= "fsl,imx21-ssi", .data
= &fsl_ssi_imx21
},
249 MODULE_DEVICE_TABLE(of
, fsl_ssi_ids
);
251 static bool fsl_ssi_is_ac97(struct fsl_ssi_private
*ssi_private
)
253 return !!(ssi_private
->dai_fmt
& SND_SOC_DAIFMT_AC97
);
256 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private
*ssi_private
)
258 return (ssi_private
->dai_fmt
& SND_SOC_DAIFMT_MASTER_MASK
) ==
259 SND_SOC_DAIFMT_CBS_CFS
;
262 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private
*ssi_private
)
264 return (ssi_private
->dai_fmt
& SND_SOC_DAIFMT_MASTER_MASK
) ==
265 SND_SOC_DAIFMT_CBM_CFS
;
268 * fsl_ssi_isr: SSI interrupt handler
270 * Although it's possible to use the interrupt handler to send and receive
271 * data to/from the SSI, we use the DMA instead. Programming is more
272 * complicated, but the performance is much better.
274 * This interrupt handler is used only to gather statistics.
276 * @irq: IRQ of the SSI device
277 * @dev_id: pointer to the ssi_private structure for this SSI device
279 static irqreturn_t
fsl_ssi_isr(int irq
, void *dev_id
)
281 struct fsl_ssi_private
*ssi_private
= dev_id
;
282 struct regmap
*regs
= ssi_private
->regs
;
286 /* We got an interrupt, so read the status register to see what we
287 were interrupted for. We mask it with the Interrupt Enable register
288 so that we only check for events that we're interested in.
290 regmap_read(regs
, CCSR_SSI_SISR
, &sisr
);
292 sisr2
= sisr
& ssi_private
->soc
->sisr_write_mask
;
293 /* Clear the bits that we set */
295 regmap_write(regs
, CCSR_SSI_SISR
, sisr2
);
297 fsl_ssi_dbg_isr(&ssi_private
->dbg_stats
, sisr
);
303 * Enable/Disable all rx/tx config flags at once.
305 static void fsl_ssi_rxtx_config(struct fsl_ssi_private
*ssi_private
,
308 struct regmap
*regs
= ssi_private
->regs
;
309 struct fsl_ssi_rxtx_reg_val
*vals
= &ssi_private
->rxtx_reg_val
;
312 regmap_update_bits(regs
, CCSR_SSI_SIER
,
313 vals
->rx
.sier
| vals
->tx
.sier
,
314 vals
->rx
.sier
| vals
->tx
.sier
);
315 regmap_update_bits(regs
, CCSR_SSI_SRCR
,
316 vals
->rx
.srcr
| vals
->tx
.srcr
,
317 vals
->rx
.srcr
| vals
->tx
.srcr
);
318 regmap_update_bits(regs
, CCSR_SSI_STCR
,
319 vals
->rx
.stcr
| vals
->tx
.stcr
,
320 vals
->rx
.stcr
| vals
->tx
.stcr
);
322 regmap_update_bits(regs
, CCSR_SSI_SRCR
,
323 vals
->rx
.srcr
| vals
->tx
.srcr
, 0);
324 regmap_update_bits(regs
, CCSR_SSI_STCR
,
325 vals
->rx
.stcr
| vals
->tx
.stcr
, 0);
326 regmap_update_bits(regs
, CCSR_SSI_SIER
,
327 vals
->rx
.sier
| vals
->tx
.sier
, 0);
332 * Calculate the bits that have to be disabled for the current stream that is
333 * getting disabled. This keeps the bits enabled that are necessary for the
334 * second stream to work if 'stream_active' is true.
336 * Detailed calculation:
337 * These are the values that need to be active after disabling. For non-active
338 * second stream, this is 0:
339 * vals_stream * !!stream_active
341 * The following computes the overall differences between the setup for the
342 * to-disable stream and the active stream, a simple XOR:
343 * vals_disable ^ (vals_stream * !!(stream_active))
345 * The full expression adds a mask on all values we care about
347 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
349 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
352 * Enable/Disable a ssi configuration. You have to pass either
353 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
355 static void fsl_ssi_config(struct fsl_ssi_private
*ssi_private
, bool enable
,
356 struct fsl_ssi_reg_val
*vals
)
358 struct regmap
*regs
= ssi_private
->regs
;
359 struct fsl_ssi_reg_val
*avals
;
360 int nr_active_streams
;
364 regmap_read(regs
, CCSR_SSI_SCR
, &scr_val
);
366 nr_active_streams
= !!(scr_val
& CCSR_SSI_SCR_TE
) +
367 !!(scr_val
& CCSR_SSI_SCR_RE
);
369 if (nr_active_streams
- 1 > 0)
374 /* Find the other direction values rx or tx which we do not want to
376 if (&ssi_private
->rxtx_reg_val
.rx
== vals
)
377 avals
= &ssi_private
->rxtx_reg_val
.tx
;
379 avals
= &ssi_private
->rxtx_reg_val
.rx
;
381 /* If vals should be disabled, start with disabling the unit */
383 u32 scr
= fsl_ssi_disable_val(vals
->scr
, avals
->scr
,
385 regmap_update_bits(regs
, CCSR_SSI_SCR
, scr
, 0);
389 * We are running on a SoC which does not support online SSI
390 * reconfiguration, so we have to enable all necessary flags at once
391 * even if we do not use them later (capture and playback configuration)
393 if (ssi_private
->soc
->offline_config
) {
394 if ((enable
&& !nr_active_streams
) ||
395 (!enable
&& !keep_active
))
396 fsl_ssi_rxtx_config(ssi_private
, enable
);
402 * Configure single direction units while the SSI unit is running
403 * (online configuration)
406 regmap_update_bits(regs
, CCSR_SSI_SIER
, vals
->sier
, vals
->sier
);
407 regmap_update_bits(regs
, CCSR_SSI_SRCR
, vals
->srcr
, vals
->srcr
);
408 regmap_update_bits(regs
, CCSR_SSI_STCR
, vals
->stcr
, vals
->stcr
);
415 * Disabling the necessary flags for one of rx/tx while the
416 * other stream is active is a little bit more difficult. We
417 * have to disable only those flags that differ between both
418 * streams (rx XOR tx) and that are set in the stream that is
419 * disabled now. Otherwise we could alter flags of the other
423 /* These assignments are simply vals without bits set in avals*/
424 sier
= fsl_ssi_disable_val(vals
->sier
, avals
->sier
,
426 srcr
= fsl_ssi_disable_val(vals
->srcr
, avals
->srcr
,
428 stcr
= fsl_ssi_disable_val(vals
->stcr
, avals
->stcr
,
431 regmap_update_bits(regs
, CCSR_SSI_SRCR
, srcr
, 0);
432 regmap_update_bits(regs
, CCSR_SSI_STCR
, stcr
, 0);
433 regmap_update_bits(regs
, CCSR_SSI_SIER
, sier
, 0);
437 /* Enabling of subunits is done after configuration */
439 regmap_update_bits(regs
, CCSR_SSI_SCR
, vals
->scr
, vals
->scr
);
443 static void fsl_ssi_rx_config(struct fsl_ssi_private
*ssi_private
, bool enable
)
445 fsl_ssi_config(ssi_private
, enable
, &ssi_private
->rxtx_reg_val
.rx
);
448 static void fsl_ssi_tx_config(struct fsl_ssi_private
*ssi_private
, bool enable
)
450 fsl_ssi_config(ssi_private
, enable
, &ssi_private
->rxtx_reg_val
.tx
);
454 * Setup rx/tx register values used to enable/disable the streams. These will
455 * be used later in fsl_ssi_config to setup the streams without the need to
456 * check for all different SSI modes.
458 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private
*ssi_private
)
460 struct fsl_ssi_rxtx_reg_val
*reg
= &ssi_private
->rxtx_reg_val
;
462 reg
->rx
.sier
= CCSR_SSI_SIER_RFF0_EN
;
463 reg
->rx
.srcr
= CCSR_SSI_SRCR_RFEN0
;
465 reg
->tx
.sier
= CCSR_SSI_SIER_TFE0_EN
;
466 reg
->tx
.stcr
= CCSR_SSI_STCR_TFEN0
;
469 if (!fsl_ssi_is_ac97(ssi_private
)) {
470 reg
->rx
.scr
= CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_RE
;
471 reg
->rx
.sier
|= CCSR_SSI_SIER_RFF0_EN
;
472 reg
->tx
.scr
= CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
;
473 reg
->tx
.sier
|= CCSR_SSI_SIER_TFE0_EN
;
476 if (ssi_private
->use_dma
) {
477 reg
->rx
.sier
|= CCSR_SSI_SIER_RDMAE
;
478 reg
->tx
.sier
|= CCSR_SSI_SIER_TDMAE
;
480 reg
->rx
.sier
|= CCSR_SSI_SIER_RIE
;
481 reg
->tx
.sier
|= CCSR_SSI_SIER_TIE
;
484 reg
->rx
.sier
|= FSLSSI_SIER_DBG_RX_FLAGS
;
485 reg
->tx
.sier
|= FSLSSI_SIER_DBG_TX_FLAGS
;
488 static void fsl_ssi_setup_ac97(struct fsl_ssi_private
*ssi_private
)
490 struct regmap
*regs
= ssi_private
->regs
;
493 * Setup the clock control register
495 regmap_write(regs
, CCSR_SSI_STCCR
,
496 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
497 regmap_write(regs
, CCSR_SSI_SRCCR
,
498 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
501 * Enable AC97 mode and startup the SSI
503 regmap_write(regs
, CCSR_SSI_SACNT
,
504 CCSR_SSI_SACNT_AC97EN
| CCSR_SSI_SACNT_FV
);
505 regmap_write(regs
, CCSR_SSI_SACCDIS
, 0xff);
506 regmap_write(regs
, CCSR_SSI_SACCEN
, 0x300);
509 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
510 * codec before a stream is started.
512 regmap_update_bits(regs
, CCSR_SSI_SCR
,
513 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
,
514 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
);
516 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_WAIT(3));
520 * fsl_ssi_startup: create a new substream
522 * This is the first function called when a stream is opened.
524 * If this is the first stream open, then grab the IRQ and program most of
527 static int fsl_ssi_startup(struct snd_pcm_substream
*substream
,
528 struct snd_soc_dai
*dai
)
530 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
531 struct fsl_ssi_private
*ssi_private
=
532 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
534 /* When using dual fifo mode, it is safer to ensure an even period
535 * size. If appearing to an odd number while DMA always starts its
536 * task from fifo0, fifo1 would be neglected at the end of each
537 * period. But SSI would still access fifo1 with an invalid data.
539 if (ssi_private
->use_dual_fifo
)
540 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
541 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
, 2);
547 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
549 * Note: This function can be only called when using SSI as DAI master
551 * Quick instruction for parameters:
552 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
553 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
555 static int fsl_ssi_set_bclk(struct snd_pcm_substream
*substream
,
556 struct snd_soc_dai
*cpu_dai
,
557 struct snd_pcm_hw_params
*hw_params
)
559 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
560 struct regmap
*regs
= ssi_private
->regs
;
561 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
, ret
;
562 u32 pm
= 999, div2
, psr
, stccr
, mask
, afreq
, factor
, i
;
563 unsigned long clkrate
, baudrate
, tmprate
;
564 u64 sub
, savesub
= 100000;
566 bool baudclk_is_used
;
568 /* Prefer the explicitly set bitclock frequency */
569 if (ssi_private
->bitclk_freq
)
570 freq
= ssi_private
->bitclk_freq
;
572 freq
= params_channels(hw_params
) * 32 * params_rate(hw_params
);
574 /* Don't apply it to any non-baudclk circumstance */
575 if (IS_ERR(ssi_private
->baudclk
))
578 baudclk_is_used
= ssi_private
->baudclk_streams
& ~(BIT(substream
->stream
));
580 /* It should be already enough to divide clock by setting pm alone */
584 factor
= (div2
+ 1) * (7 * psr
+ 1) * 2;
586 for (i
= 0; i
< 255; i
++) {
587 /* The bclk rate must be smaller than 1/5 sysclk rate */
588 if (factor
* (i
+ 1) < 5)
591 tmprate
= freq
* factor
* (i
+ 2);
594 clkrate
= clk_get_rate(ssi_private
->baudclk
);
596 clkrate
= clk_round_rate(ssi_private
->baudclk
, tmprate
);
599 afreq
= clkrate
/ (i
+ 1);
603 else if (freq
/ afreq
== 1)
605 else if (afreq
/ freq
== 1)
610 /* Calculate the fraction */
625 /* No proper pm found if it is still remaining the initial value */
627 dev_err(cpu_dai
->dev
, "failed to handle the required sysclk\n");
631 stccr
= CCSR_SSI_SxCCR_PM(pm
+ 1) | (div2
? CCSR_SSI_SxCCR_DIV2
: 0) |
632 (psr
? CCSR_SSI_SxCCR_PSR
: 0);
633 mask
= CCSR_SSI_SxCCR_PM_MASK
| CCSR_SSI_SxCCR_DIV2
|
636 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
|| synchronous
)
637 regmap_update_bits(regs
, CCSR_SSI_STCCR
, mask
, stccr
);
639 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, mask
, stccr
);
641 if (!baudclk_is_used
) {
642 ret
= clk_set_rate(ssi_private
->baudclk
, baudrate
);
644 dev_err(cpu_dai
->dev
, "failed to set baudclk rate\n");
652 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
653 int clk_id
, unsigned int freq
, int dir
)
655 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
657 ssi_private
->bitclk_freq
= freq
;
663 * fsl_ssi_hw_params - program the sample size
665 * Most of the SSI registers have been programmed in the startup function,
666 * but the word length must be programmed here. Unfortunately, programming
667 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
668 * cause a problem with supporting simultaneous playback and capture. If
669 * the SSI is already playing a stream, then that stream may be temporarily
670 * stopped when you start capture.
672 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
675 static int fsl_ssi_hw_params(struct snd_pcm_substream
*substream
,
676 struct snd_pcm_hw_params
*hw_params
, struct snd_soc_dai
*cpu_dai
)
678 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
679 struct regmap
*regs
= ssi_private
->regs
;
680 unsigned int channels
= params_channels(hw_params
);
681 unsigned int sample_size
=
682 snd_pcm_format_width(params_format(hw_params
));
683 u32 wl
= CCSR_SSI_SxCCR_WL(sample_size
);
688 regmap_read(regs
, CCSR_SSI_SCR
, &scr_val
);
689 enabled
= scr_val
& CCSR_SSI_SCR_SSIEN
;
692 * If we're in synchronous mode, and the SSI is already enabled,
693 * then STCCR is already set properly.
695 if (enabled
&& ssi_private
->cpu_dai_drv
.symmetric_rates
)
698 if (fsl_ssi_is_i2s_master(ssi_private
)) {
699 ret
= fsl_ssi_set_bclk(substream
, cpu_dai
, hw_params
);
703 /* Do not enable the clock if it is already enabled */
704 if (!(ssi_private
->baudclk_streams
& BIT(substream
->stream
))) {
705 ret
= clk_prepare_enable(ssi_private
->baudclk
);
709 ssi_private
->baudclk_streams
|= BIT(substream
->stream
);
713 if (!fsl_ssi_is_ac97(ssi_private
)) {
716 * Switch to normal net mode in order to have a frame sync
717 * signal every 32 bits instead of 16 bits
719 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private
) && sample_size
== 16)
720 i2smode
= CCSR_SSI_SCR_I2S_MODE_NORMAL
|
723 i2smode
= ssi_private
->i2s_mode
;
725 regmap_update_bits(regs
, CCSR_SSI_SCR
,
726 CCSR_SSI_SCR_NET
| CCSR_SSI_SCR_I2S_MODE_MASK
,
727 channels
== 1 ? 0 : i2smode
);
731 * FIXME: The documentation says that SxCCR[WL] should not be
732 * modified while the SSI is enabled. The only time this can
733 * happen is if we're trying to do simultaneous playback and
734 * capture in asynchronous mode. Unfortunately, I have been enable
735 * to get that to work at all on the P1022DS. Therefore, we don't
736 * bother to disable/enable the SSI when setting SxCCR[WL], because
737 * the SSI will stop anyway. Maybe one day, this will get fixed.
740 /* In synchronous mode, the SSI uses STCCR for capture */
741 if ((substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) ||
742 ssi_private
->cpu_dai_drv
.symmetric_rates
)
743 regmap_update_bits(regs
, CCSR_SSI_STCCR
, CCSR_SSI_SxCCR_WL_MASK
,
746 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, CCSR_SSI_SxCCR_WL_MASK
,
752 static int fsl_ssi_hw_free(struct snd_pcm_substream
*substream
,
753 struct snd_soc_dai
*cpu_dai
)
755 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
756 struct fsl_ssi_private
*ssi_private
=
757 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
759 if (fsl_ssi_is_i2s_master(ssi_private
) &&
760 ssi_private
->baudclk_streams
& BIT(substream
->stream
)) {
761 clk_disable_unprepare(ssi_private
->baudclk
);
762 ssi_private
->baudclk_streams
&= ~BIT(substream
->stream
);
768 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private
*ssi_private
,
771 struct regmap
*regs
= ssi_private
->regs
;
772 u32 strcr
= 0, stcr
, srcr
, scr
, mask
;
775 ssi_private
->dai_fmt
= fmt
;
777 if (fsl_ssi_is_i2s_master(ssi_private
) && IS_ERR(ssi_private
->baudclk
)) {
778 dev_err(&ssi_private
->pdev
->dev
, "baudclk is missing which is necessary for master mode\n");
782 fsl_ssi_setup_reg_vals(ssi_private
);
784 regmap_read(regs
, CCSR_SSI_SCR
, &scr
);
785 scr
&= ~(CCSR_SSI_SCR_SYN
| CCSR_SSI_SCR_I2S_MODE_MASK
);
786 scr
|= CCSR_SSI_SCR_SYNC_TX_FS
;
788 mask
= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
|
789 CCSR_SSI_STCR_TSCKP
| CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TFSL
|
791 regmap_read(regs
, CCSR_SSI_STCR
, &stcr
);
792 regmap_read(regs
, CCSR_SSI_SRCR
, &srcr
);
796 ssi_private
->i2s_mode
= CCSR_SSI_SCR_NET
;
797 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
798 case SND_SOC_DAIFMT_I2S
:
799 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
800 case SND_SOC_DAIFMT_CBM_CFS
:
801 case SND_SOC_DAIFMT_CBS_CFS
:
802 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_MASTER
;
803 regmap_update_bits(regs
, CCSR_SSI_STCCR
,
804 CCSR_SSI_SxCCR_DC_MASK
,
805 CCSR_SSI_SxCCR_DC(2));
806 regmap_update_bits(regs
, CCSR_SSI_SRCCR
,
807 CCSR_SSI_SxCCR_DC_MASK
,
808 CCSR_SSI_SxCCR_DC(2));
810 case SND_SOC_DAIFMT_CBM_CFM
:
811 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
817 /* Data on rising edge of bclk, frame low, 1clk before data */
818 strcr
|= CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TSCKP
|
819 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
821 case SND_SOC_DAIFMT_LEFT_J
:
822 /* Data on rising edge of bclk, frame high */
823 strcr
|= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TSCKP
;
825 case SND_SOC_DAIFMT_DSP_A
:
826 /* Data on rising edge of bclk, frame high, 1clk before data */
827 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
828 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
830 case SND_SOC_DAIFMT_DSP_B
:
831 /* Data on rising edge of bclk, frame high */
832 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
833 CCSR_SSI_STCR_TXBIT0
;
835 case SND_SOC_DAIFMT_AC97
:
836 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_NORMAL
;
841 scr
|= ssi_private
->i2s_mode
;
843 /* DAI clock inversion */
844 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
845 case SND_SOC_DAIFMT_NB_NF
:
846 /* Nothing to do for both normal cases */
848 case SND_SOC_DAIFMT_IB_NF
:
849 /* Invert bit clock */
850 strcr
^= CCSR_SSI_STCR_TSCKP
;
852 case SND_SOC_DAIFMT_NB_IF
:
853 /* Invert frame clock */
854 strcr
^= CCSR_SSI_STCR_TFSI
;
856 case SND_SOC_DAIFMT_IB_IF
:
857 /* Invert both clocks */
858 strcr
^= CCSR_SSI_STCR_TSCKP
;
859 strcr
^= CCSR_SSI_STCR_TFSI
;
865 /* DAI clock master masks */
866 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
867 case SND_SOC_DAIFMT_CBS_CFS
:
868 strcr
|= CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
;
869 scr
|= CCSR_SSI_SCR_SYS_CLK_EN
;
871 case SND_SOC_DAIFMT_CBM_CFM
:
872 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
874 case SND_SOC_DAIFMT_CBM_CFS
:
875 strcr
&= ~CCSR_SSI_STCR_TXDIR
;
876 strcr
|= CCSR_SSI_STCR_TFDIR
;
877 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
886 if (ssi_private
->cpu_dai_drv
.symmetric_rates
) {
887 /* Need to clear RXDIR when using SYNC mode */
888 srcr
&= ~CCSR_SSI_SRCR_RXDIR
;
889 scr
|= CCSR_SSI_SCR_SYN
;
892 regmap_write(regs
, CCSR_SSI_STCR
, stcr
);
893 regmap_write(regs
, CCSR_SSI_SRCR
, srcr
);
894 regmap_write(regs
, CCSR_SSI_SCR
, scr
);
897 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
898 * use FIFO 1. We program the transmit water to signal a DMA transfer
899 * if there are only two (or fewer) elements left in the FIFO. Two
900 * elements equals one frame (left channel, right channel). This value,
901 * however, depends on the depth of the transmit buffer.
903 * We set the watermark on the same level as the DMA burstsize. For
904 * fiq it is probably better to use the biggest possible watermark
907 if (ssi_private
->use_dma
)
908 wm
= ssi_private
->fifo_depth
- 2;
910 wm
= ssi_private
->fifo_depth
;
912 regmap_write(regs
, CCSR_SSI_SFCSR
,
913 CCSR_SSI_SFCSR_TFWM0(wm
) | CCSR_SSI_SFCSR_RFWM0(wm
) |
914 CCSR_SSI_SFCSR_TFWM1(wm
) | CCSR_SSI_SFCSR_RFWM1(wm
));
916 if (ssi_private
->use_dual_fifo
) {
917 regmap_update_bits(regs
, CCSR_SSI_SRCR
, CCSR_SSI_SRCR_RFEN1
,
918 CCSR_SSI_SRCR_RFEN1
);
919 regmap_update_bits(regs
, CCSR_SSI_STCR
, CCSR_SSI_STCR_TFEN1
,
920 CCSR_SSI_STCR_TFEN1
);
921 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_TCH_EN
,
922 CCSR_SSI_SCR_TCH_EN
);
925 if (fmt
& SND_SOC_DAIFMT_AC97
)
926 fsl_ssi_setup_ac97(ssi_private
);
933 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
935 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai
*cpu_dai
, unsigned int fmt
)
937 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
939 return _fsl_ssi_set_dai_fmt(ssi_private
, fmt
);
943 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
945 * Note: This function can be only called when using SSI as DAI master
947 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
, u32 tx_mask
,
948 u32 rx_mask
, int slots
, int slot_width
)
950 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
951 struct regmap
*regs
= ssi_private
->regs
;
954 /* The slot number should be >= 2 if using Network mode or I2S mode */
955 regmap_read(regs
, CCSR_SSI_SCR
, &val
);
956 val
&= CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_NET
;
957 if (val
&& slots
< 2) {
958 dev_err(cpu_dai
->dev
, "slot number should be >= 2 in I2S or NET\n");
962 regmap_update_bits(regs
, CCSR_SSI_STCCR
, CCSR_SSI_SxCCR_DC_MASK
,
963 CCSR_SSI_SxCCR_DC(slots
));
964 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, CCSR_SSI_SxCCR_DC_MASK
,
965 CCSR_SSI_SxCCR_DC(slots
));
967 /* The register SxMSKs needs SSI to provide essential clock due to
968 * hardware design. So we here temporarily enable SSI to set them.
970 regmap_read(regs
, CCSR_SSI_SCR
, &val
);
971 val
&= CCSR_SSI_SCR_SSIEN
;
972 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_SSIEN
,
975 regmap_write(regs
, CCSR_SSI_STMSK
, tx_mask
);
976 regmap_write(regs
, CCSR_SSI_SRMSK
, rx_mask
);
978 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_SSIEN
, val
);
984 * fsl_ssi_trigger: start and stop the DMA transfer.
986 * This function is called by ALSA to start, stop, pause, and resume the DMA
989 * The DMA channel is in external master start and pause mode, which
990 * means the SSI completely controls the flow of data.
992 static int fsl_ssi_trigger(struct snd_pcm_substream
*substream
, int cmd
,
993 struct snd_soc_dai
*dai
)
995 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
996 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
997 struct regmap
*regs
= ssi_private
->regs
;
1000 case SNDRV_PCM_TRIGGER_START
:
1001 case SNDRV_PCM_TRIGGER_RESUME
:
1002 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1003 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1004 fsl_ssi_tx_config(ssi_private
, true);
1006 fsl_ssi_rx_config(ssi_private
, true);
1009 case SNDRV_PCM_TRIGGER_STOP
:
1010 case SNDRV_PCM_TRIGGER_SUSPEND
:
1011 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1012 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1013 fsl_ssi_tx_config(ssi_private
, false);
1015 fsl_ssi_rx_config(ssi_private
, false);
1022 if (fsl_ssi_is_ac97(ssi_private
)) {
1023 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1024 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_TX_CLR
);
1026 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_RX_CLR
);
1032 static int fsl_ssi_dai_probe(struct snd_soc_dai
*dai
)
1034 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(dai
);
1036 if (ssi_private
->soc
->imx
&& ssi_private
->use_dma
) {
1037 dai
->playback_dma_data
= &ssi_private
->dma_params_tx
;
1038 dai
->capture_dma_data
= &ssi_private
->dma_params_rx
;
1044 static const struct snd_soc_dai_ops fsl_ssi_dai_ops
= {
1045 .startup
= fsl_ssi_startup
,
1046 .hw_params
= fsl_ssi_hw_params
,
1047 .hw_free
= fsl_ssi_hw_free
,
1048 .set_fmt
= fsl_ssi_set_dai_fmt
,
1049 .set_sysclk
= fsl_ssi_set_dai_sysclk
,
1050 .set_tdm_slot
= fsl_ssi_set_dai_tdm_slot
,
1051 .trigger
= fsl_ssi_trigger
,
1054 /* Template for the CPU dai driver structure */
1055 static struct snd_soc_dai_driver fsl_ssi_dai_template
= {
1056 .probe
= fsl_ssi_dai_probe
,
1058 .stream_name
= "CPU-Playback",
1061 .rates
= FSLSSI_I2S_RATES
,
1062 .formats
= FSLSSI_I2S_FORMATS
,
1065 .stream_name
= "CPU-Capture",
1068 .rates
= FSLSSI_I2S_RATES
,
1069 .formats
= FSLSSI_I2S_FORMATS
,
1071 .ops
= &fsl_ssi_dai_ops
,
1074 static const struct snd_soc_component_driver fsl_ssi_component
= {
1078 static struct snd_soc_dai_driver fsl_ssi_ac97_dai
= {
1081 .stream_name
= "AC97 Playback",
1084 .rates
= SNDRV_PCM_RATE_8000_48000
,
1085 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1088 .stream_name
= "AC97 Capture",
1091 .rates
= SNDRV_PCM_RATE_48000
,
1092 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1094 .ops
= &fsl_ssi_dai_ops
,
1098 static struct fsl_ssi_private
*fsl_ac97_data
;
1100 static void fsl_ssi_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
1103 struct regmap
*regs
= fsl_ac97_data
->regs
;
1112 regmap_write(regs
, CCSR_SSI_SACADD
, lreg
);
1115 regmap_write(regs
, CCSR_SSI_SACDAT
, lval
);
1117 regmap_update_bits(regs
, CCSR_SSI_SACNT
, CCSR_SSI_SACNT_RDWR_MASK
,
1122 static unsigned short fsl_ssi_ac97_read(struct snd_ac97
*ac97
,
1125 struct regmap
*regs
= fsl_ac97_data
->regs
;
1127 unsigned short val
= -1;
1131 lreg
= (reg
& 0x7f) << 12;
1132 regmap_write(regs
, CCSR_SSI_SACADD
, lreg
);
1133 regmap_update_bits(regs
, CCSR_SSI_SACNT
, CCSR_SSI_SACNT_RDWR_MASK
,
1138 regmap_read(regs
, CCSR_SSI_SACDAT
, ®_val
);
1139 val
= (reg_val
>> 4) & 0xffff;
1144 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops
= {
1145 .read
= fsl_ssi_ac97_read
,
1146 .write
= fsl_ssi_ac97_write
,
1150 * Make every character in a string lower-case
1152 static void make_lowercase(char *s
)
1158 if ((c
>= 'A') && (c
<= 'Z'))
1159 *p
= c
+ ('a' - 'A');
1164 static int fsl_ssi_imx_probe(struct platform_device
*pdev
,
1165 struct fsl_ssi_private
*ssi_private
, void __iomem
*iomem
)
1167 struct device_node
*np
= pdev
->dev
.of_node
;
1171 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1172 if (IS_ERR(ssi_private
->clk
)) {
1173 ret
= PTR_ERR(ssi_private
->clk
);
1174 dev_err(&pdev
->dev
, "could not get clock: %d\n", ret
);
1178 ret
= clk_prepare_enable(ssi_private
->clk
);
1180 dev_err(&pdev
->dev
, "clk_prepare_enable failed: %d\n", ret
);
1184 /* For those SLAVE implementations, we ingore non-baudclk cases
1185 * and, instead, abandon MASTER mode that needs baud clock.
1187 ssi_private
->baudclk
= devm_clk_get(&pdev
->dev
, "baud");
1188 if (IS_ERR(ssi_private
->baudclk
))
1189 dev_dbg(&pdev
->dev
, "could not get baud clock: %ld\n",
1190 PTR_ERR(ssi_private
->baudclk
));
1193 * We have burstsize be "fifo_depth - 2" to match the SSI
1194 * watermark setting in fsl_ssi_startup().
1196 ssi_private
->dma_params_tx
.maxburst
= ssi_private
->fifo_depth
- 2;
1197 ssi_private
->dma_params_rx
.maxburst
= ssi_private
->fifo_depth
- 2;
1198 ssi_private
->dma_params_tx
.addr
= ssi_private
->ssi_phys
+ CCSR_SSI_STX0
;
1199 ssi_private
->dma_params_rx
.addr
= ssi_private
->ssi_phys
+ CCSR_SSI_SRX0
;
1201 ret
= !of_property_read_u32_array(np
, "dmas", dmas
, 4);
1202 if (ssi_private
->use_dma
&& !ret
&& dmas
[2] == IMX_DMATYPE_SSI_DUAL
) {
1203 ssi_private
->use_dual_fifo
= true;
1204 /* When using dual fifo mode, we need to keep watermark
1205 * as even numbers due to dma script limitation.
1207 ssi_private
->dma_params_tx
.maxburst
&= ~0x1;
1208 ssi_private
->dma_params_rx
.maxburst
&= ~0x1;
1211 if (!ssi_private
->use_dma
) {
1214 * Some boards use an incompatible codec. To get it
1215 * working, we are using imx-fiq-pcm-audio, that
1216 * can handle those codecs. DMA is not possible in this
1220 ssi_private
->fiq_params
.irq
= ssi_private
->irq
;
1221 ssi_private
->fiq_params
.base
= iomem
;
1222 ssi_private
->fiq_params
.dma_params_rx
=
1223 &ssi_private
->dma_params_rx
;
1224 ssi_private
->fiq_params
.dma_params_tx
=
1225 &ssi_private
->dma_params_tx
;
1227 ret
= imx_pcm_fiq_init(pdev
, &ssi_private
->fiq_params
);
1231 ret
= imx_pcm_dma_init(pdev
);
1239 clk_disable_unprepare(ssi_private
->clk
);
1244 static void fsl_ssi_imx_clean(struct platform_device
*pdev
,
1245 struct fsl_ssi_private
*ssi_private
)
1247 if (!ssi_private
->use_dma
)
1248 imx_pcm_fiq_exit(pdev
);
1249 clk_disable_unprepare(ssi_private
->clk
);
1252 static int fsl_ssi_probe(struct platform_device
*pdev
)
1254 struct fsl_ssi_private
*ssi_private
;
1256 struct device_node
*np
= pdev
->dev
.of_node
;
1257 const struct of_device_id
*of_id
;
1258 const char *p
, *sprop
;
1259 const uint32_t *iprop
;
1260 struct resource res
;
1261 void __iomem
*iomem
;
1264 /* SSIs that are not connected on the board should have a
1265 * status = "disabled"
1266 * property in their device tree nodes.
1268 if (!of_device_is_available(np
))
1271 of_id
= of_match_device(fsl_ssi_ids
, &pdev
->dev
);
1272 if (!of_id
|| !of_id
->data
)
1275 ssi_private
= devm_kzalloc(&pdev
->dev
, sizeof(*ssi_private
),
1278 dev_err(&pdev
->dev
, "could not allocate DAI object\n");
1282 ssi_private
->soc
= of_id
->data
;
1284 sprop
= of_get_property(np
, "fsl,mode", NULL
);
1286 if (!strcmp(sprop
, "ac97-slave"))
1287 ssi_private
->dai_fmt
= SND_SOC_DAIFMT_AC97
;
1288 else if (!strcmp(sprop
, "i2s-slave"))
1289 ssi_private
->dai_fmt
= SND_SOC_DAIFMT_I2S
|
1290 SND_SOC_DAIFMT_CBM_CFM
;
1293 ssi_private
->use_dma
= !of_property_read_bool(np
,
1294 "fsl,fiq-stream-filter");
1296 if (fsl_ssi_is_ac97(ssi_private
)) {
1297 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_ac97_dai
,
1298 sizeof(fsl_ssi_ac97_dai
));
1300 fsl_ac97_data
= ssi_private
;
1302 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops
, pdev
);
1304 /* Initialize this copy of the CPU DAI driver structure */
1305 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_dai_template
,
1306 sizeof(fsl_ssi_dai_template
));
1308 ssi_private
->cpu_dai_drv
.name
= dev_name(&pdev
->dev
);
1310 /* Get the addresses and IRQ */
1311 ret
= of_address_to_resource(np
, 0, &res
);
1313 dev_err(&pdev
->dev
, "could not determine device resources\n");
1316 ssi_private
->ssi_phys
= res
.start
;
1318 iomem
= devm_ioremap(&pdev
->dev
, res
.start
, resource_size(&res
));
1320 dev_err(&pdev
->dev
, "could not map device resources\n");
1324 ssi_private
->regs
= devm_regmap_init_mmio(&pdev
->dev
, iomem
,
1325 &fsl_ssi_regconfig
);
1326 if (IS_ERR(ssi_private
->regs
)) {
1327 dev_err(&pdev
->dev
, "Failed to init register map\n");
1328 return PTR_ERR(ssi_private
->regs
);
1331 ssi_private
->irq
= irq_of_parse_and_map(np
, 0);
1332 if (!ssi_private
->irq
) {
1333 dev_err(&pdev
->dev
, "no irq for node %s\n", np
->full_name
);
1337 /* Are the RX and the TX clocks locked? */
1338 if (!of_find_property(np
, "fsl,ssi-asynchronous", NULL
)) {
1339 ssi_private
->cpu_dai_drv
.symmetric_rates
= 1;
1340 ssi_private
->cpu_dai_drv
.symmetric_channels
= 1;
1341 ssi_private
->cpu_dai_drv
.symmetric_samplebits
= 1;
1344 /* Determine the FIFO depth. */
1345 iprop
= of_get_property(np
, "fsl,fifo-depth", NULL
);
1347 ssi_private
->fifo_depth
= be32_to_cpup(iprop
);
1349 /* Older 8610 DTs didn't have the fifo-depth property */
1350 ssi_private
->fifo_depth
= 8;
1352 dev_set_drvdata(&pdev
->dev
, ssi_private
);
1354 if (ssi_private
->soc
->imx
) {
1355 ret
= fsl_ssi_imx_probe(pdev
, ssi_private
, iomem
);
1360 ret
= snd_soc_register_component(&pdev
->dev
, &fsl_ssi_component
,
1361 &ssi_private
->cpu_dai_drv
, 1);
1363 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1364 goto error_asoc_register
;
1367 if (ssi_private
->use_dma
) {
1368 ret
= devm_request_irq(&pdev
->dev
, ssi_private
->irq
,
1369 fsl_ssi_isr
, 0, dev_name(&pdev
->dev
),
1372 dev_err(&pdev
->dev
, "could not claim irq %u\n",
1378 ret
= fsl_ssi_debugfs_create(&ssi_private
->dbg_stats
, &pdev
->dev
);
1380 goto error_asoc_register
;
1383 * If codec-handle property is missing from SSI node, we assume
1384 * that the machine driver uses new binding which does not require
1385 * SSI driver to trigger machine driver's probe.
1387 if (!of_get_property(np
, "codec-handle", NULL
))
1390 /* Trigger the machine driver's probe function. The platform driver
1391 * name of the machine driver is taken from /compatible property of the
1392 * device tree. We also pass the address of the CPU DAI driver
1395 sprop
= of_get_property(of_find_node_by_path("/"), "compatible", NULL
);
1396 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1397 p
= strrchr(sprop
, ',');
1400 snprintf(name
, sizeof(name
), "snd-soc-%s", sprop
);
1401 make_lowercase(name
);
1404 platform_device_register_data(&pdev
->dev
, name
, 0, NULL
, 0);
1405 if (IS_ERR(ssi_private
->pdev
)) {
1406 ret
= PTR_ERR(ssi_private
->pdev
);
1407 dev_err(&pdev
->dev
, "failed to register platform: %d\n", ret
);
1408 goto error_sound_card
;
1412 if (ssi_private
->dai_fmt
)
1413 _fsl_ssi_set_dai_fmt(ssi_private
, ssi_private
->dai_fmt
);
1418 fsl_ssi_debugfs_remove(&ssi_private
->dbg_stats
);
1421 snd_soc_unregister_component(&pdev
->dev
);
1423 error_asoc_register
:
1424 if (ssi_private
->soc
->imx
)
1425 fsl_ssi_imx_clean(pdev
, ssi_private
);
1428 if (ssi_private
->use_dma
)
1429 irq_dispose_mapping(ssi_private
->irq
);
1434 static int fsl_ssi_remove(struct platform_device
*pdev
)
1436 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(&pdev
->dev
);
1438 fsl_ssi_debugfs_remove(&ssi_private
->dbg_stats
);
1440 if (ssi_private
->pdev
)
1441 platform_device_unregister(ssi_private
->pdev
);
1442 snd_soc_unregister_component(&pdev
->dev
);
1444 if (ssi_private
->soc
->imx
)
1445 fsl_ssi_imx_clean(pdev
, ssi_private
);
1447 if (ssi_private
->use_dma
)
1448 irq_dispose_mapping(ssi_private
->irq
);
1453 static struct platform_driver fsl_ssi_driver
= {
1455 .name
= "fsl-ssi-dai",
1456 .owner
= THIS_MODULE
,
1457 .of_match_table
= fsl_ssi_ids
,
1459 .probe
= fsl_ssi_probe
,
1460 .remove
= fsl_ssi_remove
,
1463 module_platform_driver(fsl_ssi_driver
);
1465 MODULE_ALIAS("platform:fsl-ssi-dai");
1466 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1467 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1468 MODULE_LICENSE("GPL v2");