sound/soc/fsl/fsl_ssi.c

   1 /*
   2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
   3  *
   4  * Author: Timur Tabi <timur@freescale.com>
   5  *
   6  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/clk.h>
  18 #include <linux/device.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/initval.h>
  29 #include <sound/soc.h>
  30
  31 #include "fsl_ssi.h"
  32 #include "imx-pcm.h"
  33
  34 #ifdef PPC
  35 #define read_ssi(addr)                   in_be32(addr)
  36 #define write_ssi(val, addr)             out_be32(addr, val)
  37 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
  38 #elif defined ARM
  39 #define read_ssi(addr)                   readl(addr)
  40 #define write_ssi(val, addr)             writel(val, addr)
  41 /*
  42  * FIXME: Proper locking should be added at write_ssi_mask caller level
  43  * to ensure this register read/modify/write sequence is race free.
  44  */
  45 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
  46 {
  47         u32 val = readl(addr);
  48         val = (val & ~clear) | set;
  49         writel(val, addr);
  50 }
  51 #endif
  52
  53 /**
  54  * FSLSSI_I2S_RATES: sample rates supported by the I2S
  55  *
  56  * This driver currently only supports the SSI running in I2S slave mode,
  57  * which means the codec determines the sample rate.  Therefore, we tell
  58  * ALSA that we support all rates and let the codec driver decide what rates
  59  * are really supported.
  60  */
  61 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
  62                           SNDRV_PCM_RATE_CONTINUOUS)
  63
  64 /**
  65  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
  66  *
  67  * This driver currently only supports the SSI running in I2S slave mode.
  68  *
  69  * The SSI has a limitation in that the samples must be in the same byte
  70  * order as the host CPU.  This is because when multiple bytes are written
  71  * to the STX register, the bytes and bits must be written in the same
  72  * order.  The STX is a shift register, so all the bits need to be aligned
  73  * (bit-endianness must match byte-endianness).  Processors typically write
  74  * the bits within a byte in the same order that the bytes of a word are
  75  * written in.  So if the host CPU is big-endian, then only big-endian
  76  * samples will be written to STX properly.
  77  */
  78 #ifdef __BIG_ENDIAN
  79 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
  80          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
  81          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
  82 #else
  83 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
  84          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  85          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
  86 #endif
  87
  88 /* SIER bitflag of interrupts to enable */
  89 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
  90                     CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
  91                     CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
  92                     CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
  93                     CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
  94
  95 /**
  96  * fsl_ssi_private: per-SSI private data
  97  *
  98  * @ssi: pointer to the SSI's registers
  99  * @ssi_phys: physical address of the SSI registers
 100  * @irq: IRQ of this SSI
 101  * @first_stream: pointer to the stream that was opened first
 102  * @second_stream: pointer to second stream
 103  * @playback: the number of playback streams opened
 104  * @capture: the number of capture streams opened
 105  * @cpu_dai: the CPU DAI for this device
 106  * @dev_attr: the sysfs device attribute structure
 107  * @stats: SSI statistics
 108  * @name: name for this device
 109  */
 110 struct fsl_ssi_private {
 111         struct ccsr_ssi __iomem *ssi;
 112         dma_addr_t ssi_phys;
 113         unsigned int irq;
 114         struct snd_pcm_substream *first_stream;
 115         struct snd_pcm_substream *second_stream;
 116         unsigned int fifo_depth;
 117         struct snd_soc_dai_driver cpu_dai_drv;
 118         struct device_attribute dev_attr;
 119         struct platform_device *pdev;
 120
 121         bool new_binding;
 122         bool ssi_on_imx;
 123         struct clk *clk;
 124         struct platform_device *imx_pcm_pdev;
 125         struct imx_pcm_dma_params dma_params_tx;
 126         struct imx_pcm_dma_params dma_params_rx;
 127
 128         struct {
 129                 unsigned int rfrc;
 130                 unsigned int tfrc;
 131                 unsigned int cmdau;
 132                 unsigned int cmddu;
 133                 unsigned int rxt;
 134                 unsigned int rdr1;
 135                 unsigned int rdr0;
 136                 unsigned int tde1;
 137                 unsigned int tde0;
 138                 unsigned int roe1;
 139                 unsigned int roe0;
 140                 unsigned int tue1;
 141                 unsigned int tue0;
 142                 unsigned int tfs;
 143                 unsigned int rfs;
 144                 unsigned int tls;
 145                 unsigned int rls;
 146                 unsigned int rff1;
 147                 unsigned int rff0;
 148                 unsigned int tfe1;
 149                 unsigned int tfe0;
 150         } stats;
 151
 152         char name[1];
 153 };
 154
 155 /**
 156  * fsl_ssi_isr: SSI interrupt handler
 157  *
 158  * Although it's possible to use the interrupt handler to send and receive
 159  * data to/from the SSI, we use the DMA instead.  Programming is more
 160  * complicated, but the performance is much better.
 161  *
 162  * This interrupt handler is used only to gather statistics.
 163  *
 164  * @irq: IRQ of the SSI device
 165  * @dev_id: pointer to the ssi_private structure for this SSI device
 166  */
 167 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 168 {
 169         struct fsl_ssi_private *ssi_private = dev_id;
 170         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 171         irqreturn_t ret = IRQ_NONE;
 172         __be32 sisr;
 173         __be32 sisr2 = 0;
 174
 175         /* We got an interrupt, so read the status register to see what we
 176            were interrupted for.  We mask it with the Interrupt Enable register
 177            so that we only check for events that we're interested in.
 178          */
 179         sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
 180
 181         if (sisr & CCSR_SSI_SISR_RFRC) {
 182                 ssi_private->stats.rfrc++;
 183                 sisr2 |= CCSR_SSI_SISR_RFRC;
 184                 ret = IRQ_HANDLED;
 185         }
 186
 187         if (sisr & CCSR_SSI_SISR_TFRC) {
 188                 ssi_private->stats.tfrc++;
 189                 sisr2 |= CCSR_SSI_SISR_TFRC;
 190                 ret = IRQ_HANDLED;
 191         }
 192
 193         if (sisr & CCSR_SSI_SISR_CMDAU) {
 194                 ssi_private->stats.cmdau++;
 195                 ret = IRQ_HANDLED;
 196         }
 197
 198         if (sisr & CCSR_SSI_SISR_CMDDU) {
 199                 ssi_private->stats.cmddu++;
 200                 ret = IRQ_HANDLED;
 201         }
 202
 203         if (sisr & CCSR_SSI_SISR_RXT) {
 204                 ssi_private->stats.rxt++;
 205                 ret = IRQ_HANDLED;
 206         }
 207
 208         if (sisr & CCSR_SSI_SISR_RDR1) {
 209                 ssi_private->stats.rdr1++;
 210                 ret = IRQ_HANDLED;
 211         }
 212
 213         if (sisr & CCSR_SSI_SISR_RDR0) {
 214                 ssi_private->stats.rdr0++;
 215                 ret = IRQ_HANDLED;
 216         }
 217
 218         if (sisr & CCSR_SSI_SISR_TDE1) {
 219                 ssi_private->stats.tde1++;
 220                 ret = IRQ_HANDLED;
 221         }
 222
 223         if (sisr & CCSR_SSI_SISR_TDE0) {
 224                 ssi_private->stats.tde0++;
 225                 ret = IRQ_HANDLED;
 226         }
 227
 228         if (sisr & CCSR_SSI_SISR_ROE1) {
 229                 ssi_private->stats.roe1++;
 230                 sisr2 |= CCSR_SSI_SISR_ROE1;
 231                 ret = IRQ_HANDLED;
 232         }
 233
 234         if (sisr & CCSR_SSI_SISR_ROE0) {
 235                 ssi_private->stats.roe0++;
 236                 sisr2 |= CCSR_SSI_SISR_ROE0;
 237                 ret = IRQ_HANDLED;
 238         }
 239
 240         if (sisr & CCSR_SSI_SISR_TUE1) {
 241                 ssi_private->stats.tue1++;
 242                 sisr2 |= CCSR_SSI_SISR_TUE1;
 243                 ret = IRQ_HANDLED;
 244         }
 245
 246         if (sisr & CCSR_SSI_SISR_TUE0) {
 247                 ssi_private->stats.tue0++;
 248                 sisr2 |= CCSR_SSI_SISR_TUE0;
 249                 ret = IRQ_HANDLED;
 250         }
 251
 252         if (sisr & CCSR_SSI_SISR_TFS) {
 253                 ssi_private->stats.tfs++;
 254                 ret = IRQ_HANDLED;
 255         }
 256
 257         if (sisr & CCSR_SSI_SISR_RFS) {
 258                 ssi_private->stats.rfs++;
 259                 ret = IRQ_HANDLED;
 260         }
 261
 262         if (sisr & CCSR_SSI_SISR_TLS) {
 263                 ssi_private->stats.tls++;
 264                 ret = IRQ_HANDLED;
 265         }
 266
 267         if (sisr & CCSR_SSI_SISR_RLS) {
 268                 ssi_private->stats.rls++;
 269                 ret = IRQ_HANDLED;
 270         }
 271
 272         if (sisr & CCSR_SSI_SISR_RFF1) {
 273                 ssi_private->stats.rff1++;
 274                 ret = IRQ_HANDLED;
 275         }
 276
 277         if (sisr & CCSR_SSI_SISR_RFF0) {
 278                 ssi_private->stats.rff0++;
 279                 ret = IRQ_HANDLED;
 280         }
 281
 282         if (sisr & CCSR_SSI_SISR_TFE1) {
 283                 ssi_private->stats.tfe1++;
 284                 ret = IRQ_HANDLED;
 285         }
 286
 287         if (sisr & CCSR_SSI_SISR_TFE0) {
 288                 ssi_private->stats.tfe0++;
 289                 ret = IRQ_HANDLED;
 290         }
 291
 292         /* Clear the bits that we set */
 293         if (sisr2)
 294                 write_ssi(sisr2, &ssi->sisr);
 295
 296         return ret;
 297 }
 298
 299 /**
 300  * fsl_ssi_startup: create a new substream
 301  *
 302  * This is the first function called when a stream is opened.
 303  *
 304  * If this is the first stream open, then grab the IRQ and program most of
 305  * the SSI registers.
 306  */
 307 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 308                            struct snd_soc_dai *dai)
 309 {
 310         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 311         struct fsl_ssi_private *ssi_private =
 312                 snd_soc_dai_get_drvdata(rtd->cpu_dai);
 313         int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
 314
 315         /*
 316          * If this is the first stream opened, then request the IRQ
 317          * and initialize the SSI registers.
 318          */
 319         if (!ssi_private->first_stream) {
 320                 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 321
 322                 ssi_private->first_stream = substream;
 323
 324                 /*
 325                  * Section 16.5 of the MPC8610 reference manual says that the
 326                  * SSI needs to be disabled before updating the registers we set
 327                  * here.
 328                  */
 329                 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 330
 331                 /*
 332                  * Program the SSI into I2S Slave Non-Network Synchronous mode.
 333                  * Also enable the transmit and receive FIFO.
 334                  *
 335                  * FIXME: Little-endian samples require a different shift dir
 336                  */
 337                 write_ssi_mask(&ssi->scr,
 338                         CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
 339                         CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
 340                         | (synchronous ? CCSR_SSI_SCR_SYN : 0));
 341
 342                 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
 343                          CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
 344                          CCSR_SSI_STCR_TSCKP, &ssi->stcr);
 345
 346                 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
 347                          CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
 348                          CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
 349
 350                 /*
 351                  * The DC and PM bits are only used if the SSI is the clock
 352                  * master.
 353                  */
 354
 355                 /* Enable the interrupts and DMA requests */
 356                 write_ssi(SIER_FLAGS, &ssi->sier);
 357
 358                 /*
 359                  * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
 360                  * don't use FIFO 1.  We program the transmit water to signal a
 361                  * DMA transfer if there are only two (or fewer) elements left
 362                  * in the FIFO.  Two elements equals one frame (left channel,
 363                  * right channel).  This value, however, depends on the depth of
 364                  * the transmit buffer.
 365                  *
 366                  * We program the receive FIFO to notify us if at least two
 367                  * elements (one frame) have been written to the FIFO.  We could
 368                  * make this value larger (and maybe we should), but this way
 369                  * data will be written to memory as soon as it's available.
 370                  */
 371                 write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
 372                         CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
 373                         &ssi->sfcsr);
 374
 375                 /*
 376                  * We keep the SSI disabled because if we enable it, then the
 377                  * DMA controller will start.  It's not supposed to start until
 378                  * the SCR.TE (or SCR.RE) bit is set, but it does anyway.  The
 379                  * DMA controller will transfer one "BWC" of data (i.e. the
 380                  * amount of data that the MR.BWC bits are set to).  The reason
 381                  * this is bad is because at this point, the PCM driver has not
 382                  * finished initializing the DMA controller.
 383                  */
 384         } else {
 385                 if (synchronous) {
 386                         struct snd_pcm_runtime *first_runtime =
 387                                 ssi_private->first_stream->runtime;
 388                         /*
 389                          * This is the second stream open, and we're in
 390                          * synchronous mode, so we need to impose sample
 391                          * sample size constraints. This is because STCCR is
 392                          * used for playback and capture in synchronous mode,
 393                          * so there's no way to specify different word
 394                          * lengths.
 395                          *
 396                          * Note that this can cause a race condition if the
 397                          * second stream is opened before the first stream is
 398                          * fully initialized.  We provide some protection by
 399                          * checking to make sure the first stream is
 400                          * initialized, but it's not perfect.  ALSA sometimes
 401                          * re-initializes the driver with a different sample
 402                          * rate or size.  If the second stream is opened
 403                          * before the first stream has received its final
 404                          * parameters, then the second stream may be
 405                          * constrained to the wrong sample rate or size.
 406                          */
 407                         if (!first_runtime->sample_bits) {
 408                                 dev_err(substream->pcm->card->dev,
 409                                         "set sample size in %s stream first\n",
 410                                         substream->stream ==
 411                                         SNDRV_PCM_STREAM_PLAYBACK
 412                                         ? "capture" : "playback");
 413                                 return -EAGAIN;
 414                         }
 415
 416                         snd_pcm_hw_constraint_minmax(substream->runtime,
 417                                 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
 418                                 first_runtime->sample_bits,
 419                                 first_runtime->sample_bits);
 420                 }
 421
 422                 ssi_private->second_stream = substream;
 423         }
 424
 425         if (ssi_private->ssi_on_imx)
 426                 snd_soc_dai_set_dma_data(dai, substream,
 427                         (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
 428                                 &ssi_private->dma_params_tx :
 429                                 &ssi_private->dma_params_rx);
 430
 431         return 0;
 432 }
 433
 434 /**
 435  * fsl_ssi_hw_params - program the sample size
 436  *
 437  * Most of the SSI registers have been programmed in the startup function,
 438  * but the word length must be programmed here.  Unfortunately, programming
 439  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
 440  * cause a problem with supporting simultaneous playback and capture.  If
 441  * the SSI is already playing a stream, then that stream may be temporarily
 442  * stopped when you start capture.
 443  *
 444  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
 445  * clock master.
 446  */
 447 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 448         struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
 449 {
 450         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
 451         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 452         unsigned int sample_size =
 453                 snd_pcm_format_width(params_format(hw_params));
 454         u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
 455         int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
 456
 457         /*
 458          * If we're in synchronous mode, and the SSI is already enabled,
 459          * then STCCR is already set properly.
 460          */
 461         if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
 462                 return 0;
 463
 464         /*
 465          * FIXME: The documentation says that SxCCR[WL] should not be
 466          * modified while the SSI is enabled.  The only time this can
 467          * happen is if we're trying to do simultaneous playback and
 468          * capture in asynchronous mode.  Unfortunately, I have been enable
 469          * to get that to work at all on the P1022DS.  Therefore, we don't
 470          * bother to disable/enable the SSI when setting SxCCR[WL], because
 471          * the SSI will stop anyway.  Maybe one day, this will get fixed.
 472          */
 473
 474         /* In synchronous mode, the SSI uses STCCR for capture */
 475         if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
 476             ssi_private->cpu_dai_drv.symmetric_rates)
 477                 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 478         else
 479                 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 480
 481         return 0;
 482 }
 483
 484 /**
 485  * fsl_ssi_trigger: start and stop the DMA transfer.
 486  *
 487  * This function is called by ALSA to start, stop, pause, and resume the DMA
 488  * transfer of data.
 489  *
 490  * The DMA channel is in external master start and pause mode, which
 491  * means the SSI completely controls the flow of data.
 492  */
 493 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
 494                            struct snd_soc_dai *dai)
 495 {
 496         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 497         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
 498         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 499
 500         switch (cmd) {
 501         case SNDRV_PCM_TRIGGER_START:
 502         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 503                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 504                         write_ssi_mask(&ssi->scr, 0,
 505                                 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
 506                 else
 507                         write_ssi_mask(&ssi->scr, 0,
 508                                 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
 509                 break;
 510
 511         case SNDRV_PCM_TRIGGER_STOP:
 512         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 513                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 514                         write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
 515                 else
 516                         write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
 517                 break;
 518
 519         default:
 520                 return -EINVAL;
 521         }
 522
 523         return 0;
 524 }
 525
 526 /**
 527  * fsl_ssi_shutdown: shutdown the SSI
 528  *
 529  * Shutdown the SSI if there are no other substreams open.
 530  */
 531 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 532                              struct snd_soc_dai *dai)
 533 {
 534         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 535         struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
 536
 537         if (ssi_private->first_stream == substream)
 538                 ssi_private->first_stream = ssi_private->second_stream;
 539
 540         ssi_private->second_stream = NULL;
 541
 542         /*
 543          * If this is the last active substream, disable the SSI.
 544          */
 545         if (!ssi_private->first_stream) {
 546                 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 547
 548                 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 549         }
 550 }
 551
 552 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
 553         .startup        = fsl_ssi_startup,
 554         .hw_params      = fsl_ssi_hw_params,
 555         .shutdown       = fsl_ssi_shutdown,
 556         .trigger        = fsl_ssi_trigger,
 557 };
 558
 559 /* Template for the CPU dai driver structure */
 560 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
 561         .playback = {
 562                 /* The SSI does not support monaural audio. */
 563                 .channels_min = 2,
 564                 .channels_max = 2,
 565                 .rates = FSLSSI_I2S_RATES,
 566                 .formats = FSLSSI_I2S_FORMATS,
 567         },
 568         .capture = {
 569                 .channels_min = 2,
 570                 .channels_max = 2,
 571                 .rates = FSLSSI_I2S_RATES,
 572                 .formats = FSLSSI_I2S_FORMATS,
 573         },
 574         .ops = &fsl_ssi_dai_ops,
 575 };
 576
 577 /* Show the statistics of a flag only if its interrupt is enabled.  The
 578  * compiler will optimze this code to a no-op if the interrupt is not
 579  * enabled.
 580  */
 581 #define SIER_SHOW(flag, name) \
 582         do { \
 583                 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
 584                         length += sprintf(buf + length, #name "=%u\n", \
 585                                 ssi_private->stats.name); \
 586         } while (0)
 587
 588
 589 /**
 590  * fsl_sysfs_ssi_show: display SSI statistics
 591  *
 592  * Display the statistics for the current SSI device.  To avoid confusion,
 593  * we only show those counts that are enabled.
 594  */
 595 static ssize_t fsl_sysfs_ssi_show(struct device *dev,
 596         struct device_attribute *attr, char *buf)
 597 {
 598         struct fsl_ssi_private *ssi_private =
 599                 container_of(attr, struct fsl_ssi_private, dev_attr);
 600         ssize_t length = 0;
 601
 602         SIER_SHOW(RFRC_EN, rfrc);
 603         SIER_SHOW(TFRC_EN, tfrc);
 604         SIER_SHOW(CMDAU_EN, cmdau);
 605         SIER_SHOW(CMDDU_EN, cmddu);
 606         SIER_SHOW(RXT_EN, rxt);
 607         SIER_SHOW(RDR1_EN, rdr1);
 608         SIER_SHOW(RDR0_EN, rdr0);
 609         SIER_SHOW(TDE1_EN, tde1);
 610         SIER_SHOW(TDE0_EN, tde0);
 611         SIER_SHOW(ROE1_EN, roe1);
 612         SIER_SHOW(ROE0_EN, roe0);
 613         SIER_SHOW(TUE1_EN, tue1);
 614         SIER_SHOW(TUE0_EN, tue0);
 615         SIER_SHOW(TFS_EN, tfs);
 616         SIER_SHOW(RFS_EN, rfs);
 617         SIER_SHOW(TLS_EN, tls);
 618         SIER_SHOW(RLS_EN, rls);
 619         SIER_SHOW(RFF1_EN, rff1);
 620         SIER_SHOW(RFF0_EN, rff0);
 621         SIER_SHOW(TFE1_EN, tfe1);
 622         SIER_SHOW(TFE0_EN, tfe0);
 623
 624         return length;
 625 }
 626
 627 /**
 628  * Make every character in a string lower-case
 629  */
 630 static void make_lowercase(char *s)
 631 {
 632         char *p = s;
 633         char c;
 634
 635         while ((c = *p)) {
 636                 if ((c >= 'A') && (c <= 'Z'))
 637                         *p = c + ('a' - 'A');
 638                 p++;
 639         }
 640 }
 641
 642 static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 643 {
 644         struct fsl_ssi_private *ssi_private;
 645         int ret = 0;
 646         struct device_attribute *dev_attr = NULL;
 647         struct device_node *np = pdev->dev.of_node;
 648         const char *p, *sprop;
 649         const uint32_t *iprop;
 650         struct resource res;
 651         char name[64];
 652
 653         /* SSIs that are not connected on the board should have a
 654          *      status = "disabled"
 655          * property in their device tree nodes.
 656          */
 657         if (!of_device_is_available(np))
 658                 return -ENODEV;
 659
 660         /* We only support the SSI in "I2S Slave" mode */
 661         sprop = of_get_property(np, "fsl,mode", NULL);
 662         if (!sprop || strcmp(sprop, "i2s-slave")) {
 663                 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
 664                 return -ENODEV;
 665         }
 666
 667         /* The DAI name is the last part of the full name of the node. */
 668         p = strrchr(np->full_name, '/') + 1;
 669         ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p),
 670                               GFP_KERNEL);
 671         if (!ssi_private) {
 672                 dev_err(&pdev->dev, "could not allocate DAI object\n");
 673                 return -ENOMEM;
 674         }
 675
 676         strcpy(ssi_private->name, p);
 677
 678         /* Initialize this copy of the CPU DAI driver structure */
 679         memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
 680                sizeof(fsl_ssi_dai_template));
 681         ssi_private->cpu_dai_drv.name = ssi_private->name;
 682
 683         /* Get the addresses and IRQ */
 684         ret = of_address_to_resource(np, 0, &res);
 685         if (ret) {
 686                 dev_err(&pdev->dev, "could not determine device resources\n");
 687                 goto error_kmalloc;
 688         }
 689         ssi_private->ssi = of_iomap(np, 0);
 690         if (!ssi_private->ssi) {
 691                 dev_err(&pdev->dev, "could not map device resources\n");
 692                 ret = -ENOMEM;
 693                 goto error_kmalloc;
 694         }
 695         ssi_private->ssi_phys = res.start;
 696
 697         ssi_private->irq = irq_of_parse_and_map(np, 0);
 698         if (ssi_private->irq == NO_IRQ) {
 699                 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
 700                 ret = -ENXIO;
 701                 goto error_iomap;
 702         }
 703
 704         /* The 'name' should not have any slashes in it. */
 705         ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name,
 706                           ssi_private);
 707         if (ret < 0) {
 708                 dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq);
 709                 goto error_irqmap;
 710         }
 711
 712         /* Are the RX and the TX clocks locked? */
 713         if (!of_find_property(np, "fsl,ssi-asynchronous", NULL))
 714                 ssi_private->cpu_dai_drv.symmetric_rates = 1;
 715
 716         /* Determine the FIFO depth. */
 717         iprop = of_get_property(np, "fsl,fifo-depth", NULL);
 718         if (iprop)
 719                 ssi_private->fifo_depth = be32_to_cpup(iprop);
 720         else
 721                 /* Older 8610 DTs didn't have the fifo-depth property */
 722                 ssi_private->fifo_depth = 8;
 723
 724         if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
 725                 u32 dma_events[2];
 726                 ssi_private->ssi_on_imx = true;
 727
 728                 ssi_private->clk = clk_get(&pdev->dev, NULL);
 729                 if (IS_ERR(ssi_private->clk)) {
 730                         ret = PTR_ERR(ssi_private->clk);
 731                         dev_err(&pdev->dev, "could not get clock: %d\n", ret);
 732                         goto error_irq;
 733                 }
 734                 clk_prepare_enable(ssi_private->clk);
 735
 736                 /*
 737                  * We have burstsize be "fifo_depth - 2" to match the SSI
 738                  * watermark setting in fsl_ssi_startup().
 739                  */
 740                 ssi_private->dma_params_tx.burstsize =
 741                         ssi_private->fifo_depth - 2;
 742                 ssi_private->dma_params_rx.burstsize =
 743                         ssi_private->fifo_depth - 2;
 744                 ssi_private->dma_params_tx.dma_addr =
 745                         ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
 746                 ssi_private->dma_params_rx.dma_addr =
 747                         ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
 748                 /*
 749                  * TODO: This is a temporary solution and should be changed
 750                  * to use generic DMA binding later when the helplers get in.
 751                  */
 752                 ret = of_property_read_u32_array(pdev->dev.of_node,
 753                                         "fsl,ssi-dma-events", dma_events, 2);
 754                 if (ret) {
 755                         dev_err(&pdev->dev, "could not get dma events\n");
 756                         goto error_clk;
 757                 }
 758                 ssi_private->dma_params_tx.dma = dma_events[0];
 759                 ssi_private->dma_params_rx.dma = dma_events[1];
 760
 761                 ssi_private->dma_params_tx.shared_peripheral =
 762                                 of_device_is_compatible(of_get_parent(np),
 763                                                         "fsl,spba-bus");
 764                 ssi_private->dma_params_rx.shared_peripheral =
 765                                 ssi_private->dma_params_tx.shared_peripheral;
 766         }
 767
 768         /* Initialize the the device_attribute structure */
 769         dev_attr = &ssi_private->dev_attr;
 770         sysfs_attr_init(&dev_attr->attr);
 771         dev_attr->attr.name = "statistics";
 772         dev_attr->attr.mode = S_IRUGO;
 773         dev_attr->show = fsl_sysfs_ssi_show;
 774
 775         ret = device_create_file(&pdev->dev, dev_attr);
 776         if (ret) {
 777                 dev_err(&pdev->dev, "could not create sysfs %s file\n",
 778                         ssi_private->dev_attr.attr.name);
 779                 goto error_irq;
 780         }
 781
 782         /* Register with ASoC */
 783         dev_set_drvdata(&pdev->dev, ssi_private);
 784
 785         ret = snd_soc_register_dai(&pdev->dev, &ssi_private->cpu_dai_drv);
 786         if (ret) {
 787                 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
 788                 goto error_dev;
 789         }
 790
 791         if (ssi_private->ssi_on_imx) {
 792                 ssi_private->imx_pcm_pdev =
 793                         platform_device_register_simple("imx-pcm-audio",
 794                                                         -1, NULL, 0);
 795                 if (IS_ERR(ssi_private->imx_pcm_pdev)) {
 796                         ret = PTR_ERR(ssi_private->imx_pcm_pdev);
 797                         goto error_dev;
 798                 }
 799         }
 800
 801         /*
 802          * If codec-handle property is missing from SSI node, we assume
 803          * that the machine driver uses new binding which does not require
 804          * SSI driver to trigger machine driver's probe.
 805          */
 806         if (!of_get_property(np, "codec-handle", NULL)) {
 807                 ssi_private->new_binding = true;
 808                 goto done;
 809         }
 810
 811         /* Trigger the machine driver's probe function.  The platform driver
 812          * name of the machine driver is taken from /compatible property of the
 813          * device tree.  We also pass the address of the CPU DAI driver
 814          * structure.
 815          */
 816         sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
 817         /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
 818         p = strrchr(sprop, ',');
 819         if (p)
 820                 sprop = p + 1;
 821         snprintf(name, sizeof(name), "snd-soc-%s", sprop);
 822         make_lowercase(name);
 823
 824         ssi_private->pdev =
 825                 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
 826         if (IS_ERR(ssi_private->pdev)) {
 827                 ret = PTR_ERR(ssi_private->pdev);
 828                 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
 829                 goto error_dai;
 830         }
 831
 832 done:
 833         return 0;
 834
 835 error_dai:
 836         if (ssi_private->ssi_on_imx)
 837                 platform_device_unregister(ssi_private->imx_pcm_pdev);
 838         snd_soc_unregister_dai(&pdev->dev);
 839
 840 error_dev:
 841         dev_set_drvdata(&pdev->dev, NULL);
 842         device_remove_file(&pdev->dev, dev_attr);
 843
 844 error_clk:
 845         if (ssi_private->ssi_on_imx) {
 846                 clk_disable_unprepare(ssi_private->clk);
 847                 clk_put(ssi_private->clk);
 848         }
 849
 850 error_irq:
 851         free_irq(ssi_private->irq, ssi_private);
 852
 853 error_irqmap:
 854         irq_dispose_mapping(ssi_private->irq);
 855
 856 error_iomap:
 857         iounmap(ssi_private->ssi);
 858
 859 error_kmalloc:
 860         kfree(ssi_private);
 861
 862         return ret;
 863 }
 864
 865 static int fsl_ssi_remove(struct platform_device *pdev)
 866 {
 867         struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
 868
 869         if (!ssi_private->new_binding)
 870                 platform_device_unregister(ssi_private->pdev);
 871         if (ssi_private->ssi_on_imx) {
 872                 platform_device_unregister(ssi_private->imx_pcm_pdev);
 873                 clk_disable_unprepare(ssi_private->clk);
 874                 clk_put(ssi_private->clk);
 875         }
 876         snd_soc_unregister_dai(&pdev->dev);
 877         device_remove_file(&pdev->dev, &ssi_private->dev_attr);
 878
 879         free_irq(ssi_private->irq, ssi_private);
 880         irq_dispose_mapping(ssi_private->irq);
 881
 882         kfree(ssi_private);
 883         dev_set_drvdata(&pdev->dev, NULL);
 884
 885         return 0;
 886 }
 887
 888 static const struct of_device_id fsl_ssi_ids[] = {
 889         { .compatible = "fsl,mpc8610-ssi", },
 890         { .compatible = "fsl,imx21-ssi", },
 891         {}
 892 };
 893 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
 894
 895 static struct platform_driver fsl_ssi_driver = {
 896         .driver = {
 897                 .name = "fsl-ssi-dai",
 898                 .owner = THIS_MODULE,
 899                 .of_match_table = fsl_ssi_ids,
 900         },
 901         .probe = fsl_ssi_probe,
 902         .remove = fsl_ssi_remove,
 903 };
 904
 905 module_platform_driver(fsl_ssi_driver);
 906
 907 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
 908 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
 909 MODULE_LICENSE("GPL v2");