2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/of_address.h>
43 #include <linux/of_irq.h>
44 #include <linux/of_platform.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/initval.h>
50 #include <sound/soc.h>
51 #include <sound/dmaengine_pcm.h>
57 #define read_ssi(addr) in_be32(addr)
58 #define write_ssi(val, addr) out_be32(addr, val)
59 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
61 #define read_ssi(addr) readl(addr)
62 #define write_ssi(val, addr) writel(val, addr)
64 * FIXME: Proper locking should be added at write_ssi_mask caller level
65 * to ensure this register read/modify/write sequence is race free.
67 static inline void write_ssi_mask(u32 __iomem
*addr
, u32 clear
, u32 set
)
69 u32 val
= readl(addr
);
70 val
= (val
& ~clear
) | set
;
76 * FSLSSI_I2S_RATES: sample rates supported by the I2S
78 * This driver currently only supports the SSI running in I2S slave mode,
79 * which means the codec determines the sample rate. Therefore, we tell
80 * ALSA that we support all rates and let the codec driver decide what rates
81 * are really supported.
83 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
84 SNDRV_PCM_RATE_CONTINUOUS)
87 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
89 * This driver currently only supports the SSI running in I2S slave mode.
91 * The SSI has a limitation in that the samples must be in the same byte
92 * order as the host CPU. This is because when multiple bytes are written
93 * to the STX register, the bytes and bits must be written in the same
94 * order. The STX is a shift register, so all the bits need to be aligned
95 * (bit-endianness must match byte-endianness). Processors typically write
96 * the bits within a byte in the same order that the bytes of a word are
97 * written in. So if the host CPU is big-endian, then only big-endian
98 * samples will be written to STX properly.
101 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
102 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
103 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
105 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
106 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
107 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
110 /* SIER bitflag of interrupts to enable */
111 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
112 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
113 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
114 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
115 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
118 * fsl_ssi_private: per-SSI private data
120 * @ssi: pointer to the SSI's registers
121 * @ssi_phys: physical address of the SSI registers
122 * @irq: IRQ of this SSI
123 * @playback: the number of playback streams opened
124 * @capture: the number of capture streams opened
125 * @cpu_dai: the CPU DAI for this device
126 * @dev_attr: the sysfs device attribute structure
127 * @stats: SSI statistics
128 * @name: name for this device
130 struct fsl_ssi_private
{
131 struct ccsr_ssi __iomem
*ssi
;
134 unsigned int fifo_depth
;
135 struct snd_soc_dai_driver cpu_dai_drv
;
136 struct device_attribute dev_attr
;
137 struct platform_device
*pdev
;
145 spinlock_t baudclk_lock
;
148 struct snd_dmaengine_dai_dma_data dma_params_tx
;
149 struct snd_dmaengine_dai_dma_data dma_params_rx
;
150 struct imx_dma_data filter_data_tx
;
151 struct imx_dma_data filter_data_rx
;
152 struct imx_pcm_fiq_params fiq_params
;
182 * fsl_ssi_isr: SSI interrupt handler
184 * Although it's possible to use the interrupt handler to send and receive
185 * data to/from the SSI, we use the DMA instead. Programming is more
186 * complicated, but the performance is much better.
188 * This interrupt handler is used only to gather statistics.
190 * @irq: IRQ of the SSI device
191 * @dev_id: pointer to the ssi_private structure for this SSI device
193 static irqreturn_t
fsl_ssi_isr(int irq
, void *dev_id
)
195 struct fsl_ssi_private
*ssi_private
= dev_id
;
196 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
197 irqreturn_t ret
= IRQ_NONE
;
201 /* We got an interrupt, so read the status register to see what we
202 were interrupted for. We mask it with the Interrupt Enable register
203 so that we only check for events that we're interested in.
205 sisr
= read_ssi(&ssi
->sisr
) & SIER_FLAGS
;
207 if (sisr
& CCSR_SSI_SISR_RFRC
) {
208 ssi_private
->stats
.rfrc
++;
209 sisr2
|= CCSR_SSI_SISR_RFRC
;
213 if (sisr
& CCSR_SSI_SISR_TFRC
) {
214 ssi_private
->stats
.tfrc
++;
215 sisr2
|= CCSR_SSI_SISR_TFRC
;
219 if (sisr
& CCSR_SSI_SISR_CMDAU
) {
220 ssi_private
->stats
.cmdau
++;
224 if (sisr
& CCSR_SSI_SISR_CMDDU
) {
225 ssi_private
->stats
.cmddu
++;
229 if (sisr
& CCSR_SSI_SISR_RXT
) {
230 ssi_private
->stats
.rxt
++;
234 if (sisr
& CCSR_SSI_SISR_RDR1
) {
235 ssi_private
->stats
.rdr1
++;
239 if (sisr
& CCSR_SSI_SISR_RDR0
) {
240 ssi_private
->stats
.rdr0
++;
244 if (sisr
& CCSR_SSI_SISR_TDE1
) {
245 ssi_private
->stats
.tde1
++;
249 if (sisr
& CCSR_SSI_SISR_TDE0
) {
250 ssi_private
->stats
.tde0
++;
254 if (sisr
& CCSR_SSI_SISR_ROE1
) {
255 ssi_private
->stats
.roe1
++;
256 sisr2
|= CCSR_SSI_SISR_ROE1
;
260 if (sisr
& CCSR_SSI_SISR_ROE0
) {
261 ssi_private
->stats
.roe0
++;
262 sisr2
|= CCSR_SSI_SISR_ROE0
;
266 if (sisr
& CCSR_SSI_SISR_TUE1
) {
267 ssi_private
->stats
.tue1
++;
268 sisr2
|= CCSR_SSI_SISR_TUE1
;
272 if (sisr
& CCSR_SSI_SISR_TUE0
) {
273 ssi_private
->stats
.tue0
++;
274 sisr2
|= CCSR_SSI_SISR_TUE0
;
278 if (sisr
& CCSR_SSI_SISR_TFS
) {
279 ssi_private
->stats
.tfs
++;
283 if (sisr
& CCSR_SSI_SISR_RFS
) {
284 ssi_private
->stats
.rfs
++;
288 if (sisr
& CCSR_SSI_SISR_TLS
) {
289 ssi_private
->stats
.tls
++;
293 if (sisr
& CCSR_SSI_SISR_RLS
) {
294 ssi_private
->stats
.rls
++;
298 if (sisr
& CCSR_SSI_SISR_RFF1
) {
299 ssi_private
->stats
.rff1
++;
303 if (sisr
& CCSR_SSI_SISR_RFF0
) {
304 ssi_private
->stats
.rff0
++;
308 if (sisr
& CCSR_SSI_SISR_TFE1
) {
309 ssi_private
->stats
.tfe1
++;
313 if (sisr
& CCSR_SSI_SISR_TFE0
) {
314 ssi_private
->stats
.tfe0
++;
318 /* Clear the bits that we set */
320 write_ssi(sisr2
, &ssi
->sisr
);
325 static void fsl_ssi_setup_ac97(struct fsl_ssi_private
*ssi_private
)
327 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
330 * Setup the clock control register
332 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
334 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
338 * Enable AC97 mode and startup the SSI
340 write_ssi(CCSR_SSI_SACNT_AC97EN
| CCSR_SSI_SACNT_FV
,
342 write_ssi(0xff, &ssi
->saccdis
);
343 write_ssi(0x300, &ssi
->saccen
);
346 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
347 * codec before a stream is started.
349 write_ssi_mask(&ssi
->scr
, 0, CCSR_SSI_SCR_SSIEN
|
350 CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
);
352 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi
->sor
);
355 static int fsl_ssi_setup(struct fsl_ssi_private
*ssi_private
)
357 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
359 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
;
361 if (ssi_private
->imx_ac97
)
362 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_NORMAL
| CCSR_SSI_SCR_NET
;
364 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
367 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
368 * to be disabled before updating the registers we set here.
370 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, 0);
373 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
374 * enable the transmit and receive FIFO.
376 * FIXME: Little-endian samples require a different shift dir
378 write_ssi_mask(&ssi
->scr
,
379 CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_SYN
,
380 CCSR_SSI_SCR_TFR_CLK_DIS
|
381 ssi_private
->i2s_mode
|
382 (synchronous
? CCSR_SSI_SCR_SYN
: 0));
384 write_ssi(CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFEN0
|
385 CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TEFS
|
386 CCSR_SSI_STCR_TSCKP
, &ssi
->stcr
);
388 write_ssi(CCSR_SSI_SRCR_RXBIT0
| CCSR_SSI_SRCR_RFEN0
|
389 CCSR_SSI_SRCR_RFSI
| CCSR_SSI_SRCR_REFS
|
390 CCSR_SSI_SRCR_RSCKP
, &ssi
->srcr
);
392 * The DC and PM bits are only used if the SSI is the clock master.
396 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
397 * use FIFO 1. We program the transmit water to signal a DMA transfer
398 * if there are only two (or fewer) elements left in the FIFO. Two
399 * elements equals one frame (left channel, right channel). This value,
400 * however, depends on the depth of the transmit buffer.
402 * We set the watermark on the same level as the DMA burstsize. For
403 * fiq it is probably better to use the biggest possible watermark
406 if (ssi_private
->use_dma
)
407 wm
= ssi_private
->fifo_depth
- 2;
409 wm
= ssi_private
->fifo_depth
;
411 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm
) | CCSR_SSI_SFCSR_RFWM0(wm
) |
412 CCSR_SSI_SFCSR_TFWM1(wm
) | CCSR_SSI_SFCSR_RFWM1(wm
),
416 * For ac97 interrupts are enabled with the startup of the substream
417 * because it is also running without an active substream. Normally SSI
418 * is only enabled when there is a substream.
420 if (ssi_private
->imx_ac97
)
421 fsl_ssi_setup_ac97(ssi_private
);
428 * fsl_ssi_startup: create a new substream
430 * This is the first function called when a stream is opened.
432 * If this is the first stream open, then grab the IRQ and program most of
435 static int fsl_ssi_startup(struct snd_pcm_substream
*substream
,
436 struct snd_soc_dai
*dai
)
438 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
439 struct fsl_ssi_private
*ssi_private
=
440 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
443 /* First, we only do fsl_ssi_setup() when SSI is going to be active.
444 * Second, fsl_ssi_setup was already called by ac97_init earlier if
445 * the driver is in ac97 mode.
447 if (!dai
->active
&& !ssi_private
->imx_ac97
) {
448 fsl_ssi_setup(ssi_private
);
449 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
450 ssi_private
->baudclk_locked
= false;
451 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
458 * fsl_ssi_hw_params - program the sample size
460 * Most of the SSI registers have been programmed in the startup function,
461 * but the word length must be programmed here. Unfortunately, programming
462 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
463 * cause a problem with supporting simultaneous playback and capture. If
464 * the SSI is already playing a stream, then that stream may be temporarily
465 * stopped when you start capture.
467 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
470 static int fsl_ssi_hw_params(struct snd_pcm_substream
*substream
,
471 struct snd_pcm_hw_params
*hw_params
, struct snd_soc_dai
*cpu_dai
)
473 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
474 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
475 unsigned int channels
= params_channels(hw_params
);
476 unsigned int sample_size
=
477 snd_pcm_format_width(params_format(hw_params
));
478 u32 wl
= CCSR_SSI_SxCCR_WL(sample_size
);
479 int enabled
= read_ssi(&ssi
->scr
) & CCSR_SSI_SCR_SSIEN
;
482 * If we're in synchronous mode, and the SSI is already enabled,
483 * then STCCR is already set properly.
485 if (enabled
&& ssi_private
->cpu_dai_drv
.symmetric_rates
)
489 * FIXME: The documentation says that SxCCR[WL] should not be
490 * modified while the SSI is enabled. The only time this can
491 * happen is if we're trying to do simultaneous playback and
492 * capture in asynchronous mode. Unfortunately, I have been enable
493 * to get that to work at all on the P1022DS. Therefore, we don't
494 * bother to disable/enable the SSI when setting SxCCR[WL], because
495 * the SSI will stop anyway. Maybe one day, this will get fixed.
498 /* In synchronous mode, the SSI uses STCCR for capture */
499 if ((substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) ||
500 ssi_private
->cpu_dai_drv
.symmetric_rates
)
501 write_ssi_mask(&ssi
->stccr
, CCSR_SSI_SxCCR_WL_MASK
, wl
);
503 write_ssi_mask(&ssi
->srccr
, CCSR_SSI_SxCCR_WL_MASK
, wl
);
505 if (!ssi_private
->imx_ac97
)
506 write_ssi_mask(&ssi
->scr
,
507 CCSR_SSI_SCR_NET
| CCSR_SSI_SCR_I2S_MODE_MASK
,
508 channels
== 1 ? 0 : ssi_private
->i2s_mode
);
514 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
516 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai
*cpu_dai
, unsigned int fmt
)
518 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
519 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
520 u32 strcr
= 0, stcr
, srcr
, scr
, mask
;
522 scr
= read_ssi(&ssi
->scr
) & ~(CCSR_SSI_SCR_SYN
| CCSR_SSI_SCR_I2S_MODE_MASK
);
523 scr
|= CCSR_SSI_SCR_NET
;
525 mask
= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
|
526 CCSR_SSI_STCR_TSCKP
| CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TFSL
|
528 stcr
= read_ssi(&ssi
->stcr
) & ~mask
;
529 srcr
= read_ssi(&ssi
->srcr
) & ~mask
;
531 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
532 case SND_SOC_DAIFMT_I2S
:
533 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
534 case SND_SOC_DAIFMT_CBS_CFS
:
535 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_MASTER
;
537 case SND_SOC_DAIFMT_CBM_CFM
:
538 ssi_private
->i2s_mode
= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
543 scr
|= ssi_private
->i2s_mode
;
545 /* Data on rising edge of bclk, frame low, 1clk before data */
546 strcr
|= CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TSCKP
|
547 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
549 case SND_SOC_DAIFMT_LEFT_J
:
550 /* Data on rising edge of bclk, frame high */
551 strcr
|= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TSCKP
;
553 case SND_SOC_DAIFMT_DSP_A
:
554 /* Data on rising edge of bclk, frame high, 1clk before data */
555 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
556 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
558 case SND_SOC_DAIFMT_DSP_B
:
559 /* Data on rising edge of bclk, frame high */
560 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
561 CCSR_SSI_STCR_TXBIT0
;
567 /* DAI clock inversion */
568 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
569 case SND_SOC_DAIFMT_NB_NF
:
570 /* Nothing to do for both normal cases */
572 case SND_SOC_DAIFMT_IB_NF
:
573 /* Invert bit clock */
574 strcr
^= CCSR_SSI_STCR_TSCKP
;
576 case SND_SOC_DAIFMT_NB_IF
:
577 /* Invert frame clock */
578 strcr
^= CCSR_SSI_STCR_TFSI
;
580 case SND_SOC_DAIFMT_IB_IF
:
581 /* Invert both clocks */
582 strcr
^= CCSR_SSI_STCR_TSCKP
;
583 strcr
^= CCSR_SSI_STCR_TFSI
;
589 /* DAI clock master masks */
590 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
591 case SND_SOC_DAIFMT_CBS_CFS
:
592 strcr
|= CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
;
593 scr
|= CCSR_SSI_SCR_SYS_CLK_EN
;
595 case SND_SOC_DAIFMT_CBM_CFM
:
596 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
605 if (ssi_private
->cpu_dai_drv
.symmetric_rates
) {
606 /* Need to clear RXDIR when using SYNC mode */
607 srcr
&= ~CCSR_SSI_SRCR_RXDIR
;
608 scr
|= CCSR_SSI_SCR_SYN
;
611 write_ssi(stcr
, &ssi
->stcr
);
612 write_ssi(srcr
, &ssi
->srcr
);
613 write_ssi(scr
, &ssi
->scr
);
619 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
621 * Note: This function can be only called when using SSI as DAI master
623 * Quick instruction for parameters:
624 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
625 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
627 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
628 int clk_id
, unsigned int freq
, int dir
)
630 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
631 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
632 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
, ret
;
633 u32 pm
= 999, div2
, psr
, stccr
, mask
, afreq
, factor
, i
;
634 unsigned long flags
, clkrate
, baudrate
, tmprate
;
635 u64 sub
, savesub
= 100000;
637 /* Don't apply it to any non-baudclk circumstance */
638 if (IS_ERR(ssi_private
->baudclk
))
641 /* It should be already enough to divide clock by setting pm alone */
645 factor
= (div2
+ 1) * (7 * psr
+ 1) * 2;
647 for (i
= 0; i
< 255; i
++) {
648 /* The bclk rate must be smaller than 1/5 sysclk rate */
649 if (factor
* (i
+ 1) < 5)
652 tmprate
= freq
* factor
* (i
+ 2);
653 clkrate
= clk_round_rate(ssi_private
->baudclk
, tmprate
);
655 do_div(clkrate
, factor
);
656 afreq
= (u32
)clkrate
/ (i
+ 1);
660 else if (freq
/ afreq
== 1)
662 else if (afreq
/ freq
== 1)
667 /* Calculate the fraction */
682 /* No proper pm found if it is still remaining the initial value */
684 dev_err(cpu_dai
->dev
, "failed to handle the required sysclk\n");
688 stccr
= CCSR_SSI_SxCCR_PM(pm
+ 1) | (div2
? CCSR_SSI_SxCCR_DIV2
: 0) |
689 (psr
? CCSR_SSI_SxCCR_PSR
: 0);
690 mask
= CCSR_SSI_SxCCR_PM_MASK
| CCSR_SSI_SxCCR_DIV2
| CCSR_SSI_SxCCR_PSR
;
692 if (dir
== SND_SOC_CLOCK_OUT
|| synchronous
)
693 write_ssi_mask(&ssi
->stccr
, mask
, stccr
);
695 write_ssi_mask(&ssi
->srccr
, mask
, stccr
);
697 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
698 if (!ssi_private
->baudclk_locked
) {
699 ret
= clk_set_rate(ssi_private
->baudclk
, baudrate
);
701 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
702 dev_err(cpu_dai
->dev
, "failed to set baudclk rate\n");
705 ssi_private
->baudclk_locked
= true;
707 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
713 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
715 * Note: This function can be only called when using SSI as DAI master
717 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
, u32 tx_mask
,
718 u32 rx_mask
, int slots
, int slot_width
)
720 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
721 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
724 /* The slot number should be >= 2 if using Network mode or I2S mode */
725 val
= read_ssi(&ssi
->scr
) & (CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_NET
);
726 if (val
&& slots
< 2) {
727 dev_err(cpu_dai
->dev
, "slot number should be >= 2 in I2S or NET\n");
731 write_ssi_mask(&ssi
->stccr
, CCSR_SSI_SxCCR_DC_MASK
,
732 CCSR_SSI_SxCCR_DC(slots
));
733 write_ssi_mask(&ssi
->srccr
, CCSR_SSI_SxCCR_DC_MASK
,
734 CCSR_SSI_SxCCR_DC(slots
));
736 /* The register SxMSKs needs SSI to provide essential clock due to
737 * hardware design. So we here temporarily enable SSI to set them.
739 val
= read_ssi(&ssi
->scr
) & CCSR_SSI_SCR_SSIEN
;
740 write_ssi_mask(&ssi
->scr
, 0, CCSR_SSI_SCR_SSIEN
);
742 write_ssi(tx_mask
, &ssi
->stmsk
);
743 write_ssi(rx_mask
, &ssi
->srmsk
);
745 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, val
);
751 * fsl_ssi_trigger: start and stop the DMA transfer.
753 * This function is called by ALSA to start, stop, pause, and resume the DMA
756 * The DMA channel is in external master start and pause mode, which
757 * means the SSI completely controls the flow of data.
759 static int fsl_ssi_trigger(struct snd_pcm_substream
*substream
, int cmd
,
760 struct snd_soc_dai
*dai
)
762 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
763 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
764 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
765 unsigned int sier_bits
;
769 * Enable only the interrupts and DMA requests
770 * that are needed for the channel. As the fiq
771 * is polling for this bits, we have to ensure
772 * that this are aligned with the preallocated
776 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
777 if (ssi_private
->use_dma
)
778 sier_bits
= SIER_FLAGS
;
780 sier_bits
= CCSR_SSI_SIER_TIE
| CCSR_SSI_SIER_TFE0_EN
;
782 if (ssi_private
->use_dma
)
783 sier_bits
= SIER_FLAGS
;
785 sier_bits
= CCSR_SSI_SIER_RIE
| CCSR_SSI_SIER_RFF0_EN
;
789 case SNDRV_PCM_TRIGGER_START
:
790 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
791 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
792 write_ssi_mask(&ssi
->scr
, 0,
793 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
);
795 write_ssi_mask(&ssi
->scr
, 0,
796 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_RE
);
799 case SNDRV_PCM_TRIGGER_STOP
:
800 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
801 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
802 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_TE
, 0);
804 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_RE
, 0);
806 if (!ssi_private
->imx_ac97
&& (read_ssi(&ssi
->scr
) &
807 (CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
)) == 0) {
808 write_ssi_mask(&ssi
->scr
, CCSR_SSI_SCR_SSIEN
, 0);
809 spin_lock_irqsave(&ssi_private
->baudclk_lock
, flags
);
810 ssi_private
->baudclk_locked
= false;
811 spin_unlock_irqrestore(&ssi_private
->baudclk_lock
, flags
);
819 write_ssi(sier_bits
, &ssi
->sier
);
824 static int fsl_ssi_dai_probe(struct snd_soc_dai
*dai
)
826 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(dai
);
828 if (ssi_private
->ssi_on_imx
&& ssi_private
->use_dma
) {
829 dai
->playback_dma_data
= &ssi_private
->dma_params_tx
;
830 dai
->capture_dma_data
= &ssi_private
->dma_params_rx
;
836 static const struct snd_soc_dai_ops fsl_ssi_dai_ops
= {
837 .startup
= fsl_ssi_startup
,
838 .hw_params
= fsl_ssi_hw_params
,
839 .set_fmt
= fsl_ssi_set_dai_fmt
,
840 .set_sysclk
= fsl_ssi_set_dai_sysclk
,
841 .set_tdm_slot
= fsl_ssi_set_dai_tdm_slot
,
842 .trigger
= fsl_ssi_trigger
,
845 /* Template for the CPU dai driver structure */
846 static struct snd_soc_dai_driver fsl_ssi_dai_template
= {
847 .probe
= fsl_ssi_dai_probe
,
851 .rates
= FSLSSI_I2S_RATES
,
852 .formats
= FSLSSI_I2S_FORMATS
,
857 .rates
= FSLSSI_I2S_RATES
,
858 .formats
= FSLSSI_I2S_FORMATS
,
860 .ops
= &fsl_ssi_dai_ops
,
863 static const struct snd_soc_component_driver fsl_ssi_component
= {
868 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
870 * This function is called by ALSA to start, stop, pause, and resume the
873 static int fsl_ssi_ac97_trigger(struct snd_pcm_substream
*substream
, int cmd
,
874 struct snd_soc_dai
*dai
)
876 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
877 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(
879 struct ccsr_ssi __iomem
*ssi
= ssi_private
->ssi
;
882 case SNDRV_PCM_TRIGGER_START
:
883 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
884 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
885 write_ssi_mask(&ssi
->sier
, 0, CCSR_SSI_SIER_TIE
|
886 CCSR_SSI_SIER_TFE0_EN
);
888 write_ssi_mask(&ssi
->sier
, 0, CCSR_SSI_SIER_RIE
|
889 CCSR_SSI_SIER_RFF0_EN
);
892 case SNDRV_PCM_TRIGGER_STOP
:
893 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
894 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
895 write_ssi_mask(&ssi
->sier
, CCSR_SSI_SIER_TIE
|
896 CCSR_SSI_SIER_TFE0_EN
, 0);
898 write_ssi_mask(&ssi
->sier
, CCSR_SSI_SIER_RIE
|
899 CCSR_SSI_SIER_RFF0_EN
, 0);
906 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
907 write_ssi(CCSR_SSI_SOR_TX_CLR
, &ssi
->sor
);
909 write_ssi(CCSR_SSI_SOR_RX_CLR
, &ssi
->sor
);
914 static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops
= {
915 .startup
= fsl_ssi_startup
,
916 .trigger
= fsl_ssi_ac97_trigger
,
919 static struct snd_soc_dai_driver fsl_ssi_ac97_dai
= {
922 .stream_name
= "AC97 Playback",
925 .rates
= SNDRV_PCM_RATE_8000_48000
,
926 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
929 .stream_name
= "AC97 Capture",
932 .rates
= SNDRV_PCM_RATE_48000
,
933 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
935 .ops
= &fsl_ssi_ac97_dai_ops
,
939 static struct fsl_ssi_private
*fsl_ac97_data
;
941 static void fsl_ssi_ac97_init(void)
943 fsl_ssi_setup(fsl_ac97_data
);
946 static void fsl_ssi_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
949 struct ccsr_ssi
*ssi
= fsl_ac97_data
->ssi
;
958 write_ssi(lreg
, &ssi
->sacadd
);
961 write_ssi(lval
, &ssi
->sacdat
);
963 write_ssi_mask(&ssi
->sacnt
, CCSR_SSI_SACNT_RDWR_MASK
,
968 static unsigned short fsl_ssi_ac97_read(struct snd_ac97
*ac97
,
971 struct ccsr_ssi
*ssi
= fsl_ac97_data
->ssi
;
973 unsigned short val
= -1;
976 lreg
= (reg
& 0x7f) << 12;
977 write_ssi(lreg
, &ssi
->sacadd
);
978 write_ssi_mask(&ssi
->sacnt
, CCSR_SSI_SACNT_RDWR_MASK
,
983 val
= (read_ssi(&ssi
->sacdat
) >> 4) & 0xffff;
988 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops
= {
989 .read
= fsl_ssi_ac97_read
,
990 .write
= fsl_ssi_ac97_write
,
993 /* Show the statistics of a flag only if its interrupt is enabled. The
994 * compiler will optimze this code to a no-op if the interrupt is not
997 #define SIER_SHOW(flag, name) \
999 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
1000 length += sprintf(buf + length, #name "=%u\n", \
1001 ssi_private->stats.name); \
1006 * fsl_sysfs_ssi_show: display SSI statistics
1008 * Display the statistics for the current SSI device. To avoid confusion,
1009 * we only show those counts that are enabled.
1011 static ssize_t
fsl_sysfs_ssi_show(struct device
*dev
,
1012 struct device_attribute
*attr
, char *buf
)
1014 struct fsl_ssi_private
*ssi_private
=
1015 container_of(attr
, struct fsl_ssi_private
, dev_attr
);
1018 SIER_SHOW(RFRC_EN
, rfrc
);
1019 SIER_SHOW(TFRC_EN
, tfrc
);
1020 SIER_SHOW(CMDAU_EN
, cmdau
);
1021 SIER_SHOW(CMDDU_EN
, cmddu
);
1022 SIER_SHOW(RXT_EN
, rxt
);
1023 SIER_SHOW(RDR1_EN
, rdr1
);
1024 SIER_SHOW(RDR0_EN
, rdr0
);
1025 SIER_SHOW(TDE1_EN
, tde1
);
1026 SIER_SHOW(TDE0_EN
, tde0
);
1027 SIER_SHOW(ROE1_EN
, roe1
);
1028 SIER_SHOW(ROE0_EN
, roe0
);
1029 SIER_SHOW(TUE1_EN
, tue1
);
1030 SIER_SHOW(TUE0_EN
, tue0
);
1031 SIER_SHOW(TFS_EN
, tfs
);
1032 SIER_SHOW(RFS_EN
, rfs
);
1033 SIER_SHOW(TLS_EN
, tls
);
1034 SIER_SHOW(RLS_EN
, rls
);
1035 SIER_SHOW(RFF1_EN
, rff1
);
1036 SIER_SHOW(RFF0_EN
, rff0
);
1037 SIER_SHOW(TFE1_EN
, tfe1
);
1038 SIER_SHOW(TFE0_EN
, tfe0
);
1044 * Make every character in a string lower-case
1046 static void make_lowercase(char *s
)
1052 if ((c
>= 'A') && (c
<= 'Z'))
1053 *p
= c
+ ('a' - 'A');
1058 static int fsl_ssi_probe(struct platform_device
*pdev
)
1060 struct fsl_ssi_private
*ssi_private
;
1062 struct device_attribute
*dev_attr
= NULL
;
1063 struct device_node
*np
= pdev
->dev
.of_node
;
1064 const char *p
, *sprop
;
1065 const uint32_t *iprop
;
1066 struct resource res
;
1071 /* SSIs that are not connected on the board should have a
1072 * status = "disabled"
1073 * property in their device tree nodes.
1075 if (!of_device_is_available(np
))
1078 /* We only support the SSI in "I2S Slave" mode */
1079 sprop
= of_get_property(np
, "fsl,mode", NULL
);
1081 dev_err(&pdev
->dev
, "fsl,mode property is necessary\n");
1084 if (!strcmp(sprop
, "ac97-slave")) {
1086 } else if (strcmp(sprop
, "i2s-slave")) {
1087 dev_notice(&pdev
->dev
, "mode %s is unsupported\n", sprop
);
1091 /* The DAI name is the last part of the full name of the node. */
1092 p
= strrchr(np
->full_name
, '/') + 1;
1093 ssi_private
= devm_kzalloc(&pdev
->dev
, sizeof(*ssi_private
) + strlen(p
),
1096 dev_err(&pdev
->dev
, "could not allocate DAI object\n");
1100 strcpy(ssi_private
->name
, p
);
1102 ssi_private
->use_dma
= !of_property_read_bool(np
,
1103 "fsl,fiq-stream-filter");
1106 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_ac97_dai
,
1107 sizeof(fsl_ssi_ac97_dai
));
1109 fsl_ac97_data
= ssi_private
;
1110 ssi_private
->imx_ac97
= true;
1112 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops
, pdev
);
1114 /* Initialize this copy of the CPU DAI driver structure */
1115 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_dai_template
,
1116 sizeof(fsl_ssi_dai_template
));
1118 ssi_private
->cpu_dai_drv
.name
= ssi_private
->name
;
1120 /* Get the addresses and IRQ */
1121 ret
= of_address_to_resource(np
, 0, &res
);
1123 dev_err(&pdev
->dev
, "could not determine device resources\n");
1126 ssi_private
->ssi
= of_iomap(np
, 0);
1127 if (!ssi_private
->ssi
) {
1128 dev_err(&pdev
->dev
, "could not map device resources\n");
1131 ssi_private
->ssi_phys
= res
.start
;
1133 ssi_private
->irq
= irq_of_parse_and_map(np
, 0);
1134 if (!ssi_private
->irq
) {
1135 dev_err(&pdev
->dev
, "no irq for node %s\n", np
->full_name
);
1139 /* Are the RX and the TX clocks locked? */
1140 if (!of_find_property(np
, "fsl,ssi-asynchronous", NULL
)) {
1141 ssi_private
->cpu_dai_drv
.symmetric_rates
= 1;
1142 ssi_private
->cpu_dai_drv
.symmetric_channels
= 1;
1143 ssi_private
->cpu_dai_drv
.symmetric_samplebits
= 1;
1146 /* Determine the FIFO depth. */
1147 iprop
= of_get_property(np
, "fsl,fifo-depth", NULL
);
1149 ssi_private
->fifo_depth
= be32_to_cpup(iprop
);
1151 /* Older 8610 DTs didn't have the fifo-depth property */
1152 ssi_private
->fifo_depth
= 8;
1154 ssi_private
->baudclk_locked
= false;
1155 spin_lock_init(&ssi_private
->baudclk_lock
);
1157 if (of_device_is_compatible(pdev
->dev
.of_node
, "fsl,imx21-ssi")) {
1159 ssi_private
->ssi_on_imx
= true;
1161 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1162 if (IS_ERR(ssi_private
->clk
)) {
1163 ret
= PTR_ERR(ssi_private
->clk
);
1164 dev_err(&pdev
->dev
, "could not get clock: %d\n", ret
);
1167 ret
= clk_prepare_enable(ssi_private
->clk
);
1169 dev_err(&pdev
->dev
, "clk_prepare_enable failed: %d\n",
1174 /* For those SLAVE implementations, we ingore non-baudclk cases
1175 * and, instead, abandon MASTER mode that needs baud clock.
1177 ssi_private
->baudclk
= devm_clk_get(&pdev
->dev
, "baud");
1178 if (IS_ERR(ssi_private
->baudclk
))
1179 dev_warn(&pdev
->dev
, "could not get baud clock: %ld\n",
1180 PTR_ERR(ssi_private
->baudclk
));
1182 clk_prepare_enable(ssi_private
->baudclk
);
1185 * We have burstsize be "fifo_depth - 2" to match the SSI
1186 * watermark setting in fsl_ssi_startup().
1188 ssi_private
->dma_params_tx
.maxburst
=
1189 ssi_private
->fifo_depth
- 2;
1190 ssi_private
->dma_params_rx
.maxburst
=
1191 ssi_private
->fifo_depth
- 2;
1192 ssi_private
->dma_params_tx
.addr
=
1193 ssi_private
->ssi_phys
+ offsetof(struct ccsr_ssi
, stx0
);
1194 ssi_private
->dma_params_rx
.addr
=
1195 ssi_private
->ssi_phys
+ offsetof(struct ccsr_ssi
, srx0
);
1196 ssi_private
->dma_params_tx
.filter_data
=
1197 &ssi_private
->filter_data_tx
;
1198 ssi_private
->dma_params_rx
.filter_data
=
1199 &ssi_private
->filter_data_rx
;
1200 if (!of_property_read_bool(pdev
->dev
.of_node
, "dmas") &&
1201 ssi_private
->use_dma
) {
1203 * FIXME: This is a temporary solution until all
1204 * necessary dma drivers support the generic dma
1207 ret
= of_property_read_u32_array(pdev
->dev
.of_node
,
1208 "fsl,ssi-dma-events", dma_events
, 2);
1209 if (ret
&& ssi_private
->use_dma
) {
1210 dev_err(&pdev
->dev
, "could not get dma events but fsl-ssi is configured to use DMA\n");
1215 shared
= of_device_is_compatible(of_get_parent(np
),
1218 imx_pcm_dma_params_init_data(&ssi_private
->filter_data_tx
,
1219 dma_events
[0], shared
? IMX_DMATYPE_SSI_SP
: IMX_DMATYPE_SSI
);
1220 imx_pcm_dma_params_init_data(&ssi_private
->filter_data_rx
,
1221 dma_events
[1], shared
? IMX_DMATYPE_SSI_SP
: IMX_DMATYPE_SSI
);
1222 } else if (ssi_private
->use_dma
) {
1223 /* The 'name' should not have any slashes in it. */
1224 ret
= devm_request_irq(&pdev
->dev
, ssi_private
->irq
,
1225 fsl_ssi_isr
, 0, ssi_private
->name
,
1228 dev_err(&pdev
->dev
, "could not claim irq %u\n",
1234 /* Initialize the the device_attribute structure */
1235 dev_attr
= &ssi_private
->dev_attr
;
1236 sysfs_attr_init(&dev_attr
->attr
);
1237 dev_attr
->attr
.name
= "statistics";
1238 dev_attr
->attr
.mode
= S_IRUGO
;
1239 dev_attr
->show
= fsl_sysfs_ssi_show
;
1241 ret
= device_create_file(&pdev
->dev
, dev_attr
);
1243 dev_err(&pdev
->dev
, "could not create sysfs %s file\n",
1244 ssi_private
->dev_attr
.attr
.name
);
1248 /* Register with ASoC */
1249 dev_set_drvdata(&pdev
->dev
, ssi_private
);
1251 ret
= snd_soc_register_component(&pdev
->dev
, &fsl_ssi_component
,
1252 &ssi_private
->cpu_dai_drv
, 1);
1254 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1258 if (ssi_private
->ssi_on_imx
) {
1259 if (!ssi_private
->use_dma
) {
1262 * Some boards use an incompatible codec. To get it
1263 * working, we are using imx-fiq-pcm-audio, that
1264 * can handle those codecs. DMA is not possible in this
1268 ssi_private
->fiq_params
.irq
= ssi_private
->irq
;
1269 ssi_private
->fiq_params
.base
= ssi_private
->ssi
;
1270 ssi_private
->fiq_params
.dma_params_rx
=
1271 &ssi_private
->dma_params_rx
;
1272 ssi_private
->fiq_params
.dma_params_tx
=
1273 &ssi_private
->dma_params_tx
;
1275 ret
= imx_pcm_fiq_init(pdev
, &ssi_private
->fiq_params
);
1279 ret
= imx_pcm_dma_init(pdev
);
1286 * If codec-handle property is missing from SSI node, we assume
1287 * that the machine driver uses new binding which does not require
1288 * SSI driver to trigger machine driver's probe.
1290 if (!of_get_property(np
, "codec-handle", NULL
)) {
1291 ssi_private
->new_binding
= true;
1295 /* Trigger the machine driver's probe function. The platform driver
1296 * name of the machine driver is taken from /compatible property of the
1297 * device tree. We also pass the address of the CPU DAI driver
1300 sprop
= of_get_property(of_find_node_by_path("/"), "compatible", NULL
);
1301 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1302 p
= strrchr(sprop
, ',');
1305 snprintf(name
, sizeof(name
), "snd-soc-%s", sprop
);
1306 make_lowercase(name
);
1309 platform_device_register_data(&pdev
->dev
, name
, 0, NULL
, 0);
1310 if (IS_ERR(ssi_private
->pdev
)) {
1311 ret
= PTR_ERR(ssi_private
->pdev
);
1312 dev_err(&pdev
->dev
, "failed to register platform: %d\n", ret
);
1317 if (ssi_private
->imx_ac97
)
1318 fsl_ssi_ac97_init();
1323 snd_soc_unregister_component(&pdev
->dev
);
1326 device_remove_file(&pdev
->dev
, dev_attr
);
1329 if (ssi_private
->ssi_on_imx
) {
1330 if (!IS_ERR(ssi_private
->baudclk
))
1331 clk_disable_unprepare(ssi_private
->baudclk
);
1332 clk_disable_unprepare(ssi_private
->clk
);
1336 irq_dispose_mapping(ssi_private
->irq
);
1341 static int fsl_ssi_remove(struct platform_device
*pdev
)
1343 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(&pdev
->dev
);
1345 if (!ssi_private
->new_binding
)
1346 platform_device_unregister(ssi_private
->pdev
);
1347 snd_soc_unregister_component(&pdev
->dev
);
1348 device_remove_file(&pdev
->dev
, &ssi_private
->dev_attr
);
1349 if (ssi_private
->ssi_on_imx
) {
1350 if (!IS_ERR(ssi_private
->baudclk
))
1351 clk_disable_unprepare(ssi_private
->baudclk
);
1352 clk_disable_unprepare(ssi_private
->clk
);
1354 irq_dispose_mapping(ssi_private
->irq
);
1359 static const struct of_device_id fsl_ssi_ids
[] = {
1360 { .compatible
= "fsl,mpc8610-ssi", },
1361 { .compatible
= "fsl,imx21-ssi", },
1364 MODULE_DEVICE_TABLE(of
, fsl_ssi_ids
);
1366 static struct platform_driver fsl_ssi_driver
= {
1368 .name
= "fsl-ssi-dai",
1369 .owner
= THIS_MODULE
,
1370 .of_match_table
= fsl_ssi_ids
,
1372 .probe
= fsl_ssi_probe
,
1373 .remove
= fsl_ssi_remove
,
1376 module_platform_driver(fsl_ssi_driver
);
1378 MODULE_ALIAS("platform:fsl-ssi-dai");
1379 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1380 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1381 MODULE_LICENSE("GPL v2");