2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * The SSI has a limitation in that the samples must be in the same byte
71 * order as the host CPU. This is because when multiple bytes are written
72 * to the STX register, the bytes and bits must be written in the same
73 * order. The STX is a shift register, so all the bits need to be aligned
74 * (bit-endianness must match byte-endianness). Processors typically write
75 * the bits within a byte in the same order that the bytes of a word are
76 * written in. So if the host CPU is big-endian, then only big-endian
77 * samples will be written to STX properly.
80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
103 struct fsl_ssi_reg_val
{
110 struct fsl_ssi_rxtx_reg_val
{
111 struct fsl_ssi_reg_val rx
;
112 struct fsl_ssi_reg_val tx
;
115 static bool fsl_ssi_readable_reg(struct device
*dev
, unsigned int reg
)
118 case CCSR_SSI_SACCEN
:
119 case CCSR_SSI_SACCDIS
:
126 static bool fsl_ssi_volatile_reg(struct device
*dev
, unsigned int reg
)
136 case CCSR_SSI_SACADD
:
137 case CCSR_SSI_SACDAT
:
139 case CCSR_SSI_SACCST
:
146 static bool fsl_ssi_precious_reg(struct device
*dev
, unsigned int reg
)
152 case CCSR_SSI_SACADD
:
153 case CCSR_SSI_SACDAT
:
161 static bool fsl_ssi_writeable_reg(struct device
*dev
, unsigned int reg
)
166 case CCSR_SSI_SACCST
:
173 static const struct regmap_config fsl_ssi_regconfig
= {
174 .max_register
= CCSR_SSI_SACCDIS
,
178 .val_format_endian
= REGMAP_ENDIAN_NATIVE
,
179 .num_reg_defaults_raw
= CCSR_SSI_SACCDIS
/ sizeof(uint32_t) + 1,
180 .readable_reg
= fsl_ssi_readable_reg
,
181 .volatile_reg
= fsl_ssi_volatile_reg
,
182 .precious_reg
= fsl_ssi_precious_reg
,
183 .writeable_reg
= fsl_ssi_writeable_reg
,
184 .cache_type
= REGCACHE_RBTREE
,
187 struct fsl_ssi_soc_data
{
189 bool imx21regs
; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
195 * fsl_ssi_private: per-SSI private data
197 * @reg: Pointer to the regmap registers
198 * @irq: IRQ of this SSI
199 * @cpu_dai_drv: CPU DAI driver for this device
201 * @dai_fmt: DAI configuration this device is currently used with
202 * @i2s_mode: i2s and network mode configuration of the device. Is used to
203 * switch between normal and i2s/network mode
204 * mode depending on the number of channels
205 * @use_dma: DMA is used or FIQ with stream filter
206 * @use_dual_fifo: DMA with support for both FIFOs used
207 * @fifo_deph: Depth of the SSI FIFOs
208 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
211 * @baudclk: SSI baud clock for master mode
212 * @baudclk_streams: Active streams that are using baudclk
213 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
215 * @dma_params_tx: DMA transmit parameters
216 * @dma_params_rx: DMA receive parameters
217 * @ssi_phys: physical address of the SSI registers
219 * @fiq_params: FIQ stream filtering parameters
221 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
223 * @dbg_stats: Debugging statistics
225 * @soc: SoC specific data
227 struct fsl_ssi_private
{
230 struct snd_soc_dai_driver cpu_dai_drv
;
232 unsigned int dai_fmt
;
236 bool has_ipg_clk_name
;
237 unsigned int fifo_depth
;
238 struct fsl_ssi_rxtx_reg_val rxtx_reg_val
;
242 unsigned int baudclk_streams
;
243 unsigned int bitclk_freq
;
245 /* regcache for volatile regs */
250 struct snd_dmaengine_dai_dma_data dma_params_tx
;
251 struct snd_dmaengine_dai_dma_data dma_params_rx
;
254 /* params for non-dma FIQ stream filtered mode */
255 struct imx_pcm_fiq_params fiq_params
;
257 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
258 * should be replaced with simple-sound-card. */
259 struct platform_device
*pdev
;
261 struct fsl_ssi_dbg dbg_stats
;
263 const struct fsl_ssi_soc_data
*soc
;
267 * imx51 and later SoCs have a slightly different IP that allows the
268 * SSI configuration while the SSI unit is running.
270 * More important, it is necessary on those SoCs to configure the
271 * sperate TX/RX DMA bits just before starting the stream
272 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
273 * sends any DMA requests to the SDMA unit, otherwise it is not defined
274 * how the SDMA unit handles the DMA request.
276 * SDMA units are present on devices starting at imx35 but the imx35
277 * reference manual states that the DMA bits should not be changed
278 * while the SSI unit is running (SSIEN). So we support the necessary
279 * online configuration of fsl-ssi starting at imx51.
282 static struct fsl_ssi_soc_data fsl_ssi_mpc8610
= {
284 .offline_config
= true,
285 .sisr_write_mask
= CCSR_SSI_SISR_RFRC
| CCSR_SSI_SISR_TFRC
|
286 CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
287 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
290 static struct fsl_ssi_soc_data fsl_ssi_imx21
= {
293 .offline_config
= true,
294 .sisr_write_mask
= 0,
297 static struct fsl_ssi_soc_data fsl_ssi_imx35
= {
299 .offline_config
= true,
300 .sisr_write_mask
= CCSR_SSI_SISR_RFRC
| CCSR_SSI_SISR_TFRC
|
301 CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
302 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
305 static struct fsl_ssi_soc_data fsl_ssi_imx51
= {
307 .offline_config
= false,
308 .sisr_write_mask
= CCSR_SSI_SISR_ROE0
| CCSR_SSI_SISR_ROE1
|
309 CCSR_SSI_SISR_TUE0
| CCSR_SSI_SISR_TUE1
,
312 static const struct of_device_id fsl_ssi_ids
[] = {
313 { .compatible
= "fsl,mpc8610-ssi", .data
= &fsl_ssi_mpc8610
},
314 { .compatible
= "fsl,imx51-ssi", .data
= &fsl_ssi_imx51
},
315 { .compatible
= "fsl,imx35-ssi", .data
= &fsl_ssi_imx35
},
316 { .compatible
= "fsl,imx21-ssi", .data
= &fsl_ssi_imx21
},
319 MODULE_DEVICE_TABLE(of
, fsl_ssi_ids
);
321 static bool fsl_ssi_is_ac97(struct fsl_ssi_private
*ssi_private
)
323 return (ssi_private
->dai_fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) ==
327 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private
*ssi_private
)
329 return (ssi_private
->dai_fmt
& SND_SOC_DAIFMT_MASTER_MASK
) ==
330 SND_SOC_DAIFMT_CBS_CFS
;
333 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private
*ssi_private
)
335 return (ssi_private
->dai_fmt
& SND_SOC_DAIFMT_MASTER_MASK
) ==
336 SND_SOC_DAIFMT_CBM_CFS
;
339 * fsl_ssi_isr: SSI interrupt handler
341 * Although it's possible to use the interrupt handler to send and receive
342 * data to/from the SSI, we use the DMA instead. Programming is more
343 * complicated, but the performance is much better.
345 * This interrupt handler is used only to gather statistics.
347 * @irq: IRQ of the SSI device
348 * @dev_id: pointer to the ssi_private structure for this SSI device
350 static irqreturn_t
fsl_ssi_isr(int irq
, void *dev_id
)
352 struct fsl_ssi_private
*ssi_private
= dev_id
;
353 struct regmap
*regs
= ssi_private
->regs
;
357 /* We got an interrupt, so read the status register to see what we
358 were interrupted for. We mask it with the Interrupt Enable register
359 so that we only check for events that we're interested in.
361 regmap_read(regs
, CCSR_SSI_SISR
, &sisr
);
363 sisr2
= sisr
& ssi_private
->soc
->sisr_write_mask
;
364 /* Clear the bits that we set */
366 regmap_write(regs
, CCSR_SSI_SISR
, sisr2
);
368 fsl_ssi_dbg_isr(&ssi_private
->dbg_stats
, sisr
);
374 * Enable/Disable all rx/tx config flags at once.
376 static void fsl_ssi_rxtx_config(struct fsl_ssi_private
*ssi_private
,
379 struct regmap
*regs
= ssi_private
->regs
;
380 struct fsl_ssi_rxtx_reg_val
*vals
= &ssi_private
->rxtx_reg_val
;
383 regmap_update_bits(regs
, CCSR_SSI_SIER
,
384 vals
->rx
.sier
| vals
->tx
.sier
,
385 vals
->rx
.sier
| vals
->tx
.sier
);
386 regmap_update_bits(regs
, CCSR_SSI_SRCR
,
387 vals
->rx
.srcr
| vals
->tx
.srcr
,
388 vals
->rx
.srcr
| vals
->tx
.srcr
);
389 regmap_update_bits(regs
, CCSR_SSI_STCR
,
390 vals
->rx
.stcr
| vals
->tx
.stcr
,
391 vals
->rx
.stcr
| vals
->tx
.stcr
);
393 regmap_update_bits(regs
, CCSR_SSI_SRCR
,
394 vals
->rx
.srcr
| vals
->tx
.srcr
, 0);
395 regmap_update_bits(regs
, CCSR_SSI_STCR
,
396 vals
->rx
.stcr
| vals
->tx
.stcr
, 0);
397 regmap_update_bits(regs
, CCSR_SSI_SIER
,
398 vals
->rx
.sier
| vals
->tx
.sier
, 0);
403 * Calculate the bits that have to be disabled for the current stream that is
404 * getting disabled. This keeps the bits enabled that are necessary for the
405 * second stream to work if 'stream_active' is true.
407 * Detailed calculation:
408 * These are the values that need to be active after disabling. For non-active
409 * second stream, this is 0:
410 * vals_stream * !!stream_active
412 * The following computes the overall differences between the setup for the
413 * to-disable stream and the active stream, a simple XOR:
414 * vals_disable ^ (vals_stream * !!(stream_active))
416 * The full expression adds a mask on all values we care about
418 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
420 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
423 * Enable/Disable a ssi configuration. You have to pass either
424 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
426 static void fsl_ssi_config(struct fsl_ssi_private
*ssi_private
, bool enable
,
427 struct fsl_ssi_reg_val
*vals
)
429 struct regmap
*regs
= ssi_private
->regs
;
430 struct fsl_ssi_reg_val
*avals
;
431 int nr_active_streams
;
435 regmap_read(regs
, CCSR_SSI_SCR
, &scr_val
);
437 nr_active_streams
= !!(scr_val
& CCSR_SSI_SCR_TE
) +
438 !!(scr_val
& CCSR_SSI_SCR_RE
);
440 if (nr_active_streams
- 1 > 0)
445 /* Find the other direction values rx or tx which we do not want to
447 if (&ssi_private
->rxtx_reg_val
.rx
== vals
)
448 avals
= &ssi_private
->rxtx_reg_val
.tx
;
450 avals
= &ssi_private
->rxtx_reg_val
.rx
;
452 /* If vals should be disabled, start with disabling the unit */
454 u32 scr
= fsl_ssi_disable_val(vals
->scr
, avals
->scr
,
456 regmap_update_bits(regs
, CCSR_SSI_SCR
, scr
, 0);
460 * We are running on a SoC which does not support online SSI
461 * reconfiguration, so we have to enable all necessary flags at once
462 * even if we do not use them later (capture and playback configuration)
464 if (ssi_private
->soc
->offline_config
) {
465 if ((enable
&& !nr_active_streams
) ||
466 (!enable
&& !keep_active
))
467 fsl_ssi_rxtx_config(ssi_private
, enable
);
473 * Configure single direction units while the SSI unit is running
474 * (online configuration)
477 regmap_update_bits(regs
, CCSR_SSI_SIER
, vals
->sier
, vals
->sier
);
478 regmap_update_bits(regs
, CCSR_SSI_SRCR
, vals
->srcr
, vals
->srcr
);
479 regmap_update_bits(regs
, CCSR_SSI_STCR
, vals
->stcr
, vals
->stcr
);
486 * Disabling the necessary flags for one of rx/tx while the
487 * other stream is active is a little bit more difficult. We
488 * have to disable only those flags that differ between both
489 * streams (rx XOR tx) and that are set in the stream that is
490 * disabled now. Otherwise we could alter flags of the other
494 /* These assignments are simply vals without bits set in avals*/
495 sier
= fsl_ssi_disable_val(vals
->sier
, avals
->sier
,
497 srcr
= fsl_ssi_disable_val(vals
->srcr
, avals
->srcr
,
499 stcr
= fsl_ssi_disable_val(vals
->stcr
, avals
->stcr
,
502 regmap_update_bits(regs
, CCSR_SSI_SRCR
, srcr
, 0);
503 regmap_update_bits(regs
, CCSR_SSI_STCR
, stcr
, 0);
504 regmap_update_bits(regs
, CCSR_SSI_SIER
, sier
, 0);
508 /* Enabling of subunits is done after configuration */
510 regmap_update_bits(regs
, CCSR_SSI_SCR
, vals
->scr
, vals
->scr
);
514 static void fsl_ssi_rx_config(struct fsl_ssi_private
*ssi_private
, bool enable
)
516 fsl_ssi_config(ssi_private
, enable
, &ssi_private
->rxtx_reg_val
.rx
);
519 static void fsl_ssi_tx_config(struct fsl_ssi_private
*ssi_private
, bool enable
)
521 fsl_ssi_config(ssi_private
, enable
, &ssi_private
->rxtx_reg_val
.tx
);
525 * Setup rx/tx register values used to enable/disable the streams. These will
526 * be used later in fsl_ssi_config to setup the streams without the need to
527 * check for all different SSI modes.
529 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private
*ssi_private
)
531 struct fsl_ssi_rxtx_reg_val
*reg
= &ssi_private
->rxtx_reg_val
;
533 reg
->rx
.sier
= CCSR_SSI_SIER_RFF0_EN
;
534 reg
->rx
.srcr
= CCSR_SSI_SRCR_RFEN0
;
536 reg
->tx
.sier
= CCSR_SSI_SIER_TFE0_EN
;
537 reg
->tx
.stcr
= CCSR_SSI_STCR_TFEN0
;
540 if (!fsl_ssi_is_ac97(ssi_private
)) {
541 reg
->rx
.scr
= CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_RE
;
542 reg
->rx
.sier
|= CCSR_SSI_SIER_RFF0_EN
;
543 reg
->tx
.scr
= CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
;
544 reg
->tx
.sier
|= CCSR_SSI_SIER_TFE0_EN
;
547 if (ssi_private
->use_dma
) {
548 reg
->rx
.sier
|= CCSR_SSI_SIER_RDMAE
;
549 reg
->tx
.sier
|= CCSR_SSI_SIER_TDMAE
;
551 reg
->rx
.sier
|= CCSR_SSI_SIER_RIE
;
552 reg
->tx
.sier
|= CCSR_SSI_SIER_TIE
;
555 reg
->rx
.sier
|= FSLSSI_SIER_DBG_RX_FLAGS
;
556 reg
->tx
.sier
|= FSLSSI_SIER_DBG_TX_FLAGS
;
559 static void fsl_ssi_setup_ac97(struct fsl_ssi_private
*ssi_private
)
561 struct regmap
*regs
= ssi_private
->regs
;
564 * Setup the clock control register
566 regmap_write(regs
, CCSR_SSI_STCCR
,
567 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
568 regmap_write(regs
, CCSR_SSI_SRCCR
,
569 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
572 * Enable AC97 mode and startup the SSI
574 regmap_write(regs
, CCSR_SSI_SACNT
,
575 CCSR_SSI_SACNT_AC97EN
| CCSR_SSI_SACNT_FV
);
577 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
578 if (!ssi_private
->soc
->imx21regs
) {
579 regmap_write(regs
, CCSR_SSI_SACCDIS
, 0xff);
580 regmap_write(regs
, CCSR_SSI_SACCEN
, 0x300);
584 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
585 * codec before a stream is started.
587 regmap_update_bits(regs
, CCSR_SSI_SCR
,
588 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
,
589 CCSR_SSI_SCR_SSIEN
| CCSR_SSI_SCR_TE
| CCSR_SSI_SCR_RE
);
591 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_WAIT(3));
595 * fsl_ssi_startup: create a new substream
597 * This is the first function called when a stream is opened.
599 * If this is the first stream open, then grab the IRQ and program most of
602 static int fsl_ssi_startup(struct snd_pcm_substream
*substream
,
603 struct snd_soc_dai
*dai
)
605 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
606 struct fsl_ssi_private
*ssi_private
=
607 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
610 ret
= clk_prepare_enable(ssi_private
->clk
);
614 /* When using dual fifo mode, it is safer to ensure an even period
615 * size. If appearing to an odd number while DMA always starts its
616 * task from fifo0, fifo1 would be neglected at the end of each
617 * period. But SSI would still access fifo1 with an invalid data.
619 if (ssi_private
->use_dual_fifo
)
620 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
621 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
, 2);
627 * fsl_ssi_shutdown: shutdown the SSI
630 static void fsl_ssi_shutdown(struct snd_pcm_substream
*substream
,
631 struct snd_soc_dai
*dai
)
633 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
634 struct fsl_ssi_private
*ssi_private
=
635 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
637 clk_disable_unprepare(ssi_private
->clk
);
642 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
644 * Note: This function can be only called when using SSI as DAI master
646 * Quick instruction for parameters:
647 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
648 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
650 static int fsl_ssi_set_bclk(struct snd_pcm_substream
*substream
,
651 struct snd_soc_dai
*cpu_dai
,
652 struct snd_pcm_hw_params
*hw_params
)
654 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
655 struct regmap
*regs
= ssi_private
->regs
;
656 int synchronous
= ssi_private
->cpu_dai_drv
.symmetric_rates
, ret
;
657 u32 pm
= 999, div2
, psr
, stccr
, mask
, afreq
, factor
, i
;
658 unsigned long clkrate
, baudrate
, tmprate
;
659 u64 sub
, savesub
= 100000;
661 bool baudclk_is_used
;
663 /* Prefer the explicitly set bitclock frequency */
664 if (ssi_private
->bitclk_freq
)
665 freq
= ssi_private
->bitclk_freq
;
667 freq
= params_channels(hw_params
) * 32 * params_rate(hw_params
);
669 /* Don't apply it to any non-baudclk circumstance */
670 if (IS_ERR(ssi_private
->baudclk
))
674 * Hardware limitation: The bclk rate must be
675 * never greater than 1/5 IPG clock rate
677 if (freq
* 5 > clk_get_rate(ssi_private
->clk
)) {
678 dev_err(cpu_dai
->dev
, "bitclk > ipgclk/5\n");
682 baudclk_is_used
= ssi_private
->baudclk_streams
& ~(BIT(substream
->stream
));
684 /* It should be already enough to divide clock by setting pm alone */
688 factor
= (div2
+ 1) * (7 * psr
+ 1) * 2;
690 for (i
= 0; i
< 255; i
++) {
691 tmprate
= freq
* factor
* (i
+ 1);
694 clkrate
= clk_get_rate(ssi_private
->baudclk
);
696 clkrate
= clk_round_rate(ssi_private
->baudclk
, tmprate
);
699 afreq
= clkrate
/ (i
+ 1);
703 else if (freq
/ afreq
== 1)
705 else if (afreq
/ freq
== 1)
710 /* Calculate the fraction */
714 if (sub
< savesub
&& !(i
== 0 && psr
== 0 && div2
== 0)) {
725 /* No proper pm found if it is still remaining the initial value */
727 dev_err(cpu_dai
->dev
, "failed to handle the required sysclk\n");
731 stccr
= CCSR_SSI_SxCCR_PM(pm
+ 1) | (div2
? CCSR_SSI_SxCCR_DIV2
: 0) |
732 (psr
? CCSR_SSI_SxCCR_PSR
: 0);
733 mask
= CCSR_SSI_SxCCR_PM_MASK
| CCSR_SSI_SxCCR_DIV2
|
736 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
|| synchronous
)
737 regmap_update_bits(regs
, CCSR_SSI_STCCR
, mask
, stccr
);
739 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, mask
, stccr
);
741 if (!baudclk_is_used
) {
742 ret
= clk_set_rate(ssi_private
->baudclk
, baudrate
);
744 dev_err(cpu_dai
->dev
, "failed to set baudclk rate\n");
752 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
753 int clk_id
, unsigned int freq
, int dir
)
755 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
757 ssi_private
->bitclk_freq
= freq
;
763 * fsl_ssi_hw_params - program the sample size
765 * Most of the SSI registers have been programmed in the startup function,
766 * but the word length must be programmed here. Unfortunately, programming
767 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
768 * cause a problem with supporting simultaneous playback and capture. If
769 * the SSI is already playing a stream, then that stream may be temporarily
770 * stopped when you start capture.
772 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
775 static int fsl_ssi_hw_params(struct snd_pcm_substream
*substream
,
776 struct snd_pcm_hw_params
*hw_params
, struct snd_soc_dai
*cpu_dai
)
778 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
779 struct regmap
*regs
= ssi_private
->regs
;
780 unsigned int channels
= params_channels(hw_params
);
781 unsigned int sample_size
= params_width(hw_params
);
782 u32 wl
= CCSR_SSI_SxCCR_WL(sample_size
);
787 regmap_read(regs
, CCSR_SSI_SCR
, &scr_val
);
788 enabled
= scr_val
& CCSR_SSI_SCR_SSIEN
;
791 * If we're in synchronous mode, and the SSI is already enabled,
792 * then STCCR is already set properly.
794 if (enabled
&& ssi_private
->cpu_dai_drv
.symmetric_rates
)
797 if (fsl_ssi_is_i2s_master(ssi_private
)) {
798 ret
= fsl_ssi_set_bclk(substream
, cpu_dai
, hw_params
);
802 /* Do not enable the clock if it is already enabled */
803 if (!(ssi_private
->baudclk_streams
& BIT(substream
->stream
))) {
804 ret
= clk_prepare_enable(ssi_private
->baudclk
);
808 ssi_private
->baudclk_streams
|= BIT(substream
->stream
);
812 if (!fsl_ssi_is_ac97(ssi_private
)) {
815 * Switch to normal net mode in order to have a frame sync
816 * signal every 32 bits instead of 16 bits
818 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private
) && sample_size
== 16)
819 i2smode
= CCSR_SSI_SCR_I2S_MODE_NORMAL
|
822 i2smode
= ssi_private
->i2s_mode
;
824 regmap_update_bits(regs
, CCSR_SSI_SCR
,
825 CCSR_SSI_SCR_NET
| CCSR_SSI_SCR_I2S_MODE_MASK
,
826 channels
== 1 ? 0 : i2smode
);
830 * FIXME: The documentation says that SxCCR[WL] should not be
831 * modified while the SSI is enabled. The only time this can
832 * happen is if we're trying to do simultaneous playback and
833 * capture in asynchronous mode. Unfortunately, I have been enable
834 * to get that to work at all on the P1022DS. Therefore, we don't
835 * bother to disable/enable the SSI when setting SxCCR[WL], because
836 * the SSI will stop anyway. Maybe one day, this will get fixed.
839 /* In synchronous mode, the SSI uses STCCR for capture */
840 if ((substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) ||
841 ssi_private
->cpu_dai_drv
.symmetric_rates
)
842 regmap_update_bits(regs
, CCSR_SSI_STCCR
, CCSR_SSI_SxCCR_WL_MASK
,
845 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, CCSR_SSI_SxCCR_WL_MASK
,
851 static int fsl_ssi_hw_free(struct snd_pcm_substream
*substream
,
852 struct snd_soc_dai
*cpu_dai
)
854 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
855 struct fsl_ssi_private
*ssi_private
=
856 snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
858 if (fsl_ssi_is_i2s_master(ssi_private
) &&
859 ssi_private
->baudclk_streams
& BIT(substream
->stream
)) {
860 clk_disable_unprepare(ssi_private
->baudclk
);
861 ssi_private
->baudclk_streams
&= ~BIT(substream
->stream
);
867 static int _fsl_ssi_set_dai_fmt(struct device
*dev
,
868 struct fsl_ssi_private
*ssi_private
,
871 struct regmap
*regs
= ssi_private
->regs
;
872 u32 strcr
= 0, stcr
, srcr
, scr
, mask
;
875 ssi_private
->dai_fmt
= fmt
;
877 if (fsl_ssi_is_i2s_master(ssi_private
) && IS_ERR(ssi_private
->baudclk
)) {
878 dev_err(dev
, "baudclk is missing which is necessary for master mode\n");
882 fsl_ssi_setup_reg_vals(ssi_private
);
884 regmap_read(regs
, CCSR_SSI_SCR
, &scr
);
885 scr
&= ~(CCSR_SSI_SCR_SYN
| CCSR_SSI_SCR_I2S_MODE_MASK
);
886 scr
|= CCSR_SSI_SCR_SYNC_TX_FS
;
888 mask
= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
|
889 CCSR_SSI_STCR_TSCKP
| CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TFSL
|
891 regmap_read(regs
, CCSR_SSI_STCR
, &stcr
);
892 regmap_read(regs
, CCSR_SSI_SRCR
, &srcr
);
896 ssi_private
->i2s_mode
= CCSR_SSI_SCR_NET
;
897 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
898 case SND_SOC_DAIFMT_I2S
:
899 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
900 case SND_SOC_DAIFMT_CBM_CFS
:
901 case SND_SOC_DAIFMT_CBS_CFS
:
902 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_MASTER
;
903 regmap_update_bits(regs
, CCSR_SSI_STCCR
,
904 CCSR_SSI_SxCCR_DC_MASK
,
905 CCSR_SSI_SxCCR_DC(2));
906 regmap_update_bits(regs
, CCSR_SSI_SRCCR
,
907 CCSR_SSI_SxCCR_DC_MASK
,
908 CCSR_SSI_SxCCR_DC(2));
910 case SND_SOC_DAIFMT_CBM_CFM
:
911 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_SLAVE
;
917 /* Data on rising edge of bclk, frame low, 1clk before data */
918 strcr
|= CCSR_SSI_STCR_TFSI
| CCSR_SSI_STCR_TSCKP
|
919 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
921 case SND_SOC_DAIFMT_LEFT_J
:
922 /* Data on rising edge of bclk, frame high */
923 strcr
|= CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TSCKP
;
925 case SND_SOC_DAIFMT_DSP_A
:
926 /* Data on rising edge of bclk, frame high, 1clk before data */
927 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
928 CCSR_SSI_STCR_TXBIT0
| CCSR_SSI_STCR_TEFS
;
930 case SND_SOC_DAIFMT_DSP_B
:
931 /* Data on rising edge of bclk, frame high */
932 strcr
|= CCSR_SSI_STCR_TFSL
| CCSR_SSI_STCR_TSCKP
|
933 CCSR_SSI_STCR_TXBIT0
;
935 case SND_SOC_DAIFMT_AC97
:
936 ssi_private
->i2s_mode
|= CCSR_SSI_SCR_I2S_MODE_NORMAL
;
941 scr
|= ssi_private
->i2s_mode
;
943 /* DAI clock inversion */
944 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
945 case SND_SOC_DAIFMT_NB_NF
:
946 /* Nothing to do for both normal cases */
948 case SND_SOC_DAIFMT_IB_NF
:
949 /* Invert bit clock */
950 strcr
^= CCSR_SSI_STCR_TSCKP
;
952 case SND_SOC_DAIFMT_NB_IF
:
953 /* Invert frame clock */
954 strcr
^= CCSR_SSI_STCR_TFSI
;
956 case SND_SOC_DAIFMT_IB_IF
:
957 /* Invert both clocks */
958 strcr
^= CCSR_SSI_STCR_TSCKP
;
959 strcr
^= CCSR_SSI_STCR_TFSI
;
965 /* DAI clock master masks */
966 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
967 case SND_SOC_DAIFMT_CBS_CFS
:
968 strcr
|= CCSR_SSI_STCR_TFDIR
| CCSR_SSI_STCR_TXDIR
;
969 scr
|= CCSR_SSI_SCR_SYS_CLK_EN
;
971 case SND_SOC_DAIFMT_CBM_CFM
:
972 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
974 case SND_SOC_DAIFMT_CBM_CFS
:
975 strcr
&= ~CCSR_SSI_STCR_TXDIR
;
976 strcr
|= CCSR_SSI_STCR_TFDIR
;
977 scr
&= ~CCSR_SSI_SCR_SYS_CLK_EN
;
980 if (!fsl_ssi_is_ac97(ssi_private
))
987 if (ssi_private
->cpu_dai_drv
.symmetric_rates
988 || fsl_ssi_is_ac97(ssi_private
)) {
989 /* Need to clear RXDIR when using SYNC or AC97 mode */
990 srcr
&= ~CCSR_SSI_SRCR_RXDIR
;
991 scr
|= CCSR_SSI_SCR_SYN
;
994 regmap_write(regs
, CCSR_SSI_STCR
, stcr
);
995 regmap_write(regs
, CCSR_SSI_SRCR
, srcr
);
996 regmap_write(regs
, CCSR_SSI_SCR
, scr
);
999 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
1000 * use FIFO 1. We program the transmit water to signal a DMA transfer
1001 * if there are only two (or fewer) elements left in the FIFO. Two
1002 * elements equals one frame (left channel, right channel). This value,
1003 * however, depends on the depth of the transmit buffer.
1005 * We set the watermark on the same level as the DMA burstsize. For
1006 * fiq it is probably better to use the biggest possible watermark
1009 if (ssi_private
->use_dma
)
1010 wm
= ssi_private
->fifo_depth
- 2;
1012 wm
= ssi_private
->fifo_depth
;
1014 regmap_write(regs
, CCSR_SSI_SFCSR
,
1015 CCSR_SSI_SFCSR_TFWM0(wm
) | CCSR_SSI_SFCSR_RFWM0(wm
) |
1016 CCSR_SSI_SFCSR_TFWM1(wm
) | CCSR_SSI_SFCSR_RFWM1(wm
));
1018 if (ssi_private
->use_dual_fifo
) {
1019 regmap_update_bits(regs
, CCSR_SSI_SRCR
, CCSR_SSI_SRCR_RFEN1
,
1020 CCSR_SSI_SRCR_RFEN1
);
1021 regmap_update_bits(regs
, CCSR_SSI_STCR
, CCSR_SSI_STCR_TFEN1
,
1022 CCSR_SSI_STCR_TFEN1
);
1023 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_TCH_EN
,
1024 CCSR_SSI_SCR_TCH_EN
);
1027 if ((fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) == SND_SOC_DAIFMT_AC97
)
1028 fsl_ssi_setup_ac97(ssi_private
);
1035 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1037 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai
*cpu_dai
, unsigned int fmt
)
1039 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
1041 return _fsl_ssi_set_dai_fmt(cpu_dai
->dev
, ssi_private
, fmt
);
1045 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1047 * Note: This function can be only called when using SSI as DAI master
1049 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai
*cpu_dai
, u32 tx_mask
,
1050 u32 rx_mask
, int slots
, int slot_width
)
1052 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(cpu_dai
);
1053 struct regmap
*regs
= ssi_private
->regs
;
1056 /* The slot number should be >= 2 if using Network mode or I2S mode */
1057 regmap_read(regs
, CCSR_SSI_SCR
, &val
);
1058 val
&= CCSR_SSI_SCR_I2S_MODE_MASK
| CCSR_SSI_SCR_NET
;
1059 if (val
&& slots
< 2) {
1060 dev_err(cpu_dai
->dev
, "slot number should be >= 2 in I2S or NET\n");
1064 regmap_update_bits(regs
, CCSR_SSI_STCCR
, CCSR_SSI_SxCCR_DC_MASK
,
1065 CCSR_SSI_SxCCR_DC(slots
));
1066 regmap_update_bits(regs
, CCSR_SSI_SRCCR
, CCSR_SSI_SxCCR_DC_MASK
,
1067 CCSR_SSI_SxCCR_DC(slots
));
1069 /* The register SxMSKs needs SSI to provide essential clock due to
1070 * hardware design. So we here temporarily enable SSI to set them.
1072 regmap_read(regs
, CCSR_SSI_SCR
, &val
);
1073 val
&= CCSR_SSI_SCR_SSIEN
;
1074 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_SSIEN
,
1075 CCSR_SSI_SCR_SSIEN
);
1077 regmap_write(regs
, CCSR_SSI_STMSK
, ~tx_mask
);
1078 regmap_write(regs
, CCSR_SSI_SRMSK
, ~rx_mask
);
1080 regmap_update_bits(regs
, CCSR_SSI_SCR
, CCSR_SSI_SCR_SSIEN
, val
);
1086 * fsl_ssi_trigger: start and stop the DMA transfer.
1088 * This function is called by ALSA to start, stop, pause, and resume the DMA
1091 * The DMA channel is in external master start and pause mode, which
1092 * means the SSI completely controls the flow of data.
1094 static int fsl_ssi_trigger(struct snd_pcm_substream
*substream
, int cmd
,
1095 struct snd_soc_dai
*dai
)
1097 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1098 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
1099 struct regmap
*regs
= ssi_private
->regs
;
1102 case SNDRV_PCM_TRIGGER_START
:
1103 case SNDRV_PCM_TRIGGER_RESUME
:
1104 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1105 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1106 fsl_ssi_tx_config(ssi_private
, true);
1108 fsl_ssi_rx_config(ssi_private
, true);
1111 case SNDRV_PCM_TRIGGER_STOP
:
1112 case SNDRV_PCM_TRIGGER_SUSPEND
:
1113 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1114 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1115 fsl_ssi_tx_config(ssi_private
, false);
1117 fsl_ssi_rx_config(ssi_private
, false);
1124 if (fsl_ssi_is_ac97(ssi_private
)) {
1125 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1126 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_TX_CLR
);
1128 regmap_write(regs
, CCSR_SSI_SOR
, CCSR_SSI_SOR_RX_CLR
);
1134 static int fsl_ssi_dai_probe(struct snd_soc_dai
*dai
)
1136 struct fsl_ssi_private
*ssi_private
= snd_soc_dai_get_drvdata(dai
);
1138 if (ssi_private
->soc
->imx
&& ssi_private
->use_dma
) {
1139 dai
->playback_dma_data
= &ssi_private
->dma_params_tx
;
1140 dai
->capture_dma_data
= &ssi_private
->dma_params_rx
;
1146 static const struct snd_soc_dai_ops fsl_ssi_dai_ops
= {
1147 .startup
= fsl_ssi_startup
,
1148 .shutdown
= fsl_ssi_shutdown
,
1149 .hw_params
= fsl_ssi_hw_params
,
1150 .hw_free
= fsl_ssi_hw_free
,
1151 .set_fmt
= fsl_ssi_set_dai_fmt
,
1152 .set_sysclk
= fsl_ssi_set_dai_sysclk
,
1153 .set_tdm_slot
= fsl_ssi_set_dai_tdm_slot
,
1154 .trigger
= fsl_ssi_trigger
,
1157 /* Template for the CPU dai driver structure */
1158 static struct snd_soc_dai_driver fsl_ssi_dai_template
= {
1159 .probe
= fsl_ssi_dai_probe
,
1161 .stream_name
= "CPU-Playback",
1164 .rates
= FSLSSI_I2S_RATES
,
1165 .formats
= FSLSSI_I2S_FORMATS
,
1168 .stream_name
= "CPU-Capture",
1171 .rates
= FSLSSI_I2S_RATES
,
1172 .formats
= FSLSSI_I2S_FORMATS
,
1174 .ops
= &fsl_ssi_dai_ops
,
1177 static const struct snd_soc_component_driver fsl_ssi_component
= {
1181 static struct snd_soc_dai_driver fsl_ssi_ac97_dai
= {
1182 .bus_control
= true,
1183 .probe
= fsl_ssi_dai_probe
,
1185 .stream_name
= "AC97 Playback",
1188 .rates
= SNDRV_PCM_RATE_8000_48000
,
1189 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1192 .stream_name
= "AC97 Capture",
1195 .rates
= SNDRV_PCM_RATE_48000
,
1196 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1198 .ops
= &fsl_ssi_dai_ops
,
1202 static struct fsl_ssi_private
*fsl_ac97_data
;
1204 static void fsl_ssi_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
1207 struct regmap
*regs
= fsl_ac97_data
->regs
;
1215 ret
= clk_prepare_enable(fsl_ac97_data
->clk
);
1217 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1223 regmap_write(regs
, CCSR_SSI_SACADD
, lreg
);
1226 regmap_write(regs
, CCSR_SSI_SACDAT
, lval
);
1228 regmap_update_bits(regs
, CCSR_SSI_SACNT
, CCSR_SSI_SACNT_RDWR_MASK
,
1232 clk_disable_unprepare(fsl_ac97_data
->clk
);
1235 static unsigned short fsl_ssi_ac97_read(struct snd_ac97
*ac97
,
1238 struct regmap
*regs
= fsl_ac97_data
->regs
;
1240 unsigned short val
= -1;
1245 ret
= clk_prepare_enable(fsl_ac97_data
->clk
);
1247 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1252 lreg
= (reg
& 0x7f) << 12;
1253 regmap_write(regs
, CCSR_SSI_SACADD
, lreg
);
1254 regmap_update_bits(regs
, CCSR_SSI_SACNT
, CCSR_SSI_SACNT_RDWR_MASK
,
1259 regmap_read(regs
, CCSR_SSI_SACDAT
, ®_val
);
1260 val
= (reg_val
>> 4) & 0xffff;
1262 clk_disable_unprepare(fsl_ac97_data
->clk
);
1267 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops
= {
1268 .read
= fsl_ssi_ac97_read
,
1269 .write
= fsl_ssi_ac97_write
,
1273 * Make every character in a string lower-case
1275 static void make_lowercase(char *s
)
1281 if ((c
>= 'A') && (c
<= 'Z'))
1282 *p
= c
+ ('a' - 'A');
1287 static int fsl_ssi_imx_probe(struct platform_device
*pdev
,
1288 struct fsl_ssi_private
*ssi_private
, void __iomem
*iomem
)
1290 struct device_node
*np
= pdev
->dev
.of_node
;
1294 if (ssi_private
->has_ipg_clk_name
)
1295 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, "ipg");
1297 ssi_private
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1298 if (IS_ERR(ssi_private
->clk
)) {
1299 ret
= PTR_ERR(ssi_private
->clk
);
1300 dev_err(&pdev
->dev
, "could not get clock: %d\n", ret
);
1304 if (!ssi_private
->has_ipg_clk_name
) {
1305 ret
= clk_prepare_enable(ssi_private
->clk
);
1307 dev_err(&pdev
->dev
, "clk_prepare_enable failed: %d\n", ret
);
1312 /* For those SLAVE implementations, we ignore non-baudclk cases
1313 * and, instead, abandon MASTER mode that needs baud clock.
1315 ssi_private
->baudclk
= devm_clk_get(&pdev
->dev
, "baud");
1316 if (IS_ERR(ssi_private
->baudclk
))
1317 dev_dbg(&pdev
->dev
, "could not get baud clock: %ld\n",
1318 PTR_ERR(ssi_private
->baudclk
));
1321 * We have burstsize be "fifo_depth - 2" to match the SSI
1322 * watermark setting in fsl_ssi_startup().
1324 ssi_private
->dma_params_tx
.maxburst
= ssi_private
->fifo_depth
- 2;
1325 ssi_private
->dma_params_rx
.maxburst
= ssi_private
->fifo_depth
- 2;
1326 ssi_private
->dma_params_tx
.addr
= ssi_private
->ssi_phys
+ CCSR_SSI_STX0
;
1327 ssi_private
->dma_params_rx
.addr
= ssi_private
->ssi_phys
+ CCSR_SSI_SRX0
;
1329 ret
= of_property_read_u32_array(np
, "dmas", dmas
, 4);
1330 if (ssi_private
->use_dma
&& !ret
&& dmas
[2] == IMX_DMATYPE_SSI_DUAL
) {
1331 ssi_private
->use_dual_fifo
= true;
1332 /* When using dual fifo mode, we need to keep watermark
1333 * as even numbers due to dma script limitation.
1335 ssi_private
->dma_params_tx
.maxburst
&= ~0x1;
1336 ssi_private
->dma_params_rx
.maxburst
&= ~0x1;
1339 if (!ssi_private
->use_dma
) {
1342 * Some boards use an incompatible codec. To get it
1343 * working, we are using imx-fiq-pcm-audio, that
1344 * can handle those codecs. DMA is not possible in this
1348 ssi_private
->fiq_params
.irq
= ssi_private
->irq
;
1349 ssi_private
->fiq_params
.base
= iomem
;
1350 ssi_private
->fiq_params
.dma_params_rx
=
1351 &ssi_private
->dma_params_rx
;
1352 ssi_private
->fiq_params
.dma_params_tx
=
1353 &ssi_private
->dma_params_tx
;
1355 ret
= imx_pcm_fiq_init(pdev
, &ssi_private
->fiq_params
);
1359 ret
= imx_pcm_dma_init(pdev
, IMX_SSI_DMABUF_SIZE
);
1368 if (!ssi_private
->has_ipg_clk_name
)
1369 clk_disable_unprepare(ssi_private
->clk
);
1373 static void fsl_ssi_imx_clean(struct platform_device
*pdev
,
1374 struct fsl_ssi_private
*ssi_private
)
1376 if (!ssi_private
->use_dma
)
1377 imx_pcm_fiq_exit(pdev
);
1378 if (!ssi_private
->has_ipg_clk_name
)
1379 clk_disable_unprepare(ssi_private
->clk
);
1382 static int fsl_ssi_probe(struct platform_device
*pdev
)
1384 struct fsl_ssi_private
*ssi_private
;
1386 struct device_node
*np
= pdev
->dev
.of_node
;
1387 const struct of_device_id
*of_id
;
1388 const char *p
, *sprop
;
1389 const uint32_t *iprop
;
1390 struct resource
*res
;
1391 void __iomem
*iomem
;
1393 struct regmap_config regconfig
= fsl_ssi_regconfig
;
1395 of_id
= of_match_device(fsl_ssi_ids
, &pdev
->dev
);
1396 if (!of_id
|| !of_id
->data
)
1399 ssi_private
= devm_kzalloc(&pdev
->dev
, sizeof(*ssi_private
),
1402 dev_err(&pdev
->dev
, "could not allocate DAI object\n");
1406 ssi_private
->soc
= of_id
->data
;
1408 sprop
= of_get_property(np
, "fsl,mode", NULL
);
1410 if (!strcmp(sprop
, "ac97-slave"))
1411 ssi_private
->dai_fmt
= SND_SOC_DAIFMT_AC97
;
1414 ssi_private
->use_dma
= !of_property_read_bool(np
,
1415 "fsl,fiq-stream-filter");
1417 if (fsl_ssi_is_ac97(ssi_private
)) {
1418 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_ac97_dai
,
1419 sizeof(fsl_ssi_ac97_dai
));
1421 fsl_ac97_data
= ssi_private
;
1423 ret
= snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops
, pdev
);
1425 dev_err(&pdev
->dev
, "could not set AC'97 ops\n");
1429 /* Initialize this copy of the CPU DAI driver structure */
1430 memcpy(&ssi_private
->cpu_dai_drv
, &fsl_ssi_dai_template
,
1431 sizeof(fsl_ssi_dai_template
));
1433 ssi_private
->cpu_dai_drv
.name
= dev_name(&pdev
->dev
);
1435 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1436 iomem
= devm_ioremap_resource(&pdev
->dev
, res
);
1438 return PTR_ERR(iomem
);
1439 ssi_private
->ssi_phys
= res
->start
;
1441 if (ssi_private
->soc
->imx21regs
) {
1443 * According to datasheet imx21-class SSI
1444 * don't have SACC{ST,EN,DIS} regs.
1446 regconfig
.max_register
= CCSR_SSI_SRMSK
;
1447 regconfig
.num_reg_defaults_raw
=
1448 CCSR_SSI_SRMSK
/ sizeof(uint32_t) + 1;
1451 ret
= of_property_match_string(np
, "clock-names", "ipg");
1453 ssi_private
->has_ipg_clk_name
= false;
1454 ssi_private
->regs
= devm_regmap_init_mmio(&pdev
->dev
, iomem
,
1457 ssi_private
->has_ipg_clk_name
= true;
1458 ssi_private
->regs
= devm_regmap_init_mmio_clk(&pdev
->dev
,
1459 "ipg", iomem
, ®config
);
1461 if (IS_ERR(ssi_private
->regs
)) {
1462 dev_err(&pdev
->dev
, "Failed to init register map\n");
1463 return PTR_ERR(ssi_private
->regs
);
1466 ssi_private
->irq
= platform_get_irq(pdev
, 0);
1467 if (ssi_private
->irq
< 0) {
1468 dev_err(&pdev
->dev
, "no irq for node %s\n", pdev
->name
);
1469 return ssi_private
->irq
;
1472 /* Are the RX and the TX clocks locked? */
1473 if (!of_find_property(np
, "fsl,ssi-asynchronous", NULL
)) {
1474 if (!fsl_ssi_is_ac97(ssi_private
))
1475 ssi_private
->cpu_dai_drv
.symmetric_rates
= 1;
1477 ssi_private
->cpu_dai_drv
.symmetric_channels
= 1;
1478 ssi_private
->cpu_dai_drv
.symmetric_samplebits
= 1;
1481 /* Determine the FIFO depth. */
1482 iprop
= of_get_property(np
, "fsl,fifo-depth", NULL
);
1484 ssi_private
->fifo_depth
= be32_to_cpup(iprop
);
1486 /* Older 8610 DTs didn't have the fifo-depth property */
1487 ssi_private
->fifo_depth
= 8;
1489 dev_set_drvdata(&pdev
->dev
, ssi_private
);
1491 if (ssi_private
->soc
->imx
) {
1492 ret
= fsl_ssi_imx_probe(pdev
, ssi_private
, iomem
);
1497 ret
= devm_snd_soc_register_component(&pdev
->dev
, &fsl_ssi_component
,
1498 &ssi_private
->cpu_dai_drv
, 1);
1500 dev_err(&pdev
->dev
, "failed to register DAI: %d\n", ret
);
1501 goto error_asoc_register
;
1504 if (ssi_private
->use_dma
) {
1505 ret
= devm_request_irq(&pdev
->dev
, ssi_private
->irq
,
1506 fsl_ssi_isr
, 0, dev_name(&pdev
->dev
),
1509 dev_err(&pdev
->dev
, "could not claim irq %u\n",
1511 goto error_asoc_register
;
1515 ret
= fsl_ssi_debugfs_create(&ssi_private
->dbg_stats
, &pdev
->dev
);
1517 goto error_asoc_register
;
1520 * If codec-handle property is missing from SSI node, we assume
1521 * that the machine driver uses new binding which does not require
1522 * SSI driver to trigger machine driver's probe.
1524 if (!of_get_property(np
, "codec-handle", NULL
))
1527 /* Trigger the machine driver's probe function. The platform driver
1528 * name of the machine driver is taken from /compatible property of the
1529 * device tree. We also pass the address of the CPU DAI driver
1532 sprop
= of_get_property(of_find_node_by_path("/"), "compatible", NULL
);
1533 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1534 p
= strrchr(sprop
, ',');
1537 snprintf(name
, sizeof(name
), "snd-soc-%s", sprop
);
1538 make_lowercase(name
);
1541 platform_device_register_data(&pdev
->dev
, name
, 0, NULL
, 0);
1542 if (IS_ERR(ssi_private
->pdev
)) {
1543 ret
= PTR_ERR(ssi_private
->pdev
);
1544 dev_err(&pdev
->dev
, "failed to register platform: %d\n", ret
);
1545 goto error_sound_card
;
1549 if (ssi_private
->dai_fmt
)
1550 _fsl_ssi_set_dai_fmt(&pdev
->dev
, ssi_private
,
1551 ssi_private
->dai_fmt
);
1553 if (fsl_ssi_is_ac97(ssi_private
)) {
1556 ret
= of_property_read_u32(np
, "cell-index", &ssi_idx
);
1558 dev_err(&pdev
->dev
, "cannot get SSI index property\n");
1559 goto error_sound_card
;
1563 platform_device_register_data(NULL
,
1564 "ac97-codec", ssi_idx
, NULL
, 0);
1565 if (IS_ERR(ssi_private
->pdev
)) {
1566 ret
= PTR_ERR(ssi_private
->pdev
);
1568 "failed to register AC97 codec platform: %d\n",
1570 goto error_sound_card
;
1577 fsl_ssi_debugfs_remove(&ssi_private
->dbg_stats
);
1579 error_asoc_register
:
1580 if (ssi_private
->soc
->imx
)
1581 fsl_ssi_imx_clean(pdev
, ssi_private
);
1586 static int fsl_ssi_remove(struct platform_device
*pdev
)
1588 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(&pdev
->dev
);
1590 fsl_ssi_debugfs_remove(&ssi_private
->dbg_stats
);
1592 if (ssi_private
->pdev
)
1593 platform_device_unregister(ssi_private
->pdev
);
1595 if (ssi_private
->soc
->imx
)
1596 fsl_ssi_imx_clean(pdev
, ssi_private
);
1598 if (fsl_ssi_is_ac97(ssi_private
))
1599 snd_soc_set_ac97_ops(NULL
);
1604 #ifdef CONFIG_PM_SLEEP
1605 static int fsl_ssi_suspend(struct device
*dev
)
1607 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(dev
);
1608 struct regmap
*regs
= ssi_private
->regs
;
1610 regmap_read(regs
, CCSR_SSI_SFCSR
,
1611 &ssi_private
->regcache_sfcsr
);
1612 regmap_read(regs
, CCSR_SSI_SACNT
,
1613 &ssi_private
->regcache_sacnt
);
1615 regcache_cache_only(regs
, true);
1616 regcache_mark_dirty(regs
);
1621 static int fsl_ssi_resume(struct device
*dev
)
1623 struct fsl_ssi_private
*ssi_private
= dev_get_drvdata(dev
);
1624 struct regmap
*regs
= ssi_private
->regs
;
1626 regcache_cache_only(regs
, false);
1628 regmap_update_bits(regs
, CCSR_SSI_SFCSR
,
1629 CCSR_SSI_SFCSR_RFWM1_MASK
| CCSR_SSI_SFCSR_TFWM1_MASK
|
1630 CCSR_SSI_SFCSR_RFWM0_MASK
| CCSR_SSI_SFCSR_TFWM0_MASK
,
1631 ssi_private
->regcache_sfcsr
);
1632 regmap_write(regs
, CCSR_SSI_SACNT
,
1633 ssi_private
->regcache_sacnt
);
1635 return regcache_sync(regs
);
1637 #endif /* CONFIG_PM_SLEEP */
1639 static const struct dev_pm_ops fsl_ssi_pm
= {
1640 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend
, fsl_ssi_resume
)
1643 static struct platform_driver fsl_ssi_driver
= {
1645 .name
= "fsl-ssi-dai",
1646 .of_match_table
= fsl_ssi_ids
,
1649 .probe
= fsl_ssi_probe
,
1650 .remove
= fsl_ssi_remove
,
1653 module_platform_driver(fsl_ssi_driver
);
1655 MODULE_ALIAS("platform:fsl-ssi-dai");
1656 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1657 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1658 MODULE_LICENSE("GPL v2");