2 * skl-sst-ipc.c - Intel skl IPC Support
4 * Copyright (C) 2014-15, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as version 2, as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 #include <linux/device.h>
17 #include "../common/sst-dsp.h"
18 #include "../common/sst-dsp-priv.h"
19 #include "skl-sst-dsp.h"
20 #include "skl-sst-ipc.h"
23 #define IPC_IXC_STATUS_BITS 24
25 /* Global Message - Generic */
26 #define IPC_GLB_TYPE_SHIFT 24
27 #define IPC_GLB_TYPE_MASK (0xf << IPC_GLB_TYPE_SHIFT)
28 #define IPC_GLB_TYPE(x) ((x) << IPC_GLB_TYPE_SHIFT)
30 /* Global Message - Reply */
31 #define IPC_GLB_REPLY_STATUS_SHIFT 24
32 #define IPC_GLB_REPLY_STATUS_MASK ((0x1 << IPC_GLB_REPLY_STATUS_SHIFT) - 1)
33 #define IPC_GLB_REPLY_STATUS(x) ((x) << IPC_GLB_REPLY_STATUS_SHIFT)
35 #define IPC_TIMEOUT_MSECS 3000
37 #define IPC_EMPTY_LIST_SIZE 8
39 #define IPC_MSG_TARGET_SHIFT 30
40 #define IPC_MSG_TARGET_MASK 0x1
41 #define IPC_MSG_TARGET(x) (((x) & IPC_MSG_TARGET_MASK) \
42 << IPC_MSG_TARGET_SHIFT)
44 #define IPC_MSG_DIR_SHIFT 29
45 #define IPC_MSG_DIR_MASK 0x1
46 #define IPC_MSG_DIR(x) (((x) & IPC_MSG_DIR_MASK) \
48 /* Global Notification Message */
49 #define IPC_GLB_NOTIFY_TYPE_SHIFT 16
50 #define IPC_GLB_NOTIFY_TYPE_MASK 0xFF
51 #define IPC_GLB_NOTIFY_TYPE(x) (((x) >> IPC_GLB_NOTIFY_TYPE_SHIFT) \
52 & IPC_GLB_NOTIFY_TYPE_MASK)
54 #define IPC_GLB_NOTIFY_MSG_TYPE_SHIFT 24
55 #define IPC_GLB_NOTIFY_MSG_TYPE_MASK 0x1F
56 #define IPC_GLB_NOTIFY_MSG_TYPE(x) (((x) >> IPC_GLB_NOTIFY_MSG_TYPE_SHIFT) \
57 & IPC_GLB_NOTIFY_MSG_TYPE_MASK)
59 #define IPC_GLB_NOTIFY_RSP_SHIFT 29
60 #define IPC_GLB_NOTIFY_RSP_MASK 0x1
61 #define IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> IPC_GLB_NOTIFY_RSP_SHIFT) \
62 & IPC_GLB_NOTIFY_RSP_MASK)
64 /* Pipeline operations */
66 /* Create pipeline message */
67 #define IPC_PPL_MEM_SIZE_SHIFT 0
68 #define IPC_PPL_MEM_SIZE_MASK 0x7FF
69 #define IPC_PPL_MEM_SIZE(x) (((x) & IPC_PPL_MEM_SIZE_MASK) \
70 << IPC_PPL_MEM_SIZE_SHIFT)
72 #define IPC_PPL_TYPE_SHIFT 11
73 #define IPC_PPL_TYPE_MASK 0x1F
74 #define IPC_PPL_TYPE(x) (((x) & IPC_PPL_TYPE_MASK) \
75 << IPC_PPL_TYPE_SHIFT)
77 #define IPC_INSTANCE_ID_SHIFT 16
78 #define IPC_INSTANCE_ID_MASK 0xFF
79 #define IPC_INSTANCE_ID(x) (((x) & IPC_INSTANCE_ID_MASK) \
80 << IPC_INSTANCE_ID_SHIFT)
82 /* Set pipeline state message */
83 #define IPC_PPL_STATE_SHIFT 0
84 #define IPC_PPL_STATE_MASK 0x1F
85 #define IPC_PPL_STATE(x) (((x) & IPC_PPL_STATE_MASK) \
86 << IPC_PPL_STATE_SHIFT)
88 /* Module operations primary register */
89 #define IPC_MOD_ID_SHIFT 0
90 #define IPC_MOD_ID_MASK 0xFFFF
91 #define IPC_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
94 #define IPC_MOD_INSTANCE_ID_SHIFT 16
95 #define IPC_MOD_INSTANCE_ID_MASK 0xFF
96 #define IPC_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
97 << IPC_MOD_INSTANCE_ID_SHIFT)
99 /* Init instance message extension register */
100 #define IPC_PARAM_BLOCK_SIZE_SHIFT 0
101 #define IPC_PARAM_BLOCK_SIZE_MASK 0xFFFF
102 #define IPC_PARAM_BLOCK_SIZE(x) (((x) & IPC_PARAM_BLOCK_SIZE_MASK) \
103 << IPC_PARAM_BLOCK_SIZE_SHIFT)
105 #define IPC_PPL_INSTANCE_ID_SHIFT 16
106 #define IPC_PPL_INSTANCE_ID_MASK 0xFF
107 #define IPC_PPL_INSTANCE_ID(x) (((x) & IPC_PPL_INSTANCE_ID_MASK) \
108 << IPC_PPL_INSTANCE_ID_SHIFT)
110 #define IPC_CORE_ID_SHIFT 24
111 #define IPC_CORE_ID_MASK 0x1F
112 #define IPC_CORE_ID(x) (((x) & IPC_CORE_ID_MASK) \
113 << IPC_CORE_ID_SHIFT)
115 /* Bind/Unbind message extension register */
116 #define IPC_DST_MOD_ID_SHIFT 0
117 #define IPC_DST_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
118 << IPC_DST_MOD_ID_SHIFT)
120 #define IPC_DST_MOD_INSTANCE_ID_SHIFT 16
121 #define IPC_DST_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
122 << IPC_DST_MOD_INSTANCE_ID_SHIFT)
124 #define IPC_DST_QUEUE_SHIFT 24
125 #define IPC_DST_QUEUE_MASK 0x7
126 #define IPC_DST_QUEUE(x) (((x) & IPC_DST_QUEUE_MASK) \
127 << IPC_DST_QUEUE_SHIFT)
129 #define IPC_SRC_QUEUE_SHIFT 27
130 #define IPC_SRC_QUEUE_MASK 0x7
131 #define IPC_SRC_QUEUE(x) (((x) & IPC_SRC_QUEUE_MASK) \
132 << IPC_SRC_QUEUE_SHIFT)
133 /* Load Module count */
134 #define IPC_LOAD_MODULE_SHIFT 0
135 #define IPC_LOAD_MODULE_MASK 0xFF
136 #define IPC_LOAD_MODULE_CNT(x) (((x) & IPC_LOAD_MODULE_MASK) \
137 << IPC_LOAD_MODULE_SHIFT)
139 /* Save pipeline messgae extension register */
140 #define IPC_DMA_ID_SHIFT 0
141 #define IPC_DMA_ID_MASK 0x1F
142 #define IPC_DMA_ID(x) (((x) & IPC_DMA_ID_MASK) \
144 /* Large Config message extension register */
145 #define IPC_DATA_OFFSET_SZ_SHIFT 0
146 #define IPC_DATA_OFFSET_SZ_MASK 0xFFFFF
147 #define IPC_DATA_OFFSET_SZ(x) (((x) & IPC_DATA_OFFSET_SZ_MASK) \
148 << IPC_DATA_OFFSET_SZ_SHIFT)
149 #define IPC_DATA_OFFSET_SZ_CLEAR ~(IPC_DATA_OFFSET_SZ_MASK \
150 << IPC_DATA_OFFSET_SZ_SHIFT)
152 #define IPC_LARGE_PARAM_ID_SHIFT 20
153 #define IPC_LARGE_PARAM_ID_MASK 0xFF
154 #define IPC_LARGE_PARAM_ID(x) (((x) & IPC_LARGE_PARAM_ID_MASK) \
155 << IPC_LARGE_PARAM_ID_SHIFT)
157 #define IPC_FINAL_BLOCK_SHIFT 28
158 #define IPC_FINAL_BLOCK_MASK 0x1
159 #define IPC_FINAL_BLOCK(x) (((x) & IPC_FINAL_BLOCK_MASK) \
160 << IPC_FINAL_BLOCK_SHIFT)
162 #define IPC_INITIAL_BLOCK_SHIFT 29
163 #define IPC_INITIAL_BLOCK_MASK 0x1
164 #define IPC_INITIAL_BLOCK(x) (((x) & IPC_INITIAL_BLOCK_MASK) \
165 << IPC_INITIAL_BLOCK_SHIFT)
166 #define IPC_INITIAL_BLOCK_CLEAR ~(IPC_INITIAL_BLOCK_MASK \
167 << IPC_INITIAL_BLOCK_SHIFT)
169 enum skl_ipc_msg_target
{
174 enum skl_ipc_msg_direction
{
179 /* Global Message Types */
180 enum skl_ipc_glb_type
{
181 IPC_GLB_GET_FW_VERSION
= 0, /* Retrieves firmware version */
182 IPC_GLB_LOAD_MULTIPLE_MODS
= 15,
183 IPC_GLB_UNLOAD_MULTIPLE_MODS
= 16,
184 IPC_GLB_CREATE_PPL
= 17,
185 IPC_GLB_DELETE_PPL
= 18,
186 IPC_GLB_SET_PPL_STATE
= 19,
187 IPC_GLB_GET_PPL_STATE
= 20,
188 IPC_GLB_GET_PPL_CONTEXT_SIZE
= 21,
189 IPC_GLB_SAVE_PPL
= 22,
190 IPC_GLB_RESTORE_PPL
= 23,
192 IPC_GLB_MAX_IPC_MSG_NUMBER
= 31 /* Maximum message number */
195 enum skl_ipc_glb_reply
{
196 IPC_GLB_REPLY_SUCCESS
= 0,
198 IPC_GLB_REPLY_UNKNOWN_MSG_TYPE
= 1,
199 IPC_GLB_REPLY_ERROR_INVALID_PARAM
= 2,
201 IPC_GLB_REPLY_BUSY
= 3,
202 IPC_GLB_REPLY_PENDING
= 4,
203 IPC_GLB_REPLY_FAILURE
= 5,
204 IPC_GLB_REPLY_INVALID_REQUEST
= 6,
206 IPC_GLB_REPLY_OUT_OF_MEMORY
= 7,
207 IPC_GLB_REPLY_OUT_OF_MIPS
= 8,
209 IPC_GLB_REPLY_INVALID_RESOURCE_ID
= 9,
210 IPC_GLB_REPLY_INVALID_RESOURCE_STATE
= 10,
212 IPC_GLB_REPLY_MOD_MGMT_ERROR
= 100,
213 IPC_GLB_REPLY_MOD_LOAD_CL_FAILED
= 101,
214 IPC_GLB_REPLY_MOD_LOAD_INVALID_HASH
= 102,
216 IPC_GLB_REPLY_MOD_UNLOAD_INST_EXIST
= 103,
217 IPC_GLB_REPLY_MOD_NOT_INITIALIZED
= 104,
219 IPC_GLB_REPLY_INVALID_CONFIG_PARAM_ID
= 120,
220 IPC_GLB_REPLY_INVALID_CONFIG_DATA_LEN
= 121,
221 IPC_GLB_REPLY_GATEWAY_NOT_INITIALIZED
= 140,
222 IPC_GLB_REPLY_GATEWAY_NOT_EXIST
= 141,
224 IPC_GLB_REPLY_PPL_NOT_INITIALIZED
= 160,
225 IPC_GLB_REPLY_PPL_NOT_EXIST
= 161,
226 IPC_GLB_REPLY_PPL_SAVE_FAILED
= 162,
227 IPC_GLB_REPLY_PPL_RESTORE_FAILED
= 163,
229 IPC_MAX_STATUS
= ((1<<IPC_IXC_STATUS_BITS
)-1)
232 enum skl_ipc_notification_type
{
233 IPC_GLB_NOTIFY_GLITCH
= 0,
234 IPC_GLB_NOTIFY_OVERRUN
= 1,
235 IPC_GLB_NOTIFY_UNDERRUN
= 2,
236 IPC_GLB_NOTIFY_END_STREAM
= 3,
237 IPC_GLB_NOTIFY_PHRASE_DETECTED
= 4,
238 IPC_GLB_NOTIFY_RESOURCE_EVENT
= 5,
239 IPC_GLB_NOTIFY_LOG_BUFFER_STATUS
= 6,
240 IPC_GLB_NOTIFY_TIMESTAMP_CAPTURED
= 7,
241 IPC_GLB_NOTIFY_FW_READY
= 8
244 /* Module Message Types */
245 enum skl_ipc_module_msg
{
246 IPC_MOD_INIT_INSTANCE
= 0,
247 IPC_MOD_CONFIG_GET
= 1,
248 IPC_MOD_CONFIG_SET
= 2,
249 IPC_MOD_LARGE_CONFIG_GET
= 3,
250 IPC_MOD_LARGE_CONFIG_SET
= 4,
256 static void skl_ipc_tx_data_copy(struct ipc_message
*msg
, char *tx_data
,
260 memcpy(msg
->tx_data
, tx_data
, tx_size
);
263 static bool skl_ipc_is_dsp_busy(struct sst_dsp
*dsp
)
267 hipci
= sst_dsp_shim_read_unlocked(dsp
, SKL_ADSP_REG_HIPCI
);
268 return (hipci
& SKL_ADSP_REG_HIPCI_BUSY
);
271 /* Lock to be held by caller */
272 static void skl_ipc_tx_msg(struct sst_generic_ipc
*ipc
, struct ipc_message
*msg
)
274 struct skl_ipc_header
*header
= (struct skl_ipc_header
*)(&msg
->header
);
277 sst_dsp_outbox_write(ipc
->dsp
, msg
->tx_data
, msg
->tx_size
);
278 sst_dsp_shim_write_unlocked(ipc
->dsp
, SKL_ADSP_REG_HIPCIE
,
280 sst_dsp_shim_write_unlocked(ipc
->dsp
, SKL_ADSP_REG_HIPCI
,
281 header
->primary
| SKL_ADSP_REG_HIPCI_BUSY
);
284 static struct ipc_message
*skl_ipc_reply_get_msg(struct sst_generic_ipc
*ipc
,
287 struct ipc_message
*msg
= NULL
;
288 struct skl_ipc_header
*header
= (struct skl_ipc_header
*)(&ipc_header
);
290 if (list_empty(&ipc
->rx_list
)) {
291 dev_err(ipc
->dev
, "ipc: rx list is empty but received 0x%x\n",
296 msg
= list_first_entry(&ipc
->rx_list
, struct ipc_message
, list
);
303 static int skl_ipc_process_notification(struct sst_generic_ipc
*ipc
,
304 struct skl_ipc_header header
)
306 struct skl_sst
*skl
= container_of(ipc
, struct skl_sst
, ipc
);
308 if (IPC_GLB_NOTIFY_MSG_TYPE(header
.primary
)) {
309 switch (IPC_GLB_NOTIFY_TYPE(header
.primary
)) {
311 case IPC_GLB_NOTIFY_UNDERRUN
:
312 dev_err(ipc
->dev
, "FW Underrun %x\n", header
.primary
);
315 case IPC_GLB_NOTIFY_RESOURCE_EVENT
:
316 dev_err(ipc
->dev
, "MCPS Budget Violation: %x\n",
320 case IPC_GLB_NOTIFY_FW_READY
:
321 skl
->boot_complete
= true;
322 wake_up(&skl
->boot_wait
);
326 dev_err(ipc
->dev
, "ipc: Unhandled error msg=%x",
335 static void skl_ipc_process_reply(struct sst_generic_ipc
*ipc
,
336 struct skl_ipc_header header
)
338 struct ipc_message
*msg
;
339 u32 reply
= header
.primary
& IPC_GLB_REPLY_STATUS_MASK
;
340 u64
*ipc_header
= (u64
*)(&header
);
342 msg
= skl_ipc_reply_get_msg(ipc
, *ipc_header
);
344 dev_dbg(ipc
->dev
, "ipc: rx list is empty\n");
348 /* first process the header */
350 case IPC_GLB_REPLY_SUCCESS
:
351 dev_info(ipc
->dev
, "ipc FW reply %x: success\n", header
.primary
);
354 case IPC_GLB_REPLY_OUT_OF_MEMORY
:
355 dev_err(ipc
->dev
, "ipc fw reply: %x: no memory\n", header
.primary
);
356 msg
->errno
= -ENOMEM
;
359 case IPC_GLB_REPLY_BUSY
:
360 dev_err(ipc
->dev
, "ipc fw reply: %x: Busy\n", header
.primary
);
365 dev_err(ipc
->dev
, "Unknown ipc reply: 0x%x", reply
);
366 msg
->errno
= -EINVAL
;
370 if (reply
!= IPC_GLB_REPLY_SUCCESS
) {
371 dev_err(ipc
->dev
, "ipc FW reply: reply=%d", reply
);
372 dev_err(ipc
->dev
, "FW Error Code: %u\n",
373 ipc
->dsp
->fw_ops
.get_fw_errcode(ipc
->dsp
));
376 list_del(&msg
->list
);
377 sst_ipc_tx_msg_reply_complete(ipc
, msg
);
380 irqreturn_t
skl_dsp_irq_thread_handler(int irq
, void *context
)
382 struct sst_dsp
*dsp
= context
;
383 struct skl_sst
*skl
= sst_dsp_get_thread_context(dsp
);
384 struct sst_generic_ipc
*ipc
= &skl
->ipc
;
385 struct skl_ipc_header header
= {0};
386 u32 hipcie
, hipct
, hipcte
;
389 if (dsp
->intr_status
& SKL_ADSPIS_CL_DMA
)
390 skl_cldma_process_intr(dsp
);
392 /* Here we handle IPC interrupts only */
393 if (!(dsp
->intr_status
& SKL_ADSPIS_IPC
))
396 hipcie
= sst_dsp_shim_read_unlocked(dsp
, SKL_ADSP_REG_HIPCIE
);
397 hipct
= sst_dsp_shim_read_unlocked(dsp
, SKL_ADSP_REG_HIPCT
);
399 /* reply message from DSP */
400 if (hipcie
& SKL_ADSP_REG_HIPCIE_DONE
) {
401 sst_dsp_shim_update_bits(dsp
, SKL_ADSP_REG_HIPCCTL
,
402 SKL_ADSP_REG_HIPCCTL_DONE
, 0);
404 /* clear DONE bit - tell DSP we have completed the operation */
405 sst_dsp_shim_update_bits_forced(dsp
, SKL_ADSP_REG_HIPCIE
,
406 SKL_ADSP_REG_HIPCIE_DONE
, SKL_ADSP_REG_HIPCIE_DONE
);
410 /* unmask Done interrupt */
411 sst_dsp_shim_update_bits(dsp
, SKL_ADSP_REG_HIPCCTL
,
412 SKL_ADSP_REG_HIPCCTL_DONE
, SKL_ADSP_REG_HIPCCTL_DONE
);
415 /* New message from DSP */
416 if (hipct
& SKL_ADSP_REG_HIPCT_BUSY
) {
417 hipcte
= sst_dsp_shim_read_unlocked(dsp
, SKL_ADSP_REG_HIPCTE
);
418 header
.primary
= hipct
;
419 header
.extension
= hipcte
;
420 dev_dbg(dsp
->dev
, "IPC irq: Firmware respond primary:%x",
422 dev_dbg(dsp
->dev
, "IPC irq: Firmware respond extension:%x",
425 if (IPC_GLB_NOTIFY_RSP_TYPE(header
.primary
)) {
426 /* Handle Immediate reply from DSP Core */
427 skl_ipc_process_reply(ipc
, header
);
429 dev_dbg(dsp
->dev
, "IPC irq: Notification from firmware\n");
430 skl_ipc_process_notification(ipc
, header
);
432 /* clear busy interrupt */
433 sst_dsp_shim_update_bits_forced(dsp
, SKL_ADSP_REG_HIPCT
,
434 SKL_ADSP_REG_HIPCT_BUSY
, SKL_ADSP_REG_HIPCT_BUSY
);
441 skl_ipc_int_enable(dsp
);
443 /* continue to send any remaining messages... */
444 queue_kthread_work(&ipc
->kworker
, &ipc
->kwork
);
449 void skl_ipc_int_enable(struct sst_dsp
*ctx
)
451 sst_dsp_shim_update_bits(ctx
, SKL_ADSP_REG_ADSPIC
,
452 SKL_ADSPIC_IPC
, SKL_ADSPIC_IPC
);
455 void skl_ipc_int_disable(struct sst_dsp
*ctx
)
457 sst_dsp_shim_update_bits_unlocked(ctx
, SKL_ADSP_REG_ADSPIC
,
461 void skl_ipc_op_int_enable(struct sst_dsp
*ctx
)
463 /* enable IPC DONE interrupt */
464 sst_dsp_shim_update_bits(ctx
, SKL_ADSP_REG_HIPCCTL
,
465 SKL_ADSP_REG_HIPCCTL_DONE
, SKL_ADSP_REG_HIPCCTL_DONE
);
467 /* Enable IPC BUSY interrupt */
468 sst_dsp_shim_update_bits(ctx
, SKL_ADSP_REG_HIPCCTL
,
469 SKL_ADSP_REG_HIPCCTL_BUSY
, SKL_ADSP_REG_HIPCCTL_BUSY
);
472 void skl_ipc_op_int_disable(struct sst_dsp
*ctx
)
474 /* disable IPC DONE interrupt */
475 sst_dsp_shim_update_bits_unlocked(ctx
, SKL_ADSP_REG_HIPCCTL
,
476 SKL_ADSP_REG_HIPCCTL_DONE
, 0);
478 /* Disable IPC BUSY interrupt */
479 sst_dsp_shim_update_bits_unlocked(ctx
, SKL_ADSP_REG_HIPCCTL
,
480 SKL_ADSP_REG_HIPCCTL_BUSY
, 0);
484 bool skl_ipc_int_status(struct sst_dsp
*ctx
)
486 return sst_dsp_shim_read_unlocked(ctx
,
487 SKL_ADSP_REG_ADSPIS
) & SKL_ADSPIS_IPC
;
490 int skl_ipc_init(struct device
*dev
, struct skl_sst
*skl
)
492 struct sst_generic_ipc
*ipc
;
499 ipc
->tx_data_max_size
= SKL_ADSP_W1_SZ
;
500 ipc
->rx_data_max_size
= SKL_ADSP_W0_UP_SZ
;
502 err
= sst_ipc_init(ipc
);
506 ipc
->ops
.tx_msg
= skl_ipc_tx_msg
;
507 ipc
->ops
.tx_data_copy
= skl_ipc_tx_data_copy
;
508 ipc
->ops
.is_dsp_busy
= skl_ipc_is_dsp_busy
;
513 void skl_ipc_free(struct sst_generic_ipc
*ipc
)
515 /* Disable IPC DONE interrupt */
516 sst_dsp_shim_update_bits(ipc
->dsp
, SKL_ADSP_REG_HIPCCTL
,
517 SKL_ADSP_REG_HIPCCTL_DONE
, 0);
519 /* Disable IPC BUSY interrupt */
520 sst_dsp_shim_update_bits(ipc
->dsp
, SKL_ADSP_REG_HIPCCTL
,
521 SKL_ADSP_REG_HIPCCTL_BUSY
, 0);
526 int skl_ipc_create_pipeline(struct sst_generic_ipc
*ipc
,
527 u16 ppl_mem_size
, u8 ppl_type
, u8 instance_id
)
529 struct skl_ipc_header header
= {0};
530 u64
*ipc_header
= (u64
*)(&header
);
533 header
.primary
= IPC_MSG_TARGET(IPC_FW_GEN_MSG
);
534 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
535 header
.primary
|= IPC_GLB_TYPE(IPC_GLB_CREATE_PPL
);
536 header
.primary
|= IPC_INSTANCE_ID(instance_id
);
537 header
.primary
|= IPC_PPL_TYPE(ppl_type
);
538 header
.primary
|= IPC_PPL_MEM_SIZE(ppl_mem_size
);
540 dev_dbg(ipc
->dev
, "In %s header=%d\n", __func__
, header
.primary
);
541 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, NULL
, 0, NULL
, 0);
543 dev_err(ipc
->dev
, "ipc: create pipeline fail, err: %d\n", ret
);
549 EXPORT_SYMBOL_GPL(skl_ipc_create_pipeline
);
551 int skl_ipc_delete_pipeline(struct sst_generic_ipc
*ipc
, u8 instance_id
)
553 struct skl_ipc_header header
= {0};
554 u64
*ipc_header
= (u64
*)(&header
);
557 header
.primary
= IPC_MSG_TARGET(IPC_FW_GEN_MSG
);
558 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
559 header
.primary
|= IPC_GLB_TYPE(IPC_GLB_DELETE_PPL
);
560 header
.primary
|= IPC_INSTANCE_ID(instance_id
);
562 dev_dbg(ipc
->dev
, "In %s header=%d\n", __func__
, header
.primary
);
563 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, NULL
, 0, NULL
, 0);
565 dev_err(ipc
->dev
, "ipc: delete pipeline failed, err %d\n", ret
);
571 EXPORT_SYMBOL_GPL(skl_ipc_delete_pipeline
);
573 int skl_ipc_set_pipeline_state(struct sst_generic_ipc
*ipc
,
574 u8 instance_id
, enum skl_ipc_pipeline_state state
)
576 struct skl_ipc_header header
= {0};
577 u64
*ipc_header
= (u64
*)(&header
);
580 header
.primary
= IPC_MSG_TARGET(IPC_FW_GEN_MSG
);
581 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
582 header
.primary
|= IPC_GLB_TYPE(IPC_GLB_SET_PPL_STATE
);
583 header
.primary
|= IPC_INSTANCE_ID(instance_id
);
584 header
.primary
|= IPC_PPL_STATE(state
);
586 dev_dbg(ipc
->dev
, "In %s header=%d\n", __func__
, header
.primary
);
587 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, NULL
, 0, NULL
, 0);
589 dev_err(ipc
->dev
, "ipc: set pipeline state failed, err: %d\n", ret
);
594 EXPORT_SYMBOL_GPL(skl_ipc_set_pipeline_state
);
597 skl_ipc_save_pipeline(struct sst_generic_ipc
*ipc
, u8 instance_id
, int dma_id
)
599 struct skl_ipc_header header
= {0};
600 u64
*ipc_header
= (u64
*)(&header
);
603 header
.primary
= IPC_MSG_TARGET(IPC_FW_GEN_MSG
);
604 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
605 header
.primary
|= IPC_GLB_TYPE(IPC_GLB_SAVE_PPL
);
606 header
.primary
|= IPC_INSTANCE_ID(instance_id
);
608 header
.extension
= IPC_DMA_ID(dma_id
);
609 dev_dbg(ipc
->dev
, "In %s header=%d\n", __func__
, header
.primary
);
610 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, NULL
, 0, NULL
, 0);
612 dev_err(ipc
->dev
, "ipc: save pipeline failed, err: %d\n", ret
);
618 EXPORT_SYMBOL_GPL(skl_ipc_save_pipeline
);
620 int skl_ipc_restore_pipeline(struct sst_generic_ipc
*ipc
, u8 instance_id
)
622 struct skl_ipc_header header
= {0};
623 u64
*ipc_header
= (u64
*)(&header
);
626 header
.primary
= IPC_MSG_TARGET(IPC_FW_GEN_MSG
);
627 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
628 header
.primary
|= IPC_GLB_TYPE(IPC_GLB_RESTORE_PPL
);
629 header
.primary
|= IPC_INSTANCE_ID(instance_id
);
631 dev_dbg(ipc
->dev
, "In %s header=%d\n", __func__
, header
.primary
);
632 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, NULL
, 0, NULL
, 0);
634 dev_err(ipc
->dev
, "ipc: restore pipeline failed, err: %d\n", ret
);
640 EXPORT_SYMBOL_GPL(skl_ipc_restore_pipeline
);
642 int skl_ipc_set_dx(struct sst_generic_ipc
*ipc
, u8 instance_id
,
643 u16 module_id
, struct skl_ipc_dxstate_info
*dx
)
645 struct skl_ipc_header header
= {0};
646 u64
*ipc_header
= (u64
*)(&header
);
649 header
.primary
= IPC_MSG_TARGET(IPC_MOD_MSG
);
650 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
651 header
.primary
|= IPC_GLB_TYPE(IPC_MOD_SET_DX
);
652 header
.primary
|= IPC_MOD_INSTANCE_ID(instance_id
);
653 header
.primary
|= IPC_MOD_ID(module_id
);
655 dev_dbg(ipc
->dev
, "In %s primary =%x ext=%x\n", __func__
,
656 header
.primary
, header
.extension
);
657 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
,
658 dx
, sizeof(*dx
), NULL
, 0);
660 dev_err(ipc
->dev
, "ipc: set dx failed, err %d\n", ret
);
666 EXPORT_SYMBOL_GPL(skl_ipc_set_dx
);
668 int skl_ipc_init_instance(struct sst_generic_ipc
*ipc
,
669 struct skl_ipc_init_instance_msg
*msg
, void *param_data
)
671 struct skl_ipc_header header
= {0};
672 u64
*ipc_header
= (u64
*)(&header
);
674 u32
*buffer
= (u32
*)param_data
;
675 /* param_block_size must be in dwords */
676 u16 param_block_size
= msg
->param_data_size
/ sizeof(u32
);
678 print_hex_dump(KERN_DEBUG
, NULL
, DUMP_PREFIX_NONE
,
679 16, 4, buffer
, param_block_size
, false);
681 header
.primary
= IPC_MSG_TARGET(IPC_MOD_MSG
);
682 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
683 header
.primary
|= IPC_GLB_TYPE(IPC_MOD_INIT_INSTANCE
);
684 header
.primary
|= IPC_MOD_INSTANCE_ID(msg
->instance_id
);
685 header
.primary
|= IPC_MOD_ID(msg
->module_id
);
687 header
.extension
= IPC_CORE_ID(msg
->core_id
);
688 header
.extension
|= IPC_PPL_INSTANCE_ID(msg
->ppl_instance_id
);
689 header
.extension
|= IPC_PARAM_BLOCK_SIZE(param_block_size
);
691 dev_dbg(ipc
->dev
, "In %s primary =%x ext=%x\n", __func__
,
692 header
.primary
, header
.extension
);
693 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, param_data
,
694 msg
->param_data_size
, NULL
, 0);
697 dev_err(ipc
->dev
, "ipc: init instance failed\n");
703 EXPORT_SYMBOL_GPL(skl_ipc_init_instance
);
705 int skl_ipc_bind_unbind(struct sst_generic_ipc
*ipc
,
706 struct skl_ipc_bind_unbind_msg
*msg
)
708 struct skl_ipc_header header
= {0};
709 u64
*ipc_header
= (u64
*)(&header
);
710 u8 bind_unbind
= msg
->bind
? IPC_MOD_BIND
: IPC_MOD_UNBIND
;
713 header
.primary
= IPC_MSG_TARGET(IPC_MOD_MSG
);
714 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
715 header
.primary
|= IPC_GLB_TYPE(bind_unbind
);
716 header
.primary
|= IPC_MOD_INSTANCE_ID(msg
->instance_id
);
717 header
.primary
|= IPC_MOD_ID(msg
->module_id
);
719 header
.extension
= IPC_DST_MOD_ID(msg
->dst_module_id
);
720 header
.extension
|= IPC_DST_MOD_INSTANCE_ID(msg
->dst_instance_id
);
721 header
.extension
|= IPC_DST_QUEUE(msg
->dst_queue
);
722 header
.extension
|= IPC_SRC_QUEUE(msg
->src_queue
);
724 dev_dbg(ipc
->dev
, "In %s hdr=%x ext=%x\n", __func__
, header
.primary
,
726 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, NULL
, 0, NULL
, 0);
728 dev_err(ipc
->dev
, "ipc: bind/unbind faileden");
734 EXPORT_SYMBOL_GPL(skl_ipc_bind_unbind
);
737 * In order to load a module we need to send IPC to initiate that. DMA will
738 * performed to load the module memory. The FW supports multiple module load
739 * at single shot, so we can send IPC with N modules represented by
742 int skl_ipc_load_modules(struct sst_generic_ipc
*ipc
,
743 u8 module_cnt
, void *data
)
745 struct skl_ipc_header header
= {0};
746 u64
*ipc_header
= (u64
*)(&header
);
749 header
.primary
= IPC_MSG_TARGET(IPC_FW_GEN_MSG
);
750 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
751 header
.primary
|= IPC_GLB_TYPE(IPC_GLB_LOAD_MULTIPLE_MODS
);
752 header
.primary
|= IPC_LOAD_MODULE_CNT(module_cnt
);
754 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, data
,
755 (sizeof(u16
) * module_cnt
), NULL
, 0);
757 dev_err(ipc
->dev
, "ipc: load modules failed :%d\n", ret
);
761 EXPORT_SYMBOL_GPL(skl_ipc_load_modules
);
763 int skl_ipc_unload_modules(struct sst_generic_ipc
*ipc
, u8 module_cnt
,
766 struct skl_ipc_header header
= {0};
767 u64
*ipc_header
= (u64
*)(&header
);
770 header
.primary
= IPC_MSG_TARGET(IPC_FW_GEN_MSG
);
771 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
772 header
.primary
|= IPC_GLB_TYPE(IPC_GLB_UNLOAD_MULTIPLE_MODS
);
773 header
.primary
|= IPC_LOAD_MODULE_CNT(module_cnt
);
775 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
, data
,
776 (sizeof(u16
) * module_cnt
), NULL
, 0);
778 dev_err(ipc
->dev
, "ipc: unload modules failed :%d\n", ret
);
782 EXPORT_SYMBOL_GPL(skl_ipc_unload_modules
);
784 int skl_ipc_set_large_config(struct sst_generic_ipc
*ipc
,
785 struct skl_ipc_large_config_msg
*msg
, u32
*param
)
787 struct skl_ipc_header header
= {0};
788 u64
*ipc_header
= (u64
*)(&header
);
790 size_t sz_remaining
, tx_size
, data_offset
;
792 header
.primary
= IPC_MSG_TARGET(IPC_MOD_MSG
);
793 header
.primary
|= IPC_MSG_DIR(IPC_MSG_REQUEST
);
794 header
.primary
|= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_SET
);
795 header
.primary
|= IPC_MOD_INSTANCE_ID(msg
->instance_id
);
796 header
.primary
|= IPC_MOD_ID(msg
->module_id
);
798 header
.extension
= IPC_DATA_OFFSET_SZ(msg
->param_data_size
);
799 header
.extension
|= IPC_LARGE_PARAM_ID(msg
->large_param_id
);
800 header
.extension
|= IPC_FINAL_BLOCK(0);
801 header
.extension
|= IPC_INITIAL_BLOCK(1);
803 sz_remaining
= msg
->param_data_size
;
805 while (sz_remaining
!= 0) {
806 tx_size
= sz_remaining
> SKL_ADSP_W1_SZ
807 ? SKL_ADSP_W1_SZ
: sz_remaining
;
808 if (tx_size
== sz_remaining
)
809 header
.extension
|= IPC_FINAL_BLOCK(1);
811 dev_dbg(ipc
->dev
, "In %s primary=%#x ext=%#x\n", __func__
,
812 header
.primary
, header
.extension
);
813 dev_dbg(ipc
->dev
, "transmitting offset: %#x, size: %#x\n",
814 (unsigned)data_offset
, (unsigned)tx_size
);
815 ret
= sst_ipc_tx_message_wait(ipc
, *ipc_header
,
816 ((char *)param
) + data_offset
,
820 "ipc: set large config fail, err: %d\n", ret
);
823 sz_remaining
-= tx_size
;
824 data_offset
= msg
->param_data_size
- sz_remaining
;
826 /* clear the fields */
827 header
.extension
&= IPC_INITIAL_BLOCK_CLEAR
;
828 header
.extension
&= IPC_DATA_OFFSET_SZ_CLEAR
;
829 /* fill the fields */
830 header
.extension
|= IPC_INITIAL_BLOCK(0);
831 header
.extension
|= IPC_DATA_OFFSET_SZ(data_offset
);
836 EXPORT_SYMBOL_GPL(skl_ipc_set_large_config
);