sound/soc/intel/skylake/skl-sst.c

   1 /*
   2  * skl-sst.c - HDA DSP library functions for SKL platform
   3  *
   4  * Copyright (C) 2014-15, Intel Corporation.
   5  * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
   6  *      Jeeja KP <jeeja.kp@intel.com>
   7  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/delay.h>
  21 #include <linux/device.h>
  22 #include "../common/sst-dsp.h"
  23 #include "../common/sst-dsp-priv.h"
  24 #include "../common/sst-ipc.h"
  25 #include "skl-sst-ipc.h"
  26
  27 #define SKL_BASEFW_TIMEOUT      300
  28 #define SKL_INIT_TIMEOUT        1000
  29
  30 /* Intel HD Audio SRAM Window 0*/
  31 #define SKL_ADSP_SRAM0_BASE     0x8000
  32
  33 /* Firmware status window */
  34 #define SKL_ADSP_FW_STATUS      SKL_ADSP_SRAM0_BASE
  35 #define SKL_ADSP_ERROR_CODE     (SKL_ADSP_FW_STATUS + 0x4)
  36
  37 #define SKL_INSTANCE_ID         0
  38 #define SKL_BASE_FW_MODULE_ID   0
  39
  40 static bool skl_check_fw_status(struct sst_dsp *ctx, u32 status)
  41 {
  42         u32 cur_sts;
  43
  44         cur_sts = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS) & SKL_FW_STS_MASK;
  45
  46         return (cur_sts == status);
  47 }
  48
  49 static int skl_transfer_firmware(struct sst_dsp *ctx,
  50                 const void *basefw, u32 base_fw_size)
  51 {
  52         int ret = 0;
  53
  54         ret = ctx->cl_dev.ops.cl_copy_to_dmabuf(ctx, basefw, base_fw_size);
  55         if (ret < 0)
  56                 return ret;
  57
  58         ret = sst_dsp_register_poll(ctx,
  59                         SKL_ADSP_FW_STATUS,
  60                         SKL_FW_STS_MASK,
  61                         SKL_FW_RFW_START,
  62                         SKL_BASEFW_TIMEOUT,
  63                         "Firmware boot");
  64
  65         ctx->cl_dev.ops.cl_stop_dma(ctx);
  66
  67         return ret;
  68 }
  69
  70 static int skl_load_base_firmware(struct sst_dsp *ctx)
  71 {
  72         int ret = 0, i;
  73         struct skl_sst *skl = ctx->thread_context;
  74         u32 reg;
  75
  76         skl->boot_complete = false;
  77         init_waitqueue_head(&skl->boot_wait);
  78
  79         if (ctx->fw == NULL) {
  80                 ret = request_firmware(&ctx->fw, "dsp_fw_release.bin", ctx->dev);
  81                 if (ret < 0) {
  82                         dev_err(ctx->dev, "Request firmware failed %d\n", ret);
  83                         skl_dsp_disable_core(ctx);
  84                         return -EIO;
  85                 }
  86         }
  87
  88         ret = skl_dsp_boot(ctx);
  89         if (ret < 0) {
  90                 dev_err(ctx->dev, "Boot dsp core failed ret: %d", ret);
  91                 goto skl_load_base_firmware_failed;
  92         }
  93
  94         ret = skl_cldma_prepare(ctx);
  95         if (ret < 0) {
  96                 dev_err(ctx->dev, "CL dma prepare failed : %d", ret);
  97                 goto skl_load_base_firmware_failed;
  98         }
  99
 100         /* enable Interrupt */
 101         skl_ipc_int_enable(ctx);
 102         skl_ipc_op_int_enable(ctx);
 103
 104         /* check ROM Status */
 105         for (i = SKL_INIT_TIMEOUT; i > 0; --i) {
 106                 if (skl_check_fw_status(ctx, SKL_FW_INIT)) {
 107                         dev_dbg(ctx->dev,
 108                                 "ROM loaded, we can continue with FW loading\n");
 109                         break;
 110                 }
 111                 mdelay(1);
 112         }
 113         if (!i) {
 114                 reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS);
 115                 dev_err(ctx->dev,
 116                         "Timeout waiting for ROM init done, reg:0x%x\n", reg);
 117                 ret = -EIO;
 118                 goto skl_load_base_firmware_failed;
 119         }
 120
 121         ret = skl_transfer_firmware(ctx, ctx->fw->data, ctx->fw->size);
 122         if (ret < 0) {
 123                 dev_err(ctx->dev, "Transfer firmware failed%d\n", ret);
 124                 goto skl_load_base_firmware_failed;
 125         } else {
 126                 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
 127                                         msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
 128                 if (ret == 0) {
 129                         dev_err(ctx->dev, "DSP boot failed, FW Ready timed-out\n");
 130                         ret = -EIO;
 131                         goto skl_load_base_firmware_failed;
 132                 }
 133
 134                 dev_dbg(ctx->dev, "Download firmware successful%d\n", ret);
 135                 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
 136         }
 137         return 0;
 138
 139 skl_load_base_firmware_failed:
 140         skl_dsp_disable_core(ctx);
 141         release_firmware(ctx->fw);
 142         ctx->fw = NULL;
 143         return ret;
 144 }
 145
 146 static int skl_set_dsp_D0(struct sst_dsp *ctx)
 147 {
 148         int ret;
 149
 150         ret = skl_load_base_firmware(ctx);
 151         if (ret < 0) {
 152                 dev_err(ctx->dev, "unable to load firmware\n");
 153                 return ret;
 154         }
 155
 156         skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
 157
 158         return ret;
 159 }
 160
 161 static int skl_set_dsp_D3(struct sst_dsp *ctx)
 162 {
 163         int ret;
 164         struct skl_ipc_dxstate_info dx;
 165         struct skl_sst *skl = ctx->thread_context;
 166
 167         dev_dbg(ctx->dev, "In %s:\n", __func__);
 168         mutex_lock(&ctx->mutex);
 169         if (!is_skl_dsp_running(ctx)) {
 170                 mutex_unlock(&ctx->mutex);
 171                 return 0;
 172         }
 173         mutex_unlock(&ctx->mutex);
 174
 175         dx.core_mask = SKL_DSP_CORE0_MASK;
 176         dx.dx_mask = SKL_IPC_D3_MASK;
 177         ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID, SKL_BASE_FW_MODULE_ID, &dx);
 178         if (ret < 0) {
 179                 dev_err(ctx->dev, "Failed to set DSP to D3 state\n");
 180                 return ret;
 181         }
 182
 183         ret = skl_dsp_disable_core(ctx);
 184         if (ret < 0) {
 185                 dev_err(ctx->dev, "disable dsp core failed ret: %d\n", ret);
 186                 ret = -EIO;
 187         }
 188         skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);
 189
 190         /* disable Interrupt */
 191         ctx->cl_dev.ops.cl_cleanup_controller(ctx);
 192         skl_cldma_int_disable(ctx);
 193         skl_ipc_op_int_disable(ctx);
 194         skl_ipc_int_disable(ctx);
 195
 196         return ret;
 197 }
 198
 199 static unsigned int skl_get_errorcode(struct sst_dsp *ctx)
 200 {
 201          return sst_dsp_shim_read(ctx, SKL_ADSP_ERROR_CODE);
 202 }
 203
 204 static struct skl_dsp_fw_ops skl_fw_ops = {
 205         .set_state_D0 = skl_set_dsp_D0,
 206         .set_state_D3 = skl_set_dsp_D3,
 207         .load_fw = skl_load_base_firmware,
 208         .get_fw_errcode = skl_get_errorcode,
 209 };
 210
 211 static struct sst_ops skl_ops = {
 212         .irq_handler = skl_dsp_sst_interrupt,
 213         .write = sst_shim32_write,
 214         .read = sst_shim32_read,
 215         .ram_read = sst_memcpy_fromio_32,
 216         .ram_write = sst_memcpy_toio_32,
 217         .free = skl_dsp_free,
 218 };
 219
 220 static struct sst_dsp_device skl_dev = {
 221         .thread = skl_dsp_irq_thread_handler,
 222         .ops = &skl_ops,
 223 };
 224
 225 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 226                 struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp)
 227 {
 228         struct skl_sst *skl;
 229         struct sst_dsp *sst;
 230         int ret;
 231
 232         skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
 233         if (skl == NULL)
 234                 return -ENOMEM;
 235
 236         skl->dev = dev;
 237         skl_dev.thread_context = skl;
 238
 239         skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
 240         if (!skl->dsp) {
 241                 dev_err(skl->dev, "%s: no device\n", __func__);
 242                 return -ENODEV;
 243         }
 244
 245         sst = skl->dsp;
 246
 247         sst->addr.lpe = mmio_base;
 248         sst->addr.shim = mmio_base;
 249         sst_dsp_mailbox_init(sst, (SKL_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
 250                         SKL_ADSP_W0_UP_SZ, SKL_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
 251
 252         sst->dsp_ops = dsp_ops;
 253         sst->fw_ops = skl_fw_ops;
 254
 255         ret = skl_ipc_init(dev, skl);
 256         if (ret)
 257                 return ret;
 258
 259         ret = sst->fw_ops.load_fw(sst);
 260         if (ret < 0) {
 261                 dev_err(dev, "Load base fw failed : %d", ret);
 262                 return ret;
 263         }
 264
 265         if (dsp)
 266                 *dsp = skl;
 267
 268         return 0;
 269
 270         skl_ipc_free(&skl->ipc);
 271         return ret;
 272 }
 273 EXPORT_SYMBOL_GPL(skl_sst_dsp_init);
 274
 275 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
 276 {
 277         skl_ipc_free(&ctx->ipc);
 278         ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
 279         ctx->dsp->ops->free(ctx->dsp);
 280 }
 281 EXPORT_SYMBOL_GPL(skl_sst_dsp_cleanup);
 282
 283 MODULE_LICENSE("GPL v2");
 284 MODULE_DESCRIPTION("Intel Skylake IPC driver");