sound/soc/intel/skylake/skl-topology.h

   1 /*
   2  *  skl_topology.h - Intel HDA Platform topology header file
   3  *
   4  *  Copyright (C) 2014-15 Intel Corp
   5  *  Author: Jeeja KP <jeeja.kp@intel.com>
   6  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; version 2 of the License.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but
  13  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  *  General Public License for more details.
  16  *
  17  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  18  *
  19  */
  20
  21 #ifndef __SKL_TOPOLOGY_H__
  22 #define __SKL_TOPOLOGY_H__
  23
  24 #include <linux/types.h>
  25
  26 #include <sound/hdaudio_ext.h>
  27 #include <sound/soc.h>
  28 #include "skl.h"
  29 #include "skl-tplg-interface.h"
  30
  31 #define BITS_PER_BYTE 8
  32 #define MAX_TS_GROUPS 8
  33 #define MAX_DMIC_TS_GROUPS 4
  34 #define MAX_FIXED_DMIC_PARAMS_SIZE 727
  35
  36 /* Maximum number of coefficients up down mixer module */
  37 #define UP_DOWN_MIXER_MAX_COEFF         6
  38
  39 enum skl_channel_index {
  40         SKL_CHANNEL_LEFT = 0,
  41         SKL_CHANNEL_RIGHT = 1,
  42         SKL_CHANNEL_CENTER = 2,
  43         SKL_CHANNEL_LEFT_SURROUND = 3,
  44         SKL_CHANNEL_CENTER_SURROUND = 3,
  45         SKL_CHANNEL_RIGHT_SURROUND = 4,
  46         SKL_CHANNEL_LFE = 7,
  47         SKL_CHANNEL_INVALID = 0xF,
  48 };
  49
  50 enum skl_bitdepth {
  51         SKL_DEPTH_8BIT = 8,
  52         SKL_DEPTH_16BIT = 16,
  53         SKL_DEPTH_24BIT = 24,
  54         SKL_DEPTH_32BIT = 32,
  55         SKL_DEPTH_INVALID
  56 };
  57
  58 enum skl_interleaving {
  59         /* [s1_ch1...s1_chN,...,sM_ch1...sM_chN] */
  60         SKL_INTERLEAVING_PER_CHANNEL = 0,
  61         /* [s1_ch1...sM_ch1,...,s1_chN...sM_chN] */
  62         SKL_INTERLEAVING_PER_SAMPLE = 1,
  63 };
  64
  65 enum skl_s_freq {
  66         SKL_FS_8000 = 8000,
  67         SKL_FS_11025 = 11025,
  68         SKL_FS_12000 = 12000,
  69         SKL_FS_16000 = 16000,
  70         SKL_FS_22050 = 22050,
  71         SKL_FS_24000 = 24000,
  72         SKL_FS_32000 = 32000,
  73         SKL_FS_44100 = 44100,
  74         SKL_FS_48000 = 48000,
  75         SKL_FS_64000 = 64000,
  76         SKL_FS_88200 = 88200,
  77         SKL_FS_96000 = 96000,
  78         SKL_FS_128000 = 128000,
  79         SKL_FS_176400 = 176400,
  80         SKL_FS_192000 = 192000,
  81         SKL_FS_INVALID
  82 };
  83
  84 enum skl_widget_type {
  85         SKL_WIDGET_VMIXER = 1,
  86         SKL_WIDGET_MIXER = 2,
  87         SKL_WIDGET_PGA = 3,
  88         SKL_WIDGET_MUX = 4
  89 };
  90
  91 struct skl_audio_data_format {
  92         enum skl_s_freq s_freq;
  93         enum skl_bitdepth bit_depth;
  94         u32 channel_map;
  95         enum skl_ch_cfg ch_cfg;
  96         enum skl_interleaving interleaving;
  97         u8 number_of_channels;
  98         u8 valid_bit_depth;
  99         u8 sample_type;
 100         u8 reserved[1];
 101 } __packed;
 102
 103 struct skl_base_cfg {
 104         u32 cps;
 105         u32 ibs;
 106         u32 obs;
 107         u32 is_pages;
 108         struct skl_audio_data_format audio_fmt;
 109 };
 110
 111 struct skl_cpr_gtw_cfg {
 112         u32 node_id;
 113         u32 dma_buffer_size;
 114         u32 config_length;
 115         /* not mandatory; required only for DMIC/I2S */
 116         u32 config_data[1];
 117 } __packed;
 118
 119 struct skl_cpr_cfg {
 120         struct skl_base_cfg base_cfg;
 121         struct skl_audio_data_format out_fmt;
 122         u32 cpr_feature_mask;
 123         struct skl_cpr_gtw_cfg gtw_cfg;
 124 } __packed;
 125
 126
 127 struct skl_src_module_cfg {
 128         struct skl_base_cfg base_cfg;
 129         enum skl_s_freq src_cfg;
 130 } __packed;
 131
 132 struct notification_mask {
 133         u32 notify;
 134         u32 enable;
 135 } __packed;
 136
 137 struct skl_up_down_mixer_cfg {
 138         struct skl_base_cfg base_cfg;
 139         enum skl_ch_cfg out_ch_cfg;
 140         /* This should be set to 1 if user coefficients are required */
 141         u32 coeff_sel;
 142         /* Pass the user coeff in this array */
 143         s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
 144 } __packed;
 145
 146 enum skl_dma_type {
 147         SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
 148         SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
 149         SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
 150         SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
 151         SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
 152         SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
 153         SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
 154         SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
 155         SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
 156 };
 157
 158 union skl_ssp_dma_node {
 159         u8 val;
 160         struct {
 161                 u8 time_slot_index:4;
 162                 u8 i2s_instance:4;
 163         } dma_node;
 164 };
 165
 166 union skl_connector_node_id {
 167         u32 val;
 168         struct {
 169                 u32 vindex:8;
 170                 u32 dma_type:4;
 171                 u32 rsvd:20;
 172         } node;
 173 };
 174
 175 struct skl_module_fmt {
 176         u32 channels;
 177         u32 s_freq;
 178         u32 bit_depth;
 179         u32 valid_bit_depth;
 180         u32 ch_cfg;
 181 };
 182
 183 struct skl_module_cfg;
 184
 185 struct skl_module_inst_id {
 186         u32 module_id;
 187         u32 instance_id;
 188 };
 189
 190 enum skl_module_pin_state {
 191         SKL_PIN_UNBIND = 0,
 192         SKL_PIN_BIND_DONE = 1,
 193 };
 194
 195 struct skl_module_pin {
 196         struct skl_module_inst_id id;
 197         bool is_dynamic;
 198         bool in_use;
 199         enum skl_module_pin_state pin_state;
 200         struct skl_module_cfg *tgt_mcfg;
 201 };
 202
 203 struct skl_specific_cfg {
 204         u32 caps_size;
 205         u32 *caps;
 206 };
 207
 208 enum skl_pipe_state {
 209         SKL_PIPE_INVALID = 0,
 210         SKL_PIPE_CREATED = 1,
 211         SKL_PIPE_PAUSED = 2,
 212         SKL_PIPE_STARTED = 3
 213 };
 214
 215 struct skl_pipe_module {
 216         struct snd_soc_dapm_widget *w;
 217         struct list_head node;
 218 };
 219
 220 struct skl_pipe_params {
 221         u8 host_dma_id;
 222         u8 link_dma_id;
 223         u32 ch;
 224         u32 s_freq;
 225         u32 s_fmt;
 226         u8 linktype;
 227         int stream;
 228 };
 229
 230 struct skl_pipe {
 231         u8 ppl_id;
 232         u8 pipe_priority;
 233         u16 conn_type;
 234         u32 memory_pages;
 235         struct skl_pipe_params *p_params;
 236         enum skl_pipe_state state;
 237         struct list_head w_list;
 238 };
 239
 240 enum skl_module_state {
 241         SKL_MODULE_UNINIT = 0,
 242         SKL_MODULE_INIT_DONE = 1,
 243         SKL_MODULE_LOADED = 2,
 244         SKL_MODULE_UNLOADED = 3,
 245         SKL_MODULE_BIND_DONE = 4
 246 };
 247
 248 struct skl_module_cfg {
 249         struct skl_module_inst_id id;
 250         struct skl_module_fmt in_fmt;
 251         struct skl_module_fmt out_fmt;
 252         u8 max_in_queue;
 253         u8 max_out_queue;
 254         u8 in_queue_mask;
 255         u8 out_queue_mask;
 256         u8 in_queue;
 257         u8 out_queue;
 258         u32 mcps;
 259         u32 ibs;
 260         u32 obs;
 261         u8 is_loadable;
 262         u8 core_id;
 263         u8 dev_type;
 264         u8 dma_id;
 265         u8 time_slot;
 266         u32 params_fixup;
 267         u32 converter;
 268         u32 vbus_id;
 269         struct skl_module_pin *m_in_pin;
 270         struct skl_module_pin *m_out_pin;
 271         enum skl_module_type m_type;
 272         enum skl_hw_conn_type  hw_conn_type;
 273         enum skl_module_state m_state;
 274         struct skl_pipe *pipe;
 275         struct skl_specific_cfg formats_config;
 276 };
 277
 278 struct skl_pipeline {
 279         struct skl_pipe *pipe;
 280         struct list_head node;
 281 };
 282
 283 struct skl_dapm_path_list {
 284         struct snd_soc_dapm_path *dapm_path;
 285         struct list_head node;
 286 };
 287
 288 static inline struct skl *get_skl_ctx(struct device *dev)
 289 {
 290         struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
 291
 292         return ebus_to_skl(ebus);
 293 }
 294
 295 int skl_tplg_be_update_params(struct snd_soc_dai *dai,
 296         struct skl_pipe_params *params);
 297 void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
 298         struct skl_pipe_params *params, int stream);
 299 int skl_tplg_init(struct snd_soc_platform *platform,
 300                                 struct hdac_ext_bus *ebus);
 301 struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
 302                 struct snd_soc_dai *dai, int stream);
 303 int skl_tplg_update_pipe_params(struct device *dev,
 304                 struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
 305
 306 int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);
 307
 308 int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 309
 310 int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 311
 312 int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 313
 314 int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
 315
 316 int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config,
 317         char *param);
 318
 319 int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
 320         *src_module, struct skl_module_cfg *dst_module);
 321
 322 int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
 323         *src_module, struct skl_module_cfg *dst_module);
 324
 325 enum skl_bitdepth skl_get_bit_depth(int params);
 326 #endif