sound/soc/intel/skylake/skl-tplg-interface.h

   1 /*
   2  * skl-tplg-interface.h - Intel DSP FW private data interface
   3  *
   4  * Copyright (C) 2015 Intel Corp
   5  * Author: Jeeja KP <jeeja.kp@intel.com>
   6  *          Nilofer, Samreen <samreen.nilofer@intel.com>
   7  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  */
  18
  19 #ifndef __HDA_TPLG_INTERFACE_H__
  20 #define __HDA_TPLG_INTERFACE_H__
  21
  22 /**
  23  * enum skl_ch_cfg - channel configuration
  24  *
  25  * @SKL_CH_CFG_MONO:    One channel only
  26  * @SKL_CH_CFG_STEREO:  L & R
  27  * @SKL_CH_CFG_2_1:     L, R & LFE
  28  * @SKL_CH_CFG_3_0:     L, C & R
  29  * @SKL_CH_CFG_3_1:     L, C, R & LFE
  30  * @SKL_CH_CFG_QUATRO:  L, R, Ls & Rs
  31  * @SKL_CH_CFG_4_0:     L, C, R & Cs
  32  * @SKL_CH_CFG_5_0:     L, C, R, Ls & Rs
  33  * @SKL_CH_CFG_5_1:     L, C, R, Ls, Rs & LFE
  34  * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
  35  * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
  36  * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
  37  * @SKL_CH_CFG_INVALID: Invalid
  38  */
  39 enum skl_ch_cfg {
  40         SKL_CH_CFG_MONO = 0,
  41         SKL_CH_CFG_STEREO = 1,
  42         SKL_CH_CFG_2_1 = 2,
  43         SKL_CH_CFG_3_0 = 3,
  44         SKL_CH_CFG_3_1 = 4,
  45         SKL_CH_CFG_QUATRO = 5,
  46         SKL_CH_CFG_4_0 = 6,
  47         SKL_CH_CFG_5_0 = 7,
  48         SKL_CH_CFG_5_1 = 8,
  49         SKL_CH_CFG_DUAL_MONO = 9,
  50         SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
  51         SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
  52         SKL_CH_CFG_INVALID
  53 };
  54
  55 enum skl_module_type {
  56         SKL_MODULE_TYPE_MIXER = 0,
  57         SKL_MODULE_TYPE_COPIER,
  58         SKL_MODULE_TYPE_UPDWMIX,
  59         SKL_MODULE_TYPE_SRCINT
  60 };
  61
  62 enum skl_core_affinity {
  63         SKL_AFFINITY_CORE_0 = 0,
  64         SKL_AFFINITY_CORE_1,
  65         SKL_AFFINITY_CORE_MAX
  66 };
  67
  68 enum skl_pipe_conn_type {
  69         SKL_PIPE_CONN_TYPE_NONE = 0,
  70         SKL_PIPE_CONN_TYPE_FE,
  71         SKL_PIPE_CONN_TYPE_BE
  72 };
  73
  74 enum skl_hw_conn_type {
  75         SKL_CONN_NONE = 0,
  76         SKL_CONN_SOURCE = 1,
  77         SKL_CONN_SINK = 2
  78 };
  79
  80 enum skl_dev_type {
  81         SKL_DEVICE_BT = 0x0,
  82         SKL_DEVICE_DMIC = 0x1,
  83         SKL_DEVICE_I2S = 0x2,
  84         SKL_DEVICE_SLIMBUS = 0x3,
  85         SKL_DEVICE_HDALINK = 0x4,
  86         SKL_DEVICE_NONE
  87 };
  88 #endif