sound/soc/intel/sst-dsp.h

   1 /*
   2  * Intel Smart Sound Technology (SST) Core
   3  *
   4  * Copyright (C) 2013, Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #ifndef __SOUND_SOC_SST_DSP_H
  18 #define __SOUND_SOC_SST_DSP_H
  19
  20 #include <linux/kernel.h>
  21 #include <linux/types.h>
  22 #include <linux/interrupt.h>
  23
  24 /* SST Device IDs  */
  25 #define SST_DEV_ID_LYNX_POINT           0x33C8
  26 #define SST_DEV_ID_WILDCAT_POINT        0x3438
  27 #define SST_DEV_ID_BYT                  0x0F28
  28
  29 /* Supported SST DMA Devices */
  30 #define SST_DMA_TYPE_DW         1
  31 #define SST_DMA_TYPE_MID        2
  32
  33 /* SST Shim register map
  34  * The register naming can differ between products. Some products also
  35  * contain extra functionality.
  36  */
  37 #define SST_CSR                 0x00
  38 #define SST_PISR                0x08
  39 #define SST_PIMR                0x10
  40 #define SST_ISRX                0x18
  41 #define SST_ISRD                0x20
  42 #define SST_IMRX                0x28
  43 #define SST_IMRD                0x30
  44 #define SST_IPCX                0x38 /* IPC IA -> SST */
  45 #define SST_IPCD                0x40 /* IPC SST -> IA */
  46 #define SST_ISRSC               0x48
  47 #define SST_ISRLPESC            0x50
  48 #define SST_IMRSC               0x58
  49 #define SST_IMRLPESC            0x60
  50 #define SST_IPCSC               0x68
  51 #define SST_IPCLPESC            0x70
  52 #define SST_CLKCTL              0x78
  53 #define SST_CSR2                0x80
  54 #define SST_LTRC                0xE0
  55 #define SST_HMDC                0xE8
  56
  57 #define SST_SHIM_BEGIN          SST_CSR
  58 #define SST_SHIM_END            SST_HDMC
  59
  60 #define SST_DBGO                0xF0
  61
  62 #define SST_SHIM_SIZE           0x100
  63 #define SST_PWMCTRL             0x1000
  64
  65 /* SST Shim Register bits
  66  * The register bit naming can differ between products. Some products also
  67  * contain extra functionality.
  68  */
  69
  70 /* CSR / CS */
  71 #define SST_CSR_RST             (0x1 << 1)
  72 #define SST_CSR_SBCS0           (0x1 << 2)
  73 #define SST_CSR_SBCS1           (0x1 << 3)
  74 #define SST_CSR_DCS(x)          (x << 4)
  75 #define SST_CSR_DCS_MASK        (0x7 << 4)
  76 #define SST_CSR_STALL           (0x1 << 10)
  77 #define SST_CSR_S0IOCS          (0x1 << 21)
  78 #define SST_CSR_S1IOCS          (0x1 << 23)
  79 #define SST_CSR_LPCS            (0x1 << 31)
  80 #define SST_CSR_24MHZ_LPCS      (SST_CSR_SBCS0 | SST_CSR_SBCS1 | SST_CSR_LPCS)
  81 #define SST_CSR_24MHZ_NO_LPCS   (SST_CSR_SBCS0 | SST_CSR_SBCS1)
  82 #define SST_BYT_CSR_RST         (0x1 << 0)
  83 #define SST_BYT_CSR_VECTOR_SEL  (0x1 << 1)
  84 #define SST_BYT_CSR_STALL       (0x1 << 2)
  85 #define SST_BYT_CSR_PWAITMODE   (0x1 << 3)
  86
  87 /*  ISRX / ISC */
  88 #define SST_ISRX_BUSY           (0x1 << 1)
  89 #define SST_ISRX_DONE           (0x1 << 0)
  90 #define SST_BYT_ISRX_REQUEST    (0x1 << 1)
  91
  92 /*  ISRD / ISD */
  93 #define SST_ISRD_BUSY           (0x1 << 1)
  94 #define SST_ISRD_DONE           (0x1 << 0)
  95
  96 /* IMRX / IMC */
  97 #define SST_IMRX_BUSY           (0x1 << 1)
  98 #define SST_IMRX_DONE           (0x1 << 0)
  99 #define SST_BYT_IMRX_REQUEST    (0x1 << 1)
 100
 101 /* IMRD / IMD */
 102 #define SST_IMRD_DONE           (0x1 << 0)
 103 #define SST_IMRD_BUSY           (0x1 << 1)
 104 #define SST_IMRD_SSP0           (0x1 << 16)
 105 #define SST_IMRD_DMAC0          (0x1 << 21)
 106 #define SST_IMRD_DMAC1          (0x1 << 22)
 107 #define SST_IMRD_DMAC           (SST_IMRD_DMAC0 | SST_IMRD_DMAC1)
 108
 109 /*  IPCX / IPCC */
 110 #define SST_IPCX_DONE           (0x1 << 30)
 111 #define SST_IPCX_BUSY           (0x1 << 31)
 112 #define SST_BYT_IPCX_DONE       ((u64)0x1 << 62)
 113 #define SST_BYT_IPCX_BUSY       ((u64)0x1 << 63)
 114
 115 /*  IPCD */
 116 #define SST_IPCD_DONE           (0x1 << 30)
 117 #define SST_IPCD_BUSY           (0x1 << 31)
 118 #define SST_BYT_IPCD_DONE       ((u64)0x1 << 62)
 119 #define SST_BYT_IPCD_BUSY       ((u64)0x1 << 63)
 120
 121 /* CLKCTL */
 122 #define SST_CLKCTL_SMOS(x)      (x << 24)
 123 #define SST_CLKCTL_MASK         (3 << 24)
 124 #define SST_CLKCTL_DCPLCG       (1 << 18)
 125 #define SST_CLKCTL_SCOE1        (1 << 17)
 126 #define SST_CLKCTL_SCOE0        (1 << 16)
 127
 128 /* CSR2 / CS2 */
 129 #define SST_CSR2_SDFD_SSP0      (1 << 1)
 130 #define SST_CSR2_SDFD_SSP1      (1 << 2)
 131
 132 /* LTRC */
 133 #define SST_LTRC_VAL(x)         (x << 0)
 134
 135 /* HMDC */
 136 #define SST_HMDC_HDDA0(x)       (x << 0)
 137 #define SST_HMDC_HDDA1(x)       (x << 7)
 138 #define SST_HMDC_HDDA_E0_CH0    1
 139 #define SST_HMDC_HDDA_E0_CH1    2
 140 #define SST_HMDC_HDDA_E0_CH2    4
 141 #define SST_HMDC_HDDA_E0_CH3    8
 142 #define SST_HMDC_HDDA_E1_CH0    SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH0)
 143 #define SST_HMDC_HDDA_E1_CH1    SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH1)
 144 #define SST_HMDC_HDDA_E1_CH2    SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH2)
 145 #define SST_HMDC_HDDA_E1_CH3    SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH3)
 146 #define SST_HMDC_HDDA_E0_ALLCH  (SST_HMDC_HDDA_E0_CH0 | SST_HMDC_HDDA_E0_CH1 | \
 147                                  SST_HMDC_HDDA_E0_CH2 | SST_HMDC_HDDA_E0_CH3)
 148 #define SST_HMDC_HDDA_E1_ALLCH  (SST_HMDC_HDDA_E1_CH0 | SST_HMDC_HDDA_E1_CH1 | \
 149                                  SST_HMDC_HDDA_E1_CH2 | SST_HMDC_HDDA_E1_CH3)
 150
 151
 152 /* SST Vendor Defined Registers and bits */
 153 #define SST_VDRTCTL0            0xa0
 154 #define SST_VDRTCTL1            0xa4
 155 #define SST_VDRTCTL2            0xa8
 156 #define SST_VDRTCTL3            0xaC
 157
 158 /* VDRTCTL0 */
 159 #define SST_VDRTCL0_APLLSE_MASK         1
 160 #define SST_VDRTCL0_DSRAMPGE_SHIFT      16
 161 #define SST_VDRTCL0_DSRAMPGE_MASK       (0xffff << SST_VDRTCL0_DSRAMPGE_SHIFT)
 162 #define SST_VDRTCL0_ISRAMPGE_SHIFT      6
 163 #define SST_VDRTCL0_ISRAMPGE_MASK       (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT)
 164
 165 /* PMCS */
 166 #define SST_PMCS                0x84
 167 #define SST_PMCS_PS_MASK        0x3
 168
 169 struct sst_dsp;
 170
 171 /*
 172  * SST Device.
 173  *
 174  * This structure is populated by the SST core driver.
 175  */
 176 struct sst_dsp_device {
 177         /* Mandatory fields */
 178         struct sst_ops *ops;
 179         irqreturn_t (*thread)(int irq, void *context);
 180         void *thread_context;
 181 };
 182
 183 /*
 184  * SST Platform Data.
 185  */
 186 struct sst_pdata {
 187         /* ACPI data */
 188         u32 lpe_base;
 189         u32 lpe_size;
 190         u32 pcicfg_base;
 191         u32 pcicfg_size;
 192         u32 fw_base;
 193         u32 fw_size;
 194         int irq;
 195
 196         /* Firmware */
 197         const struct firmware *fw;
 198
 199         /* DMA */
 200         u32 dma_base;
 201         u32 dma_size;
 202         int dma_engine;
 203         struct device *dma_dev;
 204
 205         /* DSP */
 206         u32 id;
 207         void *dsp;
 208 };
 209
 210 /* Initialization */
 211 struct sst_dsp *sst_dsp_new(struct device *dev,
 212         struct sst_dsp_device *sst_dev, struct sst_pdata *pdata);
 213 void sst_dsp_free(struct sst_dsp *sst);
 214
 215 /* SHIM Read / Write */
 216 void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
 217 u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
 218 int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
 219                                 u32 mask, u32 value);
 220 void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value);
 221 u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset);
 222 int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
 223                                 u64 mask, u64 value);
 224
 225 /* SHIM Read / Write Unlocked for callers already holding sst lock */
 226 void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
 227 u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
 228 int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
 229                                 u32 mask, u32 value);
 230 void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value);
 231 u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset);
 232 int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
 233                                         u64 mask, u64 value);
 234
 235 /* Internal generic low-level SST IO functions - can be overidden */
 236 void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
 237 u32 sst_shim32_read(void __iomem *addr, u32 offset);
 238 void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
 239 u64 sst_shim32_read64(void __iomem *addr, u32 offset);
 240 void sst_memcpy_toio_32(struct sst_dsp *sst,
 241                         void __iomem *dest, void *src, size_t bytes);
 242 void sst_memcpy_fromio_32(struct sst_dsp *sst,
 243                           void *dest, void __iomem *src, size_t bytes);
 244
 245 /* DSP reset & boot */
 246 void sst_dsp_reset(struct sst_dsp *sst);
 247 int sst_dsp_boot(struct sst_dsp *sst);
 248
 249 /* Msg IO */
 250 void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg);
 251 u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp);
 252
 253 /* Mailbox management */
 254 int sst_dsp_mailbox_init(struct sst_dsp *dsp, u32 inbox_offset,
 255         size_t inbox_size, u32 outbox_offset, size_t outbox_size);
 256 void sst_dsp_inbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
 257 void sst_dsp_inbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
 258 void sst_dsp_outbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
 259 void sst_dsp_outbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
 260 void sst_dsp_mailbox_dump(struct sst_dsp *dsp, size_t bytes);
 261
 262 /* Debug */
 263 void sst_dsp_dump(struct sst_dsp *sst);
 264
 265 #endif