sound/soc/intel/sst-haswell-dsp.c

   1 /*
   2  * Intel Haswell SST DSP driver
   3  *
   4  * Copyright (C) 2013, Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/fs.h>
  19 #include <linux/slab.h>
  20 #include <linux/device.h>
  21 #include <linux/sched.h>
  22 #include <linux/export.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pci.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include "sst-dsp.h"
  32 #include "sst-dsp-priv.h"
  33 #include "sst-haswell-ipc.h"
  34
  35 #include <trace/events/hswadsp.h>
  36
  37 #define SST_HSW_FW_SIGNATURE_SIZE       4
  38 #define SST_HSW_FW_SIGN                 "$SST"
  39 #define SST_HSW_FW_LIB_SIGN             "$LIB"
  40
  41 #define SST_WPT_SHIM_OFFSET     0xFB000
  42 #define SST_LP_SHIM_OFFSET      0xE7000
  43 #define SST_WPT_IRAM_OFFSET     0xA0000
  44 #define SST_LP_IRAM_OFFSET      0x80000
  45 #define SST_WPT_DSP_DRAM_OFFSET 0x400000
  46 #define SST_WPT_DSP_IRAM_OFFSET 0x00000
  47 #define SST_LPT_DSP_DRAM_OFFSET 0x400000
  48 #define SST_LPT_DSP_IRAM_OFFSET 0x00000
  49
  50 #define SST_SHIM_PM_REG         0x84
  51
  52 #define SST_HSW_IRAM    1
  53 #define SST_HSW_DRAM    2
  54 #define SST_HSW_REGS    3
  55
  56 struct dma_block_info {
  57         __le32 type;            /* IRAM/DRAM */
  58         __le32 size;            /* Bytes */
  59         __le32 ram_offset;      /* Offset in I/DRAM */
  60         __le32 rsvd;            /* Reserved field */
  61 } __attribute__((packed));
  62
  63 struct fw_module_info {
  64         __le32 persistent_size;
  65         __le32 scratch_size;
  66 } __attribute__((packed));
  67
  68 struct fw_header {
  69         unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
  70         __le32 file_size;               /* size of fw minus this header */
  71         __le32 modules;         /*  # of modules */
  72         __le32 file_format;     /* version of header format */
  73         __le32 reserved[4];
  74 } __attribute__((packed));
  75
  76 struct fw_module_header {
  77         unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
  78         __le32 mod_size;        /* size of module */
  79         __le32 blocks;  /* # of blocks */
  80         __le16 padding;
  81         __le16 type;    /* codec type, pp lib */
  82         __le32 entry_point;
  83         struct fw_module_info info;
  84 } __attribute__((packed));
  85
  86 static void hsw_free(struct sst_dsp *sst);
  87
  88 static int hsw_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
  89         struct fw_module_header *module)
  90 {
  91         struct dma_block_info *block;
  92         struct sst_module *mod;
  93         struct sst_module_template template;
  94         int count, ret;
  95         void __iomem *ram;
  96
  97         /* TODO: allowed module types need to be configurable */
  98         if (module->type != SST_HSW_MODULE_BASE_FW
  99                 && module->type != SST_HSW_MODULE_PCM_SYSTEM
 100                 && module->type != SST_HSW_MODULE_PCM
 101                 && module->type != SST_HSW_MODULE_PCM_REFERENCE
 102                 && module->type != SST_HSW_MODULE_PCM_CAPTURE
 103                 && module->type != SST_HSW_MODULE_LPAL)
 104                 return 0;
 105
 106         dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
 107                 module->signature, module->mod_size,
 108                 module->blocks, module->type);
 109         dev_dbg(dsp->dev, " entrypoint 0x%x\n", module->entry_point);
 110         dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
 111                 module->info.persistent_size, module->info.scratch_size);
 112
 113         memset(&template, 0, sizeof(template));
 114         template.id = module->type;
 115         template.entry = module->entry_point - 4;
 116         template.persistent_size = module->info.persistent_size;
 117         template.scratch_size = module->info.scratch_size;
 118
 119         mod = sst_module_new(fw, &template, NULL);
 120         if (mod == NULL)
 121                 return -ENOMEM;
 122
 123         block = (void *)module + sizeof(*module);
 124
 125         for (count = 0; count < module->blocks; count++) {
 126
 127                 if (block->size <= 0) {
 128                         dev_err(dsp->dev,
 129                                 "error: block %d size invalid\n", count);
 130                         sst_module_free(mod);
 131                         return -EINVAL;
 132                 }
 133
 134                 switch (block->type) {
 135                 case SST_HSW_IRAM:
 136                         ram = dsp->addr.lpe;
 137                         mod->offset =
 138                                 block->ram_offset + dsp->addr.iram_offset;
 139                         mod->type = SST_MEM_IRAM;
 140                         break;
 141                 case SST_HSW_DRAM:
 142                         ram = dsp->addr.lpe;
 143                         mod->offset = block->ram_offset;
 144                         mod->type = SST_MEM_DRAM;
 145                         break;
 146                 default:
 147                         dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
 148                                 block->type, count);
 149                         sst_module_free(mod);
 150                         return -EINVAL;
 151                 }
 152
 153                 mod->size = block->size;
 154                 mod->data = (void *)block + sizeof(*block);
 155                 mod->data_offset = mod->data - fw->dma_buf;
 156
 157                 dev_dbg(dsp->dev, "module block %d type 0x%x "
 158                         "size 0x%x ==> ram %p offset 0x%x\n",
 159                         count, mod->type, block->size, ram,
 160                         block->ram_offset);
 161
 162                 ret = sst_module_alloc_blocks(mod);
 163                 if (ret < 0) {
 164                         dev_err(dsp->dev, "error: could not allocate blocks for module %d\n",
 165                                 count);
 166                         sst_module_free(mod);
 167                         return ret;
 168                 }
 169
 170                 block = (void *)block + sizeof(*block) + block->size;
 171         }
 172         mod->state = SST_MODULE_STATE_LOADED;
 173
 174         return 0;
 175 }
 176
 177 static int hsw_parse_fw_image(struct sst_fw *sst_fw)
 178 {
 179         struct fw_header *header;
 180         struct fw_module_header *module;
 181         struct sst_dsp *dsp = sst_fw->dsp;
 182         int ret, count;
 183
 184         /* Read the header information from the data pointer */
 185         header = (struct fw_header *)sst_fw->dma_buf;
 186
 187         /* verify FW */
 188         if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) ||
 189                 (sst_fw->size != header->file_size + sizeof(*header))) {
 190                 dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
 191                 return -EINVAL;
 192         }
 193
 194         dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
 195                 header->file_size, header->modules,
 196                 header->file_format, sizeof(*header));
 197
 198         /* parse each module */
 199         module = (void *)sst_fw->dma_buf + sizeof(*header);
 200         for (count = 0; count < header->modules; count++) {
 201
 202                 /* module */
 203                 ret = hsw_parse_module(dsp, sst_fw, module);
 204                 if (ret < 0) {
 205                         dev_err(dsp->dev, "error: invalid module %d\n", count);
 206                         return ret;
 207                 }
 208                 module = (void *)module + sizeof(*module) + module->mod_size;
 209         }
 210
 211         return 0;
 212 }
 213
 214 static irqreturn_t hsw_irq(int irq, void *context)
 215 {
 216         struct sst_dsp *sst = (struct sst_dsp *) context;
 217         u32 isr;
 218         int ret = IRQ_NONE;
 219
 220         spin_lock(&sst->spinlock);
 221
 222         /* Interrupt arrived, check src */
 223         isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
 224         if (isr & SST_ISRX_DONE) {
 225                 trace_sst_irq_done(isr,
 226                         sst_dsp_shim_read_unlocked(sst, SST_IMRX));
 227
 228                 /* Mask Done interrupt before return */
 229                 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 230                         SST_IMRX_DONE, SST_IMRX_DONE);
 231                 ret = IRQ_WAKE_THREAD;
 232         }
 233
 234         if (isr & SST_ISRX_BUSY) {
 235                 trace_sst_irq_busy(isr,
 236                         sst_dsp_shim_read_unlocked(sst, SST_IMRX));
 237
 238                 /* Mask Busy interrupt before return */
 239                 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 240                         SST_IMRX_BUSY, SST_IMRX_BUSY);
 241                 ret = IRQ_WAKE_THREAD;
 242         }
 243
 244         spin_unlock(&sst->spinlock);
 245         return ret;
 246 }
 247
 248 static void hsw_set_dsp_D3(struct sst_dsp *sst)
 249 {
 250         u32 val;
 251         u32 reg;
 252
 253         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 254         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 255         reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
 256         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 257
 258         /* enable power gating and switch off DRAM & IRAM blocks */
 259         val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 260         val |= SST_VDRTCL0_DSRAMPGE_MASK |
 261                 SST_VDRTCL0_ISRAMPGE_MASK;
 262         val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD);
 263         writel(val, sst->addr.pci_cfg + SST_VDRTCTL0);
 264
 265         /* switch off audio PLL */
 266         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 267         val |= SST_VDRTCL2_APLLSE_MASK;
 268         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 269
 270         /* disable MCLK(clkctl.smos = 0) */
 271         sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
 272                 SST_CLKCTL_MASK, 0);
 273
 274         /* Set D3 state, delay 50 us */
 275         val = readl(sst->addr.pci_cfg + SST_PMCS);
 276         val |= SST_PMCS_PS_MASK;
 277         writel(val, sst->addr.pci_cfg + SST_PMCS);
 278         udelay(50);
 279
 280         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 281         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 282         reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
 283         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 284
 285         udelay(50);
 286
 287 }
 288
 289 static void hsw_reset(struct sst_dsp *sst)
 290 {
 291         /* put DSP into reset and stall */
 292         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
 293                 SST_CSR_RST | SST_CSR_STALL,
 294                 SST_CSR_RST | SST_CSR_STALL);
 295
 296         /* keep in reset for 10ms */
 297         mdelay(10);
 298
 299         /* take DSP out of reset and keep stalled for FW loading */
 300         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
 301                 SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
 302 }
 303
 304 static int hsw_set_dsp_D0(struct sst_dsp *sst)
 305 {
 306         int tries = 10;
 307         u32 reg, fw_dump_bit;
 308
 309         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 310         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 311         reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
 312         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 313
 314         /* Disable D3PG (VDRTCTL0.D3PGD = 1) */
 315         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 316         reg |= SST_VDRTCL0_D3PGD;
 317         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
 318
 319         /* Set D0 state */
 320         reg = readl(sst->addr.pci_cfg + SST_PMCS);
 321         reg &= ~SST_PMCS_PS_MASK;
 322         writel(reg, sst->addr.pci_cfg + SST_PMCS);
 323
 324         /* check that ADSP shim is enabled */
 325         while (tries--) {
 326                 reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK;
 327                 if (reg == 0)
 328                         goto finish;
 329
 330                 msleep(1);
 331         }
 332
 333         return -ENODEV;
 334
 335 finish:
 336         /* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
 337         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
 338                 SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);
 339
 340         /* stall DSP core, set clk to 192/96Mhz */
 341         sst_dsp_shim_update_bits_unlocked(sst,
 342                 SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK,
 343                 SST_CSR_STALL | SST_CSR_DCS(4));
 344
 345         /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
 346         sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
 347                 SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0,
 348                 SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0);
 349
 350         /* Stall and reset core, set CSR */
 351         hsw_reset(sst);
 352
 353         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 354         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 355         reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
 356         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 357
 358         udelay(50);
 359
 360         /* switch on audio PLL */
 361         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 362         reg &= ~SST_VDRTCL2_APLLSE_MASK;
 363         writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
 364
 365         /* set default power gating control, enable power gating control for all blocks. that is,
 366         can't be accessed, please enable each block before accessing. */
 367         reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 368         reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK;
 369         /* for D0, always enable the block(DSRAM[0]) used for FW dump */
 370         fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT;
 371         writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);
 372
 373
 374         /* disable DMA finish function for SSP0 & SSP1 */
 375         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
 376                 SST_CSR2_SDFD_SSP1);
 377
 378         /* set on-demond mode on engine 0,1 for all channels */
 379         sst_dsp_shim_update_bits(sst, SST_HMDC,
 380                         SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
 381                         SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
 382
 383         /* Enable Interrupt from both sides */
 384         sst_dsp_shim_update_bits(sst, SST_IMRX, (SST_IMRX_BUSY | SST_IMRX_DONE),
 385                                  0x0);
 386         sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY |
 387                                 SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0);
 388
 389         /* clear IPC registers */
 390         sst_dsp_shim_write(sst, SST_IPCX, 0x0);
 391         sst_dsp_shim_write(sst, SST_IPCD, 0x0);
 392         sst_dsp_shim_write(sst, 0x80, 0x6);
 393         sst_dsp_shim_write(sst, 0xe0, 0x300a);
 394
 395         return 0;
 396 }
 397
 398 static void hsw_boot(struct sst_dsp *sst)
 399 {
 400         /* set oportunistic mode on engine 0,1 for all channels */
 401         sst_dsp_shim_update_bits(sst, SST_HMDC,
 402                         SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH, 0);
 403
 404         /* set DSP to RUN */
 405         sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
 406 }
 407
 408 static void hsw_stall(struct sst_dsp *sst)
 409 {
 410         /* stall DSP */
 411         sst_dsp_shim_update_bits(sst, SST_CSR,
 412                 SST_CSR_24MHZ_LPCS | SST_CSR_STALL,
 413                 SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
 414 }
 415
 416 static void hsw_sleep(struct sst_dsp *sst)
 417 {
 418         dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n");
 419
 420         /* put DSP into reset and stall */
 421         sst_dsp_shim_update_bits(sst, SST_CSR,
 422                 SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL,
 423                 SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
 424
 425         hsw_set_dsp_D3(sst);
 426         dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");
 427 }
 428
 429 static int hsw_wake(struct sst_dsp *sst)
 430 {
 431         int ret;
 432
 433         dev_dbg(sst->dev, "HSW_PM dsp runtime resume\n");
 434
 435         ret = hsw_set_dsp_D0(sst);
 436         if (ret < 0)
 437                 return ret;
 438
 439         dev_dbg(sst->dev, "HSW_PM dsp runtime resume exit\n");
 440
 441         return 0;
 442 }
 443
 444 struct sst_adsp_memregion {
 445         u32 start;
 446         u32 end;
 447         int blocks;
 448         enum sst_mem_type type;
 449 };
 450
 451 /* lynx point ADSP mem regions */
 452 static const struct sst_adsp_memregion lp_region[] = {
 453         {0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
 454         {0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
 455         {0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
 456 };
 457
 458 /* wild cat point ADSP mem regions */
 459 static const struct sst_adsp_memregion wpt_region[] = {
 460         {0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
 461         {0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
 462 };
 463
 464 static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
 465 {
 466         /* ADSP DRAM & IRAM */
 467         sst->addr.lpe_base = pdata->lpe_base;
 468         sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
 469         if (!sst->addr.lpe)
 470                 return -ENODEV;
 471
 472         /* ADSP PCI MMIO config space */
 473         sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
 474         if (!sst->addr.pci_cfg) {
 475                 iounmap(sst->addr.lpe);
 476                 return -ENODEV;
 477         }
 478
 479         /* SST Shim */
 480         sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
 481         return 0;
 482 }
 483
 484 struct sst_sram_shift {
 485         u32 dev_id;     /* SST Device IDs  */
 486         u32 iram_shift;
 487         u32 dram_shift;
 488 };
 489
 490 static const struct sst_sram_shift sram_shift[] = {
 491         {SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
 492         {SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
 493 };
 494
 495 static u32 hsw_block_get_bit(struct sst_mem_block *block)
 496 {
 497         u32 bit = 0, shift = 0, index;
 498         struct sst_dsp *sst = block->dsp;
 499
 500         for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
 501                 if (sram_shift[index].dev_id == sst->id)
 502                         break;
 503         }
 504
 505         if (index < ARRAY_SIZE(sram_shift)) {
 506                 switch (block->type) {
 507                 case SST_MEM_DRAM:
 508                         shift = sram_shift[index].dram_shift;
 509                         break;
 510                 case SST_MEM_IRAM:
 511                         shift = sram_shift[index].iram_shift;
 512                         break;
 513                 default:
 514                         shift = 0;
 515                 }
 516         } else
 517                 shift = 0;
 518
 519         bit = 1 << (block->index + shift);
 520
 521         return bit;
 522 }
 523
 524 /*dummy read a SRAM block.*/
 525 static void sst_mem_block_dummy_read(struct sst_mem_block *block)
 526 {
 527         u32 size;
 528         u8 tmp_buf[4];
 529         struct sst_dsp *sst = block->dsp;
 530
 531         size = block->size > 4 ? 4 : block->size;
 532         memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);
 533 }
 534
 535 /* enable 32kB memory block - locks held by caller */
 536 static int hsw_block_enable(struct sst_mem_block *block)
 537 {
 538         struct sst_dsp *sst = block->dsp;
 539         u32 bit, val;
 540
 541         if (block->users++ > 0)
 542                 return 0;
 543
 544         dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
 545                 block->type, block->index, block->offset);
 546
 547         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 548         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 549         val &= ~SST_VDRTCL2_DCLCGE;
 550         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 551
 552         val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 553         bit = hsw_block_get_bit(block);
 554         writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);
 555
 556         /* wait 18 DSP clock ticks */
 557         udelay(10);
 558
 559         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 560         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 561         val |= SST_VDRTCL2_DCLCGE;
 562         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 563
 564         udelay(50);
 565
 566         /*add a dummy read before the SRAM block is written, otherwise the writing may miss bytes sometimes.*/
 567         sst_mem_block_dummy_read(block);
 568         return 0;
 569 }
 570
 571 /* disable 32kB memory block - locks held by caller */
 572 static int hsw_block_disable(struct sst_mem_block *block)
 573 {
 574         struct sst_dsp *sst = block->dsp;
 575         u32 bit, val;
 576
 577         if (--block->users > 0)
 578                 return 0;
 579
 580         dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
 581                 block->type, block->index, block->offset);
 582
 583         /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
 584         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 585         val &= ~SST_VDRTCL2_DCLCGE;
 586         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 587
 588
 589         val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
 590         bit = hsw_block_get_bit(block);
 591         /* don't disable DSRAM[0], keep it always enable for FW dump*/
 592         if (bit != (1 << SST_VDRTCL0_DSRAMPGE_SHIFT))
 593                 writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0);
 594
 595         /* wait 18 DSP clock ticks */
 596         udelay(10);
 597
 598         /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
 599         val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
 600         val |= SST_VDRTCL2_DCLCGE;
 601         writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
 602
 603         udelay(50);
 604
 605         return 0;
 606 }
 607
 608 static struct sst_block_ops sst_hsw_ops = {
 609         .enable = hsw_block_enable,
 610         .disable = hsw_block_disable,
 611 };
 612
 613 static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
 614 {
 615         const struct sst_adsp_memregion *region;
 616         struct device *dev;
 617         int ret = -ENODEV, i, j, region_count;
 618         u32 offset, size, fw_dump_bit;
 619
 620         dev = sst->dma_dev;
 621
 622         switch (sst->id) {
 623         case SST_DEV_ID_LYNX_POINT:
 624                 region = lp_region;
 625                 region_count = ARRAY_SIZE(lp_region);
 626                 sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
 627                 sst->addr.dsp_iram_offset = SST_LPT_DSP_IRAM_OFFSET;
 628                 sst->addr.dsp_dram_offset = SST_LPT_DSP_DRAM_OFFSET;
 629                 sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
 630                 break;
 631         case SST_DEV_ID_WILDCAT_POINT:
 632                 region = wpt_region;
 633                 region_count = ARRAY_SIZE(wpt_region);
 634                 sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
 635                 sst->addr.dsp_iram_offset = SST_WPT_DSP_IRAM_OFFSET;
 636                 sst->addr.dsp_dram_offset = SST_WPT_DSP_DRAM_OFFSET;
 637                 sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
 638                 break;
 639         default:
 640                 dev_err(dev, "error: failed to get mem resources\n");
 641                 return ret;
 642         }
 643
 644         ret = hsw_acpi_resource_map(sst, pdata);
 645         if (ret < 0) {
 646                 dev_err(dev, "error: failed to map resources\n");
 647                 return ret;
 648         }
 649
 650         /* enable the DSP SHIM */
 651         ret = hsw_set_dsp_D0(sst);
 652         if (ret < 0) {
 653                 dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
 654                 return ret;
 655         }
 656
 657         ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
 658         if (ret)
 659                 return ret;
 660
 661
 662         /* register DSP memory blocks - ideally we should get this from ACPI */
 663         for (i = 0; i < region_count; i++) {
 664                 offset = region[i].start;
 665                 size = (region[i].end - region[i].start) / region[i].blocks;
 666
 667                 /* register individual memory blocks */
 668                 for (j = 0; j < region[i].blocks; j++) {
 669                         sst_mem_block_register(sst, offset, size,
 670                                 region[i].type, &sst_hsw_ops, j, sst);
 671                         offset += size;
 672                 }
 673         }
 674
 675         /* always enable the block(DSRAM[0]) used for FW dump */
 676         fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT;
 677         /* set default power gating control, enable power gating control for all blocks. that is,
 678         can't be accessed, please enable each block before accessing. */
 679         writel(0xffffffff & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);
 680
 681         return 0;
 682 }
 683
 684 static void hsw_free(struct sst_dsp *sst)
 685 {
 686         sst_mem_block_unregister_all(sst);
 687         iounmap(sst->addr.lpe);
 688         iounmap(sst->addr.pci_cfg);
 689 }
 690
 691 struct sst_ops haswell_ops = {
 692         .reset = hsw_reset,
 693         .boot = hsw_boot,
 694         .stall = hsw_stall,
 695         .wake = hsw_wake,
 696         .sleep = hsw_sleep,
 697         .write = sst_shim32_write,
 698         .read = sst_shim32_read,
 699         .write64 = sst_shim32_write64,
 700         .read64 = sst_shim32_read64,
 701         .ram_read = sst_memcpy_fromio_32,
 702         .ram_write = sst_memcpy_toio_32,
 703         .irq_handler = hsw_irq,
 704         .init = hsw_init,
 705         .free = hsw_free,
 706         .parse_fw = hsw_parse_fw_image,
 707 };