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Merge tag 'for-4.5' of git://git.osdn.jp/gitroot/uclinux-h8/linux
[deliverable/linux.git] / sound / soc / mediatek / mtk-afe-pcm.c
1 /*
2 * Mediatek ALSA SoC AFE platform driver
3 *
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: Koro Chen <koro.chen@mediatek.com>
6 * Sascha Hauer <s.hauer@pengutronix.de>
7 * Hidalgo Huang <hidalgo.huang@mediatek.com>
8 * Ir Lian <ir.lian@mediatek.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 and
12 * only version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/soc.h>
26 #include "mtk-afe-common.h"
27
28 /*****************************************************************************
29 * R E G I S T E R D E F I N I T I O N
30 *****************************************************************************/
31 #define AUDIO_TOP_CON0 0x0000
32 #define AUDIO_TOP_CON1 0x0004
33 #define AFE_DAC_CON0 0x0010
34 #define AFE_DAC_CON1 0x0014
35 #define AFE_I2S_CON1 0x0034
36 #define AFE_I2S_CON2 0x0038
37 #define AFE_CONN_24BIT 0x006c
38
39 #define AFE_CONN1 0x0024
40 #define AFE_CONN2 0x0028
41 #define AFE_CONN7 0x0460
42 #define AFE_CONN8 0x0464
43 #define AFE_HDMI_CONN0 0x0390
44
45 /* Memory interface */
46 #define AFE_DL1_BASE 0x0040
47 #define AFE_DL1_CUR 0x0044
48 #define AFE_DL1_END 0x0048
49 #define AFE_DL2_BASE 0x0050
50 #define AFE_DL2_CUR 0x0054
51 #define AFE_AWB_BASE 0x0070
52 #define AFE_AWB_CUR 0x007c
53 #define AFE_VUL_BASE 0x0080
54 #define AFE_VUL_CUR 0x008c
55 #define AFE_VUL_END 0x0088
56 #define AFE_DAI_BASE 0x0090
57 #define AFE_DAI_CUR 0x009c
58 #define AFE_MOD_PCM_BASE 0x0330
59 #define AFE_MOD_PCM_CUR 0x033c
60 #define AFE_HDMI_OUT_BASE 0x0374
61 #define AFE_HDMI_OUT_CUR 0x0378
62 #define AFE_HDMI_OUT_END 0x037c
63
64 #define AFE_ADDA2_TOP_CON0 0x0600
65
66 #define AFE_HDMI_OUT_CON0 0x0370
67
68 #define AFE_IRQ_MCU_CON 0x03a0
69 #define AFE_IRQ_STATUS 0x03a4
70 #define AFE_IRQ_CLR 0x03a8
71 #define AFE_IRQ_CNT1 0x03ac
72 #define AFE_IRQ_CNT2 0x03b0
73 #define AFE_IRQ_MCU_EN 0x03b4
74 #define AFE_IRQ_CNT5 0x03bc
75 #define AFE_IRQ_CNT7 0x03dc
76
77 #define AFE_TDM_CON1 0x0548
78 #define AFE_TDM_CON2 0x054c
79
80 #define AFE_BASE_END_OFFSET 8
81 #define AFE_IRQ_STATUS_BITS 0xff
82
83 /* AUDIO_TOP_CON0 (0x0000) */
84 #define AUD_TCON0_PDN_SPDF (0x1 << 21)
85 #define AUD_TCON0_PDN_HDMI (0x1 << 20)
86 #define AUD_TCON0_PDN_24M (0x1 << 9)
87 #define AUD_TCON0_PDN_22M (0x1 << 8)
88 #define AUD_TCON0_PDN_AFE (0x1 << 2)
89
90 /* AFE_I2S_CON1 (0x0034) */
91 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
92 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
93 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
94 #define AFE_I2S_CON1_EN (0x1 << 0)
95
96 /* AFE_I2S_CON2 (0x0038) */
97 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
98 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
99 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
100 #define AFE_I2S_CON2_EN (0x1 << 0)
101
102 /* AFE_CONN_24BIT (0x006c) */
103 #define AFE_CONN_24BIT_O04 (0x1 << 4)
104 #define AFE_CONN_24BIT_O03 (0x1 << 3)
105
106 /* AFE_HDMI_CONN0 (0x0390) */
107 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
108 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
109 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
110 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
111 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
112 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
113 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
114 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
115
116 /* AFE_TDM_CON1 (0x0548) */
117 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
118 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
119 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
120 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
121 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
122 #define AFE_TDM_CON1_BCK_INV (0x1 << 1)
123 #define AFE_TDM_CON1_EN (0x1 << 0)
124
125 enum afe_tdm_ch_start {
126 AFE_TDM_CH_START_O30_O31 = 0,
127 AFE_TDM_CH_START_O32_O33,
128 AFE_TDM_CH_START_O34_O35,
129 AFE_TDM_CH_START_O36_O37,
130 AFE_TDM_CH_ZERO,
131 };
132
133 static const unsigned int mtk_afe_backup_list[] = {
134 AUDIO_TOP_CON0,
135 AFE_CONN1,
136 AFE_CONN2,
137 AFE_CONN7,
138 AFE_CONN8,
139 AFE_DAC_CON1,
140 AFE_DL1_BASE,
141 AFE_DL1_END,
142 AFE_VUL_BASE,
143 AFE_VUL_END,
144 AFE_HDMI_OUT_BASE,
145 AFE_HDMI_OUT_END,
146 AFE_HDMI_CONN0,
147 AFE_DAC_CON0,
148 };
149
150 struct mtk_afe {
151 /* address for ioremap audio hardware register */
152 void __iomem *base_addr;
153 struct device *dev;
154 struct regmap *regmap;
155 struct mtk_afe_memif memif[MTK_AFE_MEMIF_NUM];
156 struct clk *clocks[MTK_CLK_NUM];
157 unsigned int backup_regs[ARRAY_SIZE(mtk_afe_backup_list)];
158 bool suspended;
159 };
160
161 static const struct snd_pcm_hardware mtk_afe_hardware = {
162 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
163 SNDRV_PCM_INFO_MMAP_VALID),
164 .buffer_bytes_max = 256 * 1024,
165 .period_bytes_min = 512,
166 .period_bytes_max = 128 * 1024,
167 .periods_min = 2,
168 .periods_max = 256,
169 .fifo_size = 0,
170 };
171
172 static snd_pcm_uframes_t mtk_afe_pcm_pointer
173 (struct snd_pcm_substream *substream)
174 {
175 struct snd_soc_pcm_runtime *rtd = substream->private_data;
176 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
177 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
178 unsigned int hw_ptr;
179 int ret;
180
181 ret = regmap_read(afe->regmap, memif->data->reg_ofs_cur, &hw_ptr);
182 if (ret || hw_ptr == 0) {
183 dev_err(afe->dev, "%s hw_ptr err\n", __func__);
184 hw_ptr = memif->phys_buf_addr;
185 }
186
187 return bytes_to_frames(substream->runtime,
188 hw_ptr - memif->phys_buf_addr);
189 }
190
191 static const struct snd_pcm_ops mtk_afe_pcm_ops = {
192 .ioctl = snd_pcm_lib_ioctl,
193 .pointer = mtk_afe_pcm_pointer,
194 };
195
196 static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime *rtd)
197 {
198 size_t size;
199 struct snd_card *card = rtd->card->snd_card;
200 struct snd_pcm *pcm = rtd->pcm;
201
202 size = mtk_afe_hardware.buffer_bytes_max;
203
204 return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
205 card->dev, size, size);
206 }
207
208 static void mtk_afe_pcm_free(struct snd_pcm *pcm)
209 {
210 snd_pcm_lib_preallocate_free_for_all(pcm);
211 }
212
213 static const struct snd_soc_platform_driver mtk_afe_pcm_platform = {
214 .ops = &mtk_afe_pcm_ops,
215 .pcm_new = mtk_afe_pcm_new,
216 .pcm_free = mtk_afe_pcm_free,
217 };
218
219 struct mtk_afe_rate {
220 unsigned int rate;
221 unsigned int regvalue;
222 };
223
224 static const struct mtk_afe_rate mtk_afe_i2s_rates[] = {
225 { .rate = 8000, .regvalue = 0 },
226 { .rate = 11025, .regvalue = 1 },
227 { .rate = 12000, .regvalue = 2 },
228 { .rate = 16000, .regvalue = 4 },
229 { .rate = 22050, .regvalue = 5 },
230 { .rate = 24000, .regvalue = 6 },
231 { .rate = 32000, .regvalue = 8 },
232 { .rate = 44100, .regvalue = 9 },
233 { .rate = 48000, .regvalue = 10 },
234 { .rate = 88000, .regvalue = 11 },
235 { .rate = 96000, .regvalue = 12 },
236 { .rate = 174000, .regvalue = 13 },
237 { .rate = 192000, .regvalue = 14 },
238 };
239
240 static int mtk_afe_i2s_fs(unsigned int sample_rate)
241 {
242 int i;
243
244 for (i = 0; i < ARRAY_SIZE(mtk_afe_i2s_rates); i++)
245 if (mtk_afe_i2s_rates[i].rate == sample_rate)
246 return mtk_afe_i2s_rates[i].regvalue;
247
248 return -EINVAL;
249 }
250
251 static int mtk_afe_set_i2s(struct mtk_afe *afe, unsigned int rate)
252 {
253 unsigned int val;
254 int fs = mtk_afe_i2s_fs(rate);
255
256 if (fs < 0)
257 return -EINVAL;
258
259 /* from external ADC */
260 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
261
262 /* set input */
263 val = AFE_I2S_CON2_LOW_JITTER_CLK |
264 AFE_I2S_CON2_RATE(fs) |
265 AFE_I2S_CON2_FORMAT_I2S;
266
267 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
268
269 /* set output */
270 val = AFE_I2S_CON1_LOW_JITTER_CLK |
271 AFE_I2S_CON1_RATE(fs) |
272 AFE_I2S_CON1_FORMAT_I2S;
273
274 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
275 return 0;
276 }
277
278 static void mtk_afe_set_i2s_enable(struct mtk_afe *afe, bool enable)
279 {
280 unsigned int val;
281
282 regmap_read(afe->regmap, AFE_I2S_CON2, &val);
283 if (!!(val & AFE_I2S_CON2_EN) == enable)
284 return; /* must skip soft reset */
285
286 /* I2S soft reset begin */
287 regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0x4);
288
289 /* input */
290 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
291
292 /* output */
293 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
294
295 /* I2S soft reset end */
296 udelay(1);
297 regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0);
298 }
299
300 static int mtk_afe_dais_enable_clks(struct mtk_afe *afe,
301 struct clk *m_ck, struct clk *b_ck)
302 {
303 int ret;
304
305 if (m_ck) {
306 ret = clk_prepare_enable(m_ck);
307 if (ret) {
308 dev_err(afe->dev, "Failed to enable m_ck\n");
309 return ret;
310 }
311 }
312
313 if (b_ck) {
314 ret = clk_prepare_enable(b_ck);
315 if (ret) {
316 dev_err(afe->dev, "Failed to enable b_ck\n");
317 return ret;
318 }
319 }
320 return 0;
321 }
322
323 static int mtk_afe_dais_set_clks(struct mtk_afe *afe,
324 struct clk *m_ck, unsigned int mck_rate,
325 struct clk *b_ck, unsigned int bck_rate)
326 {
327 int ret;
328
329 if (m_ck) {
330 ret = clk_set_rate(m_ck, mck_rate);
331 if (ret) {
332 dev_err(afe->dev, "Failed to set m_ck rate\n");
333 return ret;
334 }
335 }
336
337 if (b_ck) {
338 ret = clk_set_rate(b_ck, bck_rate);
339 if (ret) {
340 dev_err(afe->dev, "Failed to set b_ck rate\n");
341 return ret;
342 }
343 }
344 return 0;
345 }
346
347 static void mtk_afe_dais_disable_clks(struct mtk_afe *afe,
348 struct clk *m_ck, struct clk *b_ck)
349 {
350 if (m_ck)
351 clk_disable_unprepare(m_ck);
352 if (b_ck)
353 clk_disable_unprepare(b_ck);
354 }
355
356 static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream,
357 struct snd_soc_dai *dai)
358 {
359 struct snd_soc_pcm_runtime *rtd = substream->private_data;
360 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
361
362 if (dai->active)
363 return 0;
364
365 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
366 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
367 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
368 return 0;
369 }
370
371 static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream,
372 struct snd_soc_dai *dai)
373 {
374 struct snd_soc_pcm_runtime *rtd = substream->private_data;
375 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
376
377 if (dai->active)
378 return;
379
380 mtk_afe_set_i2s_enable(afe, false);
381 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
382 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
383 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
384 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
385 }
386
387 static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
388 struct snd_soc_dai *dai)
389 {
390 struct snd_soc_pcm_runtime *rtd = substream->private_data;
391 struct snd_pcm_runtime * const runtime = substream->runtime;
392 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
393 int ret;
394
395 mtk_afe_dais_set_clks(afe,
396 afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256,
397 NULL, 0);
398 /* config I2S */
399 ret = mtk_afe_set_i2s(afe, substream->runtime->rate);
400 if (ret)
401 return ret;
402
403 mtk_afe_set_i2s_enable(afe, true);
404
405 return 0;
406 }
407
408 static int mtk_afe_hdmi_startup(struct snd_pcm_substream *substream,
409 struct snd_soc_dai *dai)
410 {
411 struct snd_soc_pcm_runtime *rtd = substream->private_data;
412 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
413
414 if (dai->active)
415 return 0;
416
417 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
418 afe->clocks[MTK_CLK_I2S3_B]);
419 return 0;
420 }
421
422 static void mtk_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
423 struct snd_soc_dai *dai)
424 {
425 struct snd_soc_pcm_runtime *rtd = substream->private_data;
426 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
427
428 if (dai->active)
429 return;
430
431 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
432 afe->clocks[MTK_CLK_I2S3_B]);
433 }
434
435 static int mtk_afe_hdmi_prepare(struct snd_pcm_substream *substream,
436 struct snd_soc_dai *dai)
437 {
438 struct snd_soc_pcm_runtime *rtd = substream->private_data;
439 struct snd_pcm_runtime * const runtime = substream->runtime;
440 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
441 unsigned int val;
442
443 mtk_afe_dais_set_clks(afe,
444 afe->clocks[MTK_CLK_I2S3_M], runtime->rate * 128,
445 afe->clocks[MTK_CLK_I2S3_B],
446 runtime->rate * runtime->channels * 32);
447
448 val = AFE_TDM_CON1_BCK_INV |
449 AFE_TDM_CON1_1_BCK_DELAY |
450 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
451 AFE_TDM_CON1_WLEN_32BIT |
452 AFE_TDM_CON1_32_BCK_CYCLES |
453 AFE_TDM_CON1_LRCK_WIDTH(32);
454 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
455
456 /* set tdm2 config */
457 switch (runtime->channels) {
458 case 1:
459 case 2:
460 val = AFE_TDM_CH_START_O30_O31;
461 val |= (AFE_TDM_CH_ZERO << 4);
462 val |= (AFE_TDM_CH_ZERO << 8);
463 val |= (AFE_TDM_CH_ZERO << 12);
464 break;
465 case 3:
466 case 4:
467 val = AFE_TDM_CH_START_O30_O31;
468 val |= (AFE_TDM_CH_START_O32_O33 << 4);
469 val |= (AFE_TDM_CH_ZERO << 8);
470 val |= (AFE_TDM_CH_ZERO << 12);
471 break;
472 case 5:
473 case 6:
474 val = AFE_TDM_CH_START_O30_O31;
475 val |= (AFE_TDM_CH_START_O32_O33 << 4);
476 val |= (AFE_TDM_CH_START_O34_O35 << 8);
477 val |= (AFE_TDM_CH_ZERO << 12);
478 break;
479 case 7:
480 case 8:
481 val = AFE_TDM_CH_START_O30_O31;
482 val |= (AFE_TDM_CH_START_O32_O33 << 4);
483 val |= (AFE_TDM_CH_START_O34_O35 << 8);
484 val |= (AFE_TDM_CH_START_O36_O37 << 12);
485 break;
486 default:
487 val = 0;
488 }
489 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
490
491 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
492 0x000000f0, runtime->channels << 4);
493 return 0;
494 }
495
496 static int mtk_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
497 struct snd_soc_dai *dai)
498 {
499 struct snd_soc_pcm_runtime *rtd = substream->private_data;
500 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
501
502 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
503
504 switch (cmd) {
505 case SNDRV_PCM_TRIGGER_START:
506 case SNDRV_PCM_TRIGGER_RESUME:
507 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
508 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
509
510 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
511 regmap_write(afe->regmap, AFE_HDMI_CONN0,
512 AFE_HDMI_CONN0_O30_I30 | AFE_HDMI_CONN0_O31_I31 |
513 AFE_HDMI_CONN0_O32_I34 | AFE_HDMI_CONN0_O33_I35 |
514 AFE_HDMI_CONN0_O34_I32 | AFE_HDMI_CONN0_O35_I33 |
515 AFE_HDMI_CONN0_O36_I36 | AFE_HDMI_CONN0_O37_I37);
516
517 /* enable Out control */
518 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
519
520 /* enable tdm */
521 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
522
523 return 0;
524 case SNDRV_PCM_TRIGGER_STOP:
525 case SNDRV_PCM_TRIGGER_SUSPEND:
526 /* disable tdm */
527 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
528
529 /* disable Out control */
530 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
531
532 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
533 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
534 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
535
536 return 0;
537 default:
538 return -EINVAL;
539 }
540 }
541
542 static int mtk_afe_dais_startup(struct snd_pcm_substream *substream,
543 struct snd_soc_dai *dai)
544 {
545 struct snd_soc_pcm_runtime *rtd = substream->private_data;
546 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
547 struct snd_pcm_runtime *runtime = substream->runtime;
548 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
549 int ret;
550
551 memif->substream = substream;
552
553 snd_soc_set_runtime_hwparams(substream, &mtk_afe_hardware);
554
555 /*
556 * Capture cannot use ping-pong buffer since hw_ptr at IRQ may be
557 * smaller than period_size due to AFE's internal buffer.
558 * This easily leads to overrun when avail_min is period_size.
559 * One more period can hold the possible unread buffer.
560 */
561 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
562 ret = snd_pcm_hw_constraint_minmax(runtime,
563 SNDRV_PCM_HW_PARAM_PERIODS,
564 3,
565 mtk_afe_hardware.periods_max);
566 if (ret < 0) {
567 dev_err(afe->dev, "hw_constraint_minmax failed\n");
568 return ret;
569 }
570 }
571 ret = snd_pcm_hw_constraint_integer(runtime,
572 SNDRV_PCM_HW_PARAM_PERIODS);
573 if (ret < 0)
574 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
575 return ret;
576 }
577
578 static void mtk_afe_dais_shutdown(struct snd_pcm_substream *substream,
579 struct snd_soc_dai *dai)
580 {
581 struct snd_soc_pcm_runtime *rtd = substream->private_data;
582 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
583 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
584
585 memif->substream = NULL;
586 }
587
588 static int mtk_afe_dais_hw_params(struct snd_pcm_substream *substream,
589 struct snd_pcm_hw_params *params,
590 struct snd_soc_dai *dai)
591 {
592 struct snd_soc_pcm_runtime *rtd = substream->private_data;
593 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
594 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
595 int ret;
596
597 dev_dbg(afe->dev,
598 "%s period = %u, rate= %u, channels=%u\n",
599 __func__, params_period_size(params), params_rate(params),
600 params_channels(params));
601
602 ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
603 if (ret < 0)
604 return ret;
605
606 memif->phys_buf_addr = substream->runtime->dma_addr;
607 memif->buffer_size = substream->runtime->dma_bytes;
608
609 /* start */
610 regmap_write(afe->regmap,
611 memif->data->reg_ofs_base, memif->phys_buf_addr);
612 /* end */
613 regmap_write(afe->regmap,
614 memif->data->reg_ofs_base + AFE_BASE_END_OFFSET,
615 memif->phys_buf_addr + memif->buffer_size - 1);
616
617 /* set channel */
618 if (memif->data->mono_shift >= 0) {
619 unsigned int mono = (params_channels(params) == 1) ? 1 : 0;
620
621 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
622 1 << memif->data->mono_shift,
623 mono << memif->data->mono_shift);
624 }
625
626 /* set rate */
627 if (memif->data->fs_shift < 0)
628 return 0;
629 if (memif->data->id == MTK_AFE_MEMIF_DAI ||
630 memif->data->id == MTK_AFE_MEMIF_MOD_DAI) {
631 unsigned int val;
632
633 switch (params_rate(params)) {
634 case 8000:
635 val = 0;
636 break;
637 case 16000:
638 val = 1;
639 break;
640 case 32000:
641 val = 2;
642 break;
643 default:
644 return -EINVAL;
645 }
646
647 if (memif->data->id == MTK_AFE_MEMIF_DAI)
648 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
649 0x3 << memif->data->fs_shift,
650 val << memif->data->fs_shift);
651 else
652 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
653 0x3 << memif->data->fs_shift,
654 val << memif->data->fs_shift);
655
656 } else {
657 int fs = mtk_afe_i2s_fs(params_rate(params));
658
659 if (fs < 0)
660 return -EINVAL;
661
662 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
663 0xf << memif->data->fs_shift,
664 fs << memif->data->fs_shift);
665 }
666
667 return 0;
668 }
669
670 static int mtk_afe_dais_hw_free(struct snd_pcm_substream *substream,
671 struct snd_soc_dai *dai)
672 {
673 return snd_pcm_lib_free_pages(substream);
674 }
675
676 static int mtk_afe_dais_trigger(struct snd_pcm_substream *substream, int cmd,
677 struct snd_soc_dai *dai)
678 {
679 struct snd_soc_pcm_runtime *rtd = substream->private_data;
680 struct snd_pcm_runtime * const runtime = substream->runtime;
681 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
682 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
683 unsigned int counter = runtime->period_size;
684
685 dev_info(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd);
686
687 switch (cmd) {
688 case SNDRV_PCM_TRIGGER_START:
689 case SNDRV_PCM_TRIGGER_RESUME:
690 if (memif->data->enable_shift >= 0)
691 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
692 1 << memif->data->enable_shift,
693 1 << memif->data->enable_shift);
694
695 /* set irq counter */
696 regmap_update_bits(afe->regmap,
697 memif->data->irq_reg_cnt,
698 0x3ffff << memif->data->irq_cnt_shift,
699 counter << memif->data->irq_cnt_shift);
700
701 /* set irq fs */
702 if (memif->data->irq_fs_shift >= 0) {
703 int fs = mtk_afe_i2s_fs(runtime->rate);
704
705 if (fs < 0)
706 return -EINVAL;
707
708 regmap_update_bits(afe->regmap,
709 AFE_IRQ_MCU_CON,
710 0xf << memif->data->irq_fs_shift,
711 fs << memif->data->irq_fs_shift);
712 }
713 /* enable interrupt */
714 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
715 1 << memif->data->irq_en_shift,
716 1 << memif->data->irq_en_shift);
717
718 return 0;
719 case SNDRV_PCM_TRIGGER_STOP:
720 case SNDRV_PCM_TRIGGER_SUSPEND:
721 if (memif->data->enable_shift >= 0)
722 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
723 1 << memif->data->enable_shift, 0);
724 /* disable interrupt */
725 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
726 1 << memif->data->irq_en_shift,
727 0 << memif->data->irq_en_shift);
728 /* and clear pending IRQ */
729 regmap_write(afe->regmap, AFE_IRQ_CLR,
730 1 << memif->data->irq_clr_shift);
731 return 0;
732 default:
733 return -EINVAL;
734 }
735 }
736
737 /* FE DAIs */
738 static const struct snd_soc_dai_ops mtk_afe_dai_ops = {
739 .startup = mtk_afe_dais_startup,
740 .shutdown = mtk_afe_dais_shutdown,
741 .hw_params = mtk_afe_dais_hw_params,
742 .hw_free = mtk_afe_dais_hw_free,
743 .trigger = mtk_afe_dais_trigger,
744 };
745
746 /* BE DAIs */
747 static const struct snd_soc_dai_ops mtk_afe_i2s_ops = {
748 .startup = mtk_afe_i2s_startup,
749 .shutdown = mtk_afe_i2s_shutdown,
750 .prepare = mtk_afe_i2s_prepare,
751 };
752
753 static const struct snd_soc_dai_ops mtk_afe_hdmi_ops = {
754 .startup = mtk_afe_hdmi_startup,
755 .shutdown = mtk_afe_hdmi_shutdown,
756 .prepare = mtk_afe_hdmi_prepare,
757 .trigger = mtk_afe_hdmi_trigger,
758
759 };
760
761 static int mtk_afe_runtime_suspend(struct device *dev);
762 static int mtk_afe_runtime_resume(struct device *dev);
763
764 static int mtk_afe_dai_suspend(struct snd_soc_dai *dai)
765 {
766 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
767 int i;
768
769 dev_dbg(afe->dev, "%s\n", __func__);
770 if (pm_runtime_status_suspended(afe->dev) || afe->suspended)
771 return 0;
772
773 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
774 regmap_read(afe->regmap, mtk_afe_backup_list[i],
775 &afe->backup_regs[i]);
776
777 afe->suspended = true;
778 mtk_afe_runtime_suspend(afe->dev);
779 return 0;
780 }
781
782 static int mtk_afe_dai_resume(struct snd_soc_dai *dai)
783 {
784 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
785 int i = 0;
786
787 dev_dbg(afe->dev, "%s\n", __func__);
788 if (pm_runtime_status_suspended(afe->dev) || !afe->suspended)
789 return 0;
790
791 mtk_afe_runtime_resume(afe->dev);
792
793 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
794 regmap_write(afe->regmap, mtk_afe_backup_list[i],
795 afe->backup_regs[i]);
796
797 afe->suspended = false;
798 return 0;
799 }
800
801 static struct snd_soc_dai_driver mtk_afe_pcm_dais[] = {
802 /* FE DAIs: memory intefaces to CPU */
803 {
804 .name = "DL1", /* downlink 1 */
805 .id = MTK_AFE_MEMIF_DL1,
806 .suspend = mtk_afe_dai_suspend,
807 .resume = mtk_afe_dai_resume,
808 .playback = {
809 .stream_name = "DL1",
810 .channels_min = 1,
811 .channels_max = 2,
812 .rates = SNDRV_PCM_RATE_8000_48000,
813 .formats = SNDRV_PCM_FMTBIT_S16_LE,
814 },
815 .ops = &mtk_afe_dai_ops,
816 }, {
817 .name = "VUL", /* voice uplink */
818 .id = MTK_AFE_MEMIF_VUL,
819 .suspend = mtk_afe_dai_suspend,
820 .resume = mtk_afe_dai_resume,
821 .capture = {
822 .stream_name = "VUL",
823 .channels_min = 1,
824 .channels_max = 2,
825 .rates = SNDRV_PCM_RATE_8000_48000,
826 .formats = SNDRV_PCM_FMTBIT_S16_LE,
827 },
828 .ops = &mtk_afe_dai_ops,
829 }, {
830 /* BE DAIs */
831 .name = "I2S",
832 .id = MTK_AFE_IO_I2S,
833 .playback = {
834 .stream_name = "I2S Playback",
835 .channels_min = 1,
836 .channels_max = 2,
837 .rates = SNDRV_PCM_RATE_8000_48000,
838 .formats = SNDRV_PCM_FMTBIT_S16_LE,
839 },
840 .capture = {
841 .stream_name = "I2S Capture",
842 .channels_min = 1,
843 .channels_max = 2,
844 .rates = SNDRV_PCM_RATE_8000_48000,
845 .formats = SNDRV_PCM_FMTBIT_S16_LE,
846 },
847 .ops = &mtk_afe_i2s_ops,
848 .symmetric_rates = 1,
849 },
850 };
851
852 static struct snd_soc_dai_driver mtk_afe_hdmi_dais[] = {
853 /* FE DAIs */
854 {
855 .name = "HDMI",
856 .id = MTK_AFE_MEMIF_HDMI,
857 .suspend = mtk_afe_dai_suspend,
858 .resume = mtk_afe_dai_resume,
859 .playback = {
860 .stream_name = "HDMI",
861 .channels_min = 2,
862 .channels_max = 8,
863 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
864 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
865 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
866 SNDRV_PCM_RATE_192000,
867 .formats = SNDRV_PCM_FMTBIT_S16_LE,
868 },
869 .ops = &mtk_afe_dai_ops,
870 }, {
871 /* BE DAIs */
872 .name = "HDMIO",
873 .id = MTK_AFE_IO_HDMI,
874 .playback = {
875 .stream_name = "HDMIO Playback",
876 .channels_min = 2,
877 .channels_max = 8,
878 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
879 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
880 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
881 SNDRV_PCM_RATE_192000,
882 .formats = SNDRV_PCM_FMTBIT_S16_LE,
883 },
884 .ops = &mtk_afe_hdmi_ops,
885 },
886 };
887
888 static const struct snd_kcontrol_new mtk_afe_o03_mix[] = {
889 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
890 };
891
892 static const struct snd_kcontrol_new mtk_afe_o04_mix[] = {
893 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
894 };
895
896 static const struct snd_kcontrol_new mtk_afe_o09_mix[] = {
897 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
898 };
899
900 static const struct snd_kcontrol_new mtk_afe_o10_mix[] = {
901 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
902 };
903
904 static const struct snd_soc_dapm_widget mtk_afe_pcm_widgets[] = {
905 /* inter-connections */
906 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
907 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
908 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
909 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
910
911 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
912 mtk_afe_o03_mix, ARRAY_SIZE(mtk_afe_o03_mix)),
913 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
914 mtk_afe_o04_mix, ARRAY_SIZE(mtk_afe_o04_mix)),
915 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
916 mtk_afe_o09_mix, ARRAY_SIZE(mtk_afe_o09_mix)),
917 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
918 mtk_afe_o10_mix, ARRAY_SIZE(mtk_afe_o10_mix)),
919 };
920
921 static const struct snd_soc_dapm_route mtk_afe_pcm_routes[] = {
922 {"I05", NULL, "DL1"},
923 {"I06", NULL, "DL1"},
924 {"I2S Playback", NULL, "O03"},
925 {"I2S Playback", NULL, "O04"},
926 {"VUL", NULL, "O09"},
927 {"VUL", NULL, "O10"},
928 {"I17", NULL, "I2S Capture"},
929 {"I18", NULL, "I2S Capture"},
930 { "O03", "I05 Switch", "I05" },
931 { "O04", "I06 Switch", "I06" },
932 { "O09", "I17 Switch", "I17" },
933 { "O10", "I18 Switch", "I18" },
934 };
935
936 static const struct snd_soc_dapm_route mtk_afe_hdmi_routes[] = {
937 {"HDMIO Playback", NULL, "HDMI"},
938 };
939
940 static const struct snd_soc_component_driver mtk_afe_pcm_dai_component = {
941 .name = "mtk-afe-pcm-dai",
942 .dapm_widgets = mtk_afe_pcm_widgets,
943 .num_dapm_widgets = ARRAY_SIZE(mtk_afe_pcm_widgets),
944 .dapm_routes = mtk_afe_pcm_routes,
945 .num_dapm_routes = ARRAY_SIZE(mtk_afe_pcm_routes),
946 };
947
948 static const struct snd_soc_component_driver mtk_afe_hdmi_dai_component = {
949 .name = "mtk-afe-hdmi-dai",
950 .dapm_routes = mtk_afe_hdmi_routes,
951 .num_dapm_routes = ARRAY_SIZE(mtk_afe_hdmi_routes),
952 };
953
954 static const char *aud_clks[MTK_CLK_NUM] = {
955 [MTK_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
956 [MTK_CLK_TOP_PDN_AUD] = "top_pdn_audio",
957 [MTK_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
958 [MTK_CLK_I2S0_M] = "i2s0_m",
959 [MTK_CLK_I2S1_M] = "i2s1_m",
960 [MTK_CLK_I2S2_M] = "i2s2_m",
961 [MTK_CLK_I2S3_M] = "i2s3_m",
962 [MTK_CLK_I2S3_B] = "i2s3_b",
963 [MTK_CLK_BCK0] = "bck0",
964 [MTK_CLK_BCK1] = "bck1",
965 };
966
967 static const struct mtk_afe_memif_data memif_data[MTK_AFE_MEMIF_NUM] = {
968 {
969 .name = "DL1",
970 .id = MTK_AFE_MEMIF_DL1,
971 .reg_ofs_base = AFE_DL1_BASE,
972 .reg_ofs_cur = AFE_DL1_CUR,
973 .fs_shift = 0,
974 .mono_shift = 21,
975 .enable_shift = 1,
976 .irq_reg_cnt = AFE_IRQ_CNT1,
977 .irq_cnt_shift = 0,
978 .irq_en_shift = 0,
979 .irq_fs_shift = 4,
980 .irq_clr_shift = 0,
981 }, {
982 .name = "DL2",
983 .id = MTK_AFE_MEMIF_DL2,
984 .reg_ofs_base = AFE_DL2_BASE,
985 .reg_ofs_cur = AFE_DL2_CUR,
986 .fs_shift = 4,
987 .mono_shift = 22,
988 .enable_shift = 2,
989 .irq_reg_cnt = AFE_IRQ_CNT1,
990 .irq_cnt_shift = 20,
991 .irq_en_shift = 2,
992 .irq_fs_shift = 16,
993 .irq_clr_shift = 2,
994 }, {
995 .name = "VUL",
996 .id = MTK_AFE_MEMIF_VUL,
997 .reg_ofs_base = AFE_VUL_BASE,
998 .reg_ofs_cur = AFE_VUL_CUR,
999 .fs_shift = 16,
1000 .mono_shift = 27,
1001 .enable_shift = 3,
1002 .irq_reg_cnt = AFE_IRQ_CNT2,
1003 .irq_cnt_shift = 0,
1004 .irq_en_shift = 1,
1005 .irq_fs_shift = 8,
1006 .irq_clr_shift = 1,
1007 }, {
1008 .name = "DAI",
1009 .id = MTK_AFE_MEMIF_DAI,
1010 .reg_ofs_base = AFE_DAI_BASE,
1011 .reg_ofs_cur = AFE_DAI_CUR,
1012 .fs_shift = 24,
1013 .mono_shift = -1,
1014 .enable_shift = 4,
1015 .irq_reg_cnt = AFE_IRQ_CNT2,
1016 .irq_cnt_shift = 20,
1017 .irq_en_shift = 3,
1018 .irq_fs_shift = 20,
1019 .irq_clr_shift = 3,
1020 }, {
1021 .name = "AWB",
1022 .id = MTK_AFE_MEMIF_AWB,
1023 .reg_ofs_base = AFE_AWB_BASE,
1024 .reg_ofs_cur = AFE_AWB_CUR,
1025 .fs_shift = 12,
1026 .mono_shift = 24,
1027 .enable_shift = 6,
1028 .irq_reg_cnt = AFE_IRQ_CNT7,
1029 .irq_cnt_shift = 0,
1030 .irq_en_shift = 14,
1031 .irq_fs_shift = 24,
1032 .irq_clr_shift = 6,
1033 }, {
1034 .name = "MOD_DAI",
1035 .id = MTK_AFE_MEMIF_MOD_DAI,
1036 .reg_ofs_base = AFE_MOD_PCM_BASE,
1037 .reg_ofs_cur = AFE_MOD_PCM_CUR,
1038 .fs_shift = 30,
1039 .mono_shift = 30,
1040 .enable_shift = 7,
1041 .irq_reg_cnt = AFE_IRQ_CNT2,
1042 .irq_cnt_shift = 20,
1043 .irq_en_shift = 3,
1044 .irq_fs_shift = 20,
1045 .irq_clr_shift = 3,
1046 }, {
1047 .name = "HDMI",
1048 .id = MTK_AFE_MEMIF_HDMI,
1049 .reg_ofs_base = AFE_HDMI_OUT_BASE,
1050 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
1051 .fs_shift = -1,
1052 .mono_shift = -1,
1053 .enable_shift = -1,
1054 .irq_reg_cnt = AFE_IRQ_CNT5,
1055 .irq_cnt_shift = 0,
1056 .irq_en_shift = 12,
1057 .irq_fs_shift = -1,
1058 .irq_clr_shift = 4,
1059 },
1060 };
1061
1062 static const struct regmap_config mtk_afe_regmap_config = {
1063 .reg_bits = 32,
1064 .reg_stride = 4,
1065 .val_bits = 32,
1066 .max_register = AFE_ADDA2_TOP_CON0,
1067 .cache_type = REGCACHE_NONE,
1068 };
1069
1070 static irqreturn_t mtk_afe_irq_handler(int irq, void *dev_id)
1071 {
1072 struct mtk_afe *afe = dev_id;
1073 unsigned int reg_value;
1074 int i, ret;
1075
1076 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);
1077 if (ret) {
1078 dev_err(afe->dev, "%s irq status err\n", __func__);
1079 reg_value = AFE_IRQ_STATUS_BITS;
1080 goto err_irq;
1081 }
1082
1083 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++) {
1084 struct mtk_afe_memif *memif = &afe->memif[i];
1085
1086 if (!(reg_value & (1 << memif->data->irq_clr_shift)))
1087 continue;
1088
1089 snd_pcm_period_elapsed(memif->substream);
1090 }
1091
1092 err_irq:
1093 /* clear irq */
1094 regmap_write(afe->regmap, AFE_IRQ_CLR, reg_value & AFE_IRQ_STATUS_BITS);
1095
1096 return IRQ_HANDLED;
1097 }
1098
1099 static int mtk_afe_runtime_suspend(struct device *dev)
1100 {
1101 struct mtk_afe *afe = dev_get_drvdata(dev);
1102
1103 /* disable AFE */
1104 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
1105
1106 /* disable AFE clk */
1107 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
1108 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
1109
1110 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1111 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]);
1112 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1113 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1114 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1115 return 0;
1116 }
1117
1118 static int mtk_afe_runtime_resume(struct device *dev)
1119 {
1120 struct mtk_afe *afe = dev_get_drvdata(dev);
1121 int ret;
1122
1123 ret = clk_prepare_enable(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1124 if (ret)
1125 return ret;
1126
1127 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1128 if (ret)
1129 goto err_infra;
1130
1131 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1132 if (ret)
1133 goto err_top_aud_bus;
1134
1135 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK0]);
1136 if (ret)
1137 goto err_top_aud;
1138
1139 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]);
1140 if (ret)
1141 goto err_bck0;
1142
1143 /* enable AFE clk */
1144 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1145
1146 /* set O3/O4 16bits */
1147 regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1148 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1149
1150 /* unmask all IRQs */
1151 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1152
1153 /* enable AFE */
1154 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1155 return 0;
1156
1157 err_bck0:
1158 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1159 err_top_aud:
1160 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1161 err_top_aud_bus:
1162 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1163 err_infra:
1164 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1165 return ret;
1166 }
1167
1168 static int mtk_afe_init_audio_clk(struct mtk_afe *afe)
1169 {
1170 size_t i;
1171
1172 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1173 afe->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1174 if (IS_ERR(afe->clocks[i])) {
1175 dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1176 __func__, aud_clks[i]);
1177 return PTR_ERR(afe->clocks[i]);
1178 }
1179 }
1180 clk_set_rate(afe->clocks[MTK_CLK_BCK0], 22579200); /* 22M */
1181 clk_set_rate(afe->clocks[MTK_CLK_BCK1], 24576000); /* 24M */
1182 return 0;
1183 }
1184
1185 static int mtk_afe_pcm_dev_probe(struct platform_device *pdev)
1186 {
1187 int ret, i;
1188 unsigned int irq_id;
1189 struct mtk_afe *afe;
1190 struct resource *res;
1191
1192 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1193 if (!afe)
1194 return -ENOMEM;
1195
1196 afe->dev = &pdev->dev;
1197
1198 irq_id = platform_get_irq(pdev, 0);
1199 if (!irq_id) {
1200 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1201 return -ENXIO;
1202 }
1203 ret = devm_request_irq(afe->dev, irq_id, mtk_afe_irq_handler,
1204 0, "Afe_ISR_Handle", (void *)afe);
1205 if (ret) {
1206 dev_err(afe->dev, "could not request_irq\n");
1207 return ret;
1208 }
1209
1210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1211 afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1212 if (IS_ERR(afe->base_addr))
1213 return PTR_ERR(afe->base_addr);
1214
1215 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1216 &mtk_afe_regmap_config);
1217 if (IS_ERR(afe->regmap))
1218 return PTR_ERR(afe->regmap);
1219
1220 /* initial audio related clock */
1221 ret = mtk_afe_init_audio_clk(afe);
1222 if (ret) {
1223 dev_err(afe->dev, "mtk_afe_init_audio_clk fail\n");
1224 return ret;
1225 }
1226
1227 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++)
1228 afe->memif[i].data = &memif_data[i];
1229
1230 platform_set_drvdata(pdev, afe);
1231
1232 pm_runtime_enable(&pdev->dev);
1233 if (!pm_runtime_enabled(&pdev->dev)) {
1234 ret = mtk_afe_runtime_resume(&pdev->dev);
1235 if (ret)
1236 goto err_pm_disable;
1237 }
1238
1239 ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform);
1240 if (ret)
1241 goto err_pm_disable;
1242
1243 ret = snd_soc_register_component(&pdev->dev,
1244 &mtk_afe_pcm_dai_component,
1245 mtk_afe_pcm_dais,
1246 ARRAY_SIZE(mtk_afe_pcm_dais));
1247 if (ret)
1248 goto err_platform;
1249
1250 ret = snd_soc_register_component(&pdev->dev,
1251 &mtk_afe_hdmi_dai_component,
1252 mtk_afe_hdmi_dais,
1253 ARRAY_SIZE(mtk_afe_hdmi_dais));
1254 if (ret)
1255 goto err_comp;
1256
1257 dev_info(&pdev->dev, "MTK AFE driver initialized.\n");
1258 return 0;
1259
1260 err_comp:
1261 snd_soc_unregister_component(&pdev->dev);
1262 err_platform:
1263 snd_soc_unregister_platform(&pdev->dev);
1264 err_pm_disable:
1265 pm_runtime_disable(&pdev->dev);
1266 return ret;
1267 }
1268
1269 static int mtk_afe_pcm_dev_remove(struct platform_device *pdev)
1270 {
1271 pm_runtime_disable(&pdev->dev);
1272 if (!pm_runtime_status_suspended(&pdev->dev))
1273 mtk_afe_runtime_suspend(&pdev->dev);
1274 snd_soc_unregister_component(&pdev->dev);
1275 snd_soc_unregister_platform(&pdev->dev);
1276 return 0;
1277 }
1278
1279 static const struct of_device_id mtk_afe_pcm_dt_match[] = {
1280 { .compatible = "mediatek,mt8173-afe-pcm", },
1281 { }
1282 };
1283 MODULE_DEVICE_TABLE(of, mtk_afe_pcm_dt_match);
1284
1285 static const struct dev_pm_ops mtk_afe_pm_ops = {
1286 SET_RUNTIME_PM_OPS(mtk_afe_runtime_suspend, mtk_afe_runtime_resume,
1287 NULL)
1288 };
1289
1290 static struct platform_driver mtk_afe_pcm_driver = {
1291 .driver = {
1292 .name = "mtk-afe-pcm",
1293 .of_match_table = mtk_afe_pcm_dt_match,
1294 .pm = &mtk_afe_pm_ops,
1295 },
1296 .probe = mtk_afe_pcm_dev_probe,
1297 .remove = mtk_afe_pcm_dev_remove,
1298 };
1299
1300 module_platform_driver(mtk_afe_pcm_driver);
1301
1302 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1303 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1304 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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