2 * Mediatek ALSA SoC AFE platform driver
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: Koro Chen <koro.chen@mediatek.com>
6 * Sascha Hauer <s.hauer@pengutronix.de>
7 * Hidalgo Huang <hidalgo.huang@mediatek.com>
8 * Ir Lian <ir.lian@mediatek.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 and
12 * only version 2 as published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/delay.h>
21 #include <linux/module.h>
23 #include <linux/of_address.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/soc.h>
26 #include "mtk-afe-common.h"
28 /*****************************************************************************
29 * R E G I S T E R D E F I N I T I O N
30 *****************************************************************************/
31 #define AUDIO_TOP_CON0 0x0000
32 #define AUDIO_TOP_CON1 0x0004
33 #define AFE_DAC_CON0 0x0010
34 #define AFE_DAC_CON1 0x0014
35 #define AFE_I2S_CON1 0x0034
36 #define AFE_I2S_CON2 0x0038
37 #define AFE_CONN_24BIT 0x006c
39 #define AFE_CONN1 0x0024
40 #define AFE_CONN2 0x0028
41 #define AFE_CONN7 0x0460
42 #define AFE_CONN8 0x0464
43 #define AFE_HDMI_CONN0 0x0390
45 /* Memory interface */
46 #define AFE_DL1_BASE 0x0040
47 #define AFE_DL1_CUR 0x0044
48 #define AFE_DL1_END 0x0048
49 #define AFE_DL2_BASE 0x0050
50 #define AFE_DL2_CUR 0x0054
51 #define AFE_AWB_BASE 0x0070
52 #define AFE_AWB_CUR 0x007c
53 #define AFE_VUL_BASE 0x0080
54 #define AFE_VUL_CUR 0x008c
55 #define AFE_VUL_END 0x0088
56 #define AFE_DAI_BASE 0x0090
57 #define AFE_DAI_CUR 0x009c
58 #define AFE_MOD_PCM_BASE 0x0330
59 #define AFE_MOD_PCM_CUR 0x033c
60 #define AFE_HDMI_OUT_BASE 0x0374
61 #define AFE_HDMI_OUT_CUR 0x0378
62 #define AFE_HDMI_OUT_END 0x037c
64 #define AFE_ADDA2_TOP_CON0 0x0600
66 #define AFE_HDMI_OUT_CON0 0x0370
68 #define AFE_IRQ_MCU_CON 0x03a0
69 #define AFE_IRQ_STATUS 0x03a4
70 #define AFE_IRQ_CLR 0x03a8
71 #define AFE_IRQ_CNT1 0x03ac
72 #define AFE_IRQ_CNT2 0x03b0
73 #define AFE_IRQ_MCU_EN 0x03b4
74 #define AFE_IRQ_CNT5 0x03bc
75 #define AFE_IRQ_CNT7 0x03dc
77 #define AFE_TDM_CON1 0x0548
78 #define AFE_TDM_CON2 0x054c
80 #define AFE_BASE_END_OFFSET 8
81 #define AFE_IRQ_STATUS_BITS 0xff
83 /* AUDIO_TOP_CON0 (0x0000) */
84 #define AUD_TCON0_PDN_SPDF (0x1 << 21)
85 #define AUD_TCON0_PDN_HDMI (0x1 << 20)
86 #define AUD_TCON0_PDN_24M (0x1 << 9)
87 #define AUD_TCON0_PDN_22M (0x1 << 8)
88 #define AUD_TCON0_PDN_AFE (0x1 << 2)
90 /* AFE_I2S_CON1 (0x0034) */
91 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
92 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
93 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
94 #define AFE_I2S_CON1_EN (0x1 << 0)
96 /* AFE_I2S_CON2 (0x0038) */
97 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
98 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
99 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
100 #define AFE_I2S_CON2_EN (0x1 << 0)
102 /* AFE_CONN_24BIT (0x006c) */
103 #define AFE_CONN_24BIT_O04 (0x1 << 4)
104 #define AFE_CONN_24BIT_O03 (0x1 << 3)
106 /* AFE_HDMI_CONN0 (0x0390) */
107 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
108 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
109 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
110 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
111 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
112 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
113 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
114 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
116 /* AFE_TDM_CON1 (0x0548) */
117 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
118 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
119 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
120 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
121 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
122 #define AFE_TDM_CON1_BCK_INV (0x1 << 1)
123 #define AFE_TDM_CON1_EN (0x1 << 0)
125 enum afe_tdm_ch_start
{
126 AFE_TDM_CH_START_O30_O31
= 0,
127 AFE_TDM_CH_START_O32_O33
,
128 AFE_TDM_CH_START_O34_O35
,
129 AFE_TDM_CH_START_O36_O37
,
133 static const unsigned int mtk_afe_backup_list
[] = {
151 /* address for ioremap audio hardware register */
152 void __iomem
*base_addr
;
154 struct regmap
*regmap
;
155 struct mtk_afe_memif memif
[MTK_AFE_MEMIF_NUM
];
156 struct clk
*clocks
[MTK_CLK_NUM
];
157 unsigned int backup_regs
[ARRAY_SIZE(mtk_afe_backup_list
)];
161 static const struct snd_pcm_hardware mtk_afe_hardware
= {
162 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
163 SNDRV_PCM_INFO_MMAP_VALID
),
164 .buffer_bytes_max
= 256 * 1024,
165 .period_bytes_min
= 512,
166 .period_bytes_max
= 128 * 1024,
172 static snd_pcm_uframes_t mtk_afe_pcm_pointer
173 (struct snd_pcm_substream
*substream
)
175 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
176 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
177 struct mtk_afe_memif
*memif
= &afe
->memif
[rtd
->cpu_dai
->id
];
179 return bytes_to_frames(substream
->runtime
, memif
->hw_ptr
);
182 static const struct snd_pcm_ops mtk_afe_pcm_ops
= {
183 .ioctl
= snd_pcm_lib_ioctl
,
184 .pointer
= mtk_afe_pcm_pointer
,
187 static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime
*rtd
)
190 struct snd_card
*card
= rtd
->card
->snd_card
;
191 struct snd_pcm
*pcm
= rtd
->pcm
;
193 size
= mtk_afe_hardware
.buffer_bytes_max
;
195 return snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
196 card
->dev
, size
, size
);
199 static void mtk_afe_pcm_free(struct snd_pcm
*pcm
)
201 snd_pcm_lib_preallocate_free_for_all(pcm
);
204 static const struct snd_soc_platform_driver mtk_afe_pcm_platform
= {
205 .ops
= &mtk_afe_pcm_ops
,
206 .pcm_new
= mtk_afe_pcm_new
,
207 .pcm_free
= mtk_afe_pcm_free
,
210 struct mtk_afe_rate
{
212 unsigned int regvalue
;
215 static const struct mtk_afe_rate mtk_afe_i2s_rates
[] = {
216 { .rate
= 8000, .regvalue
= 0 },
217 { .rate
= 11025, .regvalue
= 1 },
218 { .rate
= 12000, .regvalue
= 2 },
219 { .rate
= 16000, .regvalue
= 4 },
220 { .rate
= 22050, .regvalue
= 5 },
221 { .rate
= 24000, .regvalue
= 6 },
222 { .rate
= 32000, .regvalue
= 8 },
223 { .rate
= 44100, .regvalue
= 9 },
224 { .rate
= 48000, .regvalue
= 10 },
225 { .rate
= 88000, .regvalue
= 11 },
226 { .rate
= 96000, .regvalue
= 12 },
227 { .rate
= 174000, .regvalue
= 13 },
228 { .rate
= 192000, .regvalue
= 14 },
231 static int mtk_afe_i2s_fs(unsigned int sample_rate
)
235 for (i
= 0; i
< ARRAY_SIZE(mtk_afe_i2s_rates
); i
++)
236 if (mtk_afe_i2s_rates
[i
].rate
== sample_rate
)
237 return mtk_afe_i2s_rates
[i
].regvalue
;
242 static int mtk_afe_set_i2s(struct mtk_afe
*afe
, unsigned int rate
)
245 int fs
= mtk_afe_i2s_fs(rate
);
250 /* from external ADC */
251 regmap_update_bits(afe
->regmap
, AFE_ADDA2_TOP_CON0
, 0x1, 0x1);
254 val
= AFE_I2S_CON2_LOW_JITTER_CLK
|
255 AFE_I2S_CON2_RATE(fs
) |
256 AFE_I2S_CON2_FORMAT_I2S
;
258 regmap_update_bits(afe
->regmap
, AFE_I2S_CON2
, ~AFE_I2S_CON2_EN
, val
);
261 val
= AFE_I2S_CON1_LOW_JITTER_CLK
|
262 AFE_I2S_CON1_RATE(fs
) |
263 AFE_I2S_CON1_FORMAT_I2S
;
265 regmap_update_bits(afe
->regmap
, AFE_I2S_CON1
, ~AFE_I2S_CON1_EN
, val
);
269 static void mtk_afe_set_i2s_enable(struct mtk_afe
*afe
, bool enable
)
273 regmap_read(afe
->regmap
, AFE_I2S_CON2
, &val
);
274 if (!!(val
& AFE_I2S_CON2_EN
) == enable
)
275 return; /* must skip soft reset */
277 /* I2S soft reset begin */
278 regmap_update_bits(afe
->regmap
, AUDIO_TOP_CON1
, 0x4, 0x4);
281 regmap_update_bits(afe
->regmap
, AFE_I2S_CON2
, 0x1, enable
);
284 regmap_update_bits(afe
->regmap
, AFE_I2S_CON1
, 0x1, enable
);
286 /* I2S soft reset end */
288 regmap_update_bits(afe
->regmap
, AUDIO_TOP_CON1
, 0x4, 0);
291 static int mtk_afe_dais_enable_clks(struct mtk_afe
*afe
,
292 struct clk
*m_ck
, struct clk
*b_ck
)
297 ret
= clk_prepare_enable(m_ck
);
299 dev_err(afe
->dev
, "Failed to enable m_ck\n");
302 regmap_update_bits(afe
->regmap
, AUDIO_TOP_CON0
,
303 AUD_TCON0_PDN_22M
| AUD_TCON0_PDN_24M
, 0);
307 ret
= clk_prepare_enable(b_ck
);
309 dev_err(afe
->dev
, "Failed to enable b_ck\n");
316 static int mtk_afe_dais_set_clks(struct mtk_afe
*afe
,
317 struct clk
*m_ck
, unsigned int mck_rate
,
318 struct clk
*b_ck
, unsigned int bck_rate
)
323 ret
= clk_set_rate(m_ck
, mck_rate
);
325 dev_err(afe
->dev
, "Failed to set m_ck rate\n");
331 ret
= clk_set_rate(b_ck
, bck_rate
);
333 dev_err(afe
->dev
, "Failed to set b_ck rate\n");
340 static void mtk_afe_dais_disable_clks(struct mtk_afe
*afe
,
341 struct clk
*m_ck
, struct clk
*b_ck
)
344 regmap_update_bits(afe
->regmap
, AUDIO_TOP_CON0
,
345 AUD_TCON0_PDN_22M
| AUD_TCON0_PDN_24M
,
346 AUD_TCON0_PDN_22M
| AUD_TCON0_PDN_24M
);
347 clk_disable_unprepare(m_ck
);
350 clk_disable_unprepare(b_ck
);
353 static int mtk_afe_i2s_startup(struct snd_pcm_substream
*substream
,
354 struct snd_soc_dai
*dai
)
356 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
357 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
362 mtk_afe_dais_enable_clks(afe
, afe
->clocks
[MTK_CLK_I2S1_M
], NULL
);
366 static void mtk_afe_i2s_shutdown(struct snd_pcm_substream
*substream
,
367 struct snd_soc_dai
*dai
)
369 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
370 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
375 mtk_afe_set_i2s_enable(afe
, false);
376 mtk_afe_dais_disable_clks(afe
, afe
->clocks
[MTK_CLK_I2S1_M
], NULL
);
379 regmap_update_bits(afe
->regmap
, AFE_DAC_CON0
, 0x1, 0);
382 static int mtk_afe_i2s_prepare(struct snd_pcm_substream
*substream
,
383 struct snd_soc_dai
*dai
)
385 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
386 struct snd_pcm_runtime
* const runtime
= substream
->runtime
;
387 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
390 mtk_afe_dais_set_clks(afe
,
391 afe
->clocks
[MTK_CLK_I2S1_M
], runtime
->rate
* 256,
394 ret
= mtk_afe_set_i2s(afe
, substream
->runtime
->rate
);
398 mtk_afe_set_i2s_enable(afe
, true);
403 static int mtk_afe_hdmi_startup(struct snd_pcm_substream
*substream
,
404 struct snd_soc_dai
*dai
)
406 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
407 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
412 mtk_afe_dais_enable_clks(afe
, afe
->clocks
[MTK_CLK_I2S3_M
],
413 afe
->clocks
[MTK_CLK_I2S3_B
]);
417 static void mtk_afe_hdmi_shutdown(struct snd_pcm_substream
*substream
,
418 struct snd_soc_dai
*dai
)
420 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
421 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
426 mtk_afe_dais_disable_clks(afe
, afe
->clocks
[MTK_CLK_I2S3_M
],
427 afe
->clocks
[MTK_CLK_I2S3_B
]);
430 regmap_update_bits(afe
->regmap
, AFE_DAC_CON0
, 0x1, 0);
433 static int mtk_afe_hdmi_prepare(struct snd_pcm_substream
*substream
,
434 struct snd_soc_dai
*dai
)
436 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
437 struct snd_pcm_runtime
* const runtime
= substream
->runtime
;
438 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
441 mtk_afe_dais_set_clks(afe
,
442 afe
->clocks
[MTK_CLK_I2S3_M
], runtime
->rate
* 128,
443 afe
->clocks
[MTK_CLK_I2S3_B
],
444 runtime
->rate
* runtime
->channels
* 32);
446 val
= AFE_TDM_CON1_BCK_INV
|
447 AFE_TDM_CON1_1_BCK_DELAY
|
448 AFE_TDM_CON1_MSB_ALIGNED
| /* I2S mode */
449 AFE_TDM_CON1_WLEN_32BIT
|
450 AFE_TDM_CON1_32_BCK_CYCLES
|
451 AFE_TDM_CON1_LRCK_WIDTH(32);
452 regmap_update_bits(afe
->regmap
, AFE_TDM_CON1
, ~AFE_TDM_CON1_EN
, val
);
454 /* set tdm2 config */
455 switch (runtime
->channels
) {
458 val
= AFE_TDM_CH_START_O30_O31
;
459 val
|= (AFE_TDM_CH_ZERO
<< 4);
460 val
|= (AFE_TDM_CH_ZERO
<< 8);
461 val
|= (AFE_TDM_CH_ZERO
<< 12);
465 val
= AFE_TDM_CH_START_O30_O31
;
466 val
|= (AFE_TDM_CH_START_O32_O33
<< 4);
467 val
|= (AFE_TDM_CH_ZERO
<< 8);
468 val
|= (AFE_TDM_CH_ZERO
<< 12);
472 val
= AFE_TDM_CH_START_O30_O31
;
473 val
|= (AFE_TDM_CH_START_O32_O33
<< 4);
474 val
|= (AFE_TDM_CH_START_O34_O35
<< 8);
475 val
|= (AFE_TDM_CH_ZERO
<< 12);
479 val
= AFE_TDM_CH_START_O30_O31
;
480 val
|= (AFE_TDM_CH_START_O32_O33
<< 4);
481 val
|= (AFE_TDM_CH_START_O34_O35
<< 8);
482 val
|= (AFE_TDM_CH_START_O36_O37
<< 12);
487 regmap_update_bits(afe
->regmap
, AFE_TDM_CON2
, 0x0000ffff, val
);
489 regmap_update_bits(afe
->regmap
, AFE_HDMI_OUT_CON0
,
490 0x000000f0, runtime
->channels
<< 4);
494 static int mtk_afe_hdmi_trigger(struct snd_pcm_substream
*substream
, int cmd
,
495 struct snd_soc_dai
*dai
)
497 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
498 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
500 dev_info(afe
->dev
, "%s cmd=%d %s\n", __func__
, cmd
, dai
->name
);
503 case SNDRV_PCM_TRIGGER_START
:
504 case SNDRV_PCM_TRIGGER_RESUME
:
505 regmap_update_bits(afe
->regmap
, AUDIO_TOP_CON0
,
506 AUD_TCON0_PDN_HDMI
| AUD_TCON0_PDN_SPDF
, 0);
508 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
509 regmap_write(afe
->regmap
, AFE_HDMI_CONN0
,
510 AFE_HDMI_CONN0_O30_I30
| AFE_HDMI_CONN0_O31_I31
|
511 AFE_HDMI_CONN0_O32_I34
| AFE_HDMI_CONN0_O33_I35
|
512 AFE_HDMI_CONN0_O34_I32
| AFE_HDMI_CONN0_O35_I33
|
513 AFE_HDMI_CONN0_O36_I36
| AFE_HDMI_CONN0_O37_I37
);
515 /* enable Out control */
516 regmap_update_bits(afe
->regmap
, AFE_HDMI_OUT_CON0
, 0x1, 0x1);
519 regmap_update_bits(afe
->regmap
, AFE_TDM_CON1
, 0x1, 0x1);
522 case SNDRV_PCM_TRIGGER_STOP
:
523 case SNDRV_PCM_TRIGGER_SUSPEND
:
525 regmap_update_bits(afe
->regmap
, AFE_TDM_CON1
, 0x1, 0);
527 /* disable Out control */
528 regmap_update_bits(afe
->regmap
, AFE_HDMI_OUT_CON0
, 0x1, 0);
530 regmap_update_bits(afe
->regmap
, AUDIO_TOP_CON0
,
531 AUD_TCON0_PDN_HDMI
| AUD_TCON0_PDN_SPDF
,
532 AUD_TCON0_PDN_HDMI
| AUD_TCON0_PDN_SPDF
);
540 static int mtk_afe_dais_startup(struct snd_pcm_substream
*substream
,
541 struct snd_soc_dai
*dai
)
543 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
544 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
545 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
546 struct mtk_afe_memif
*memif
= &afe
->memif
[rtd
->cpu_dai
->id
];
549 memif
->substream
= substream
;
551 snd_soc_set_runtime_hwparams(substream
, &mtk_afe_hardware
);
552 ret
= snd_pcm_hw_constraint_integer(runtime
,
553 SNDRV_PCM_HW_PARAM_PERIODS
);
555 dev_err(afe
->dev
, "snd_pcm_hw_constraint_integer failed\n");
559 static void mtk_afe_dais_shutdown(struct snd_pcm_substream
*substream
,
560 struct snd_soc_dai
*dai
)
562 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
563 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
564 struct mtk_afe_memif
*memif
= &afe
->memif
[rtd
->cpu_dai
->id
];
566 memif
->substream
= NULL
;
569 static int mtk_afe_dais_hw_params(struct snd_pcm_substream
*substream
,
570 struct snd_pcm_hw_params
*params
,
571 struct snd_soc_dai
*dai
)
573 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
574 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
575 struct mtk_afe_memif
*memif
= &afe
->memif
[rtd
->cpu_dai
->id
];
579 "%s period = %u, rate= %u, channels=%u\n",
580 __func__
, params_period_size(params
), params_rate(params
),
581 params_channels(params
));
583 ret
= snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(params
));
587 memif
->phys_buf_addr
= substream
->runtime
->dma_addr
;
588 memif
->buffer_size
= substream
->runtime
->dma_bytes
;
592 regmap_write(afe
->regmap
,
593 memif
->data
->reg_ofs_base
, memif
->phys_buf_addr
);
595 regmap_write(afe
->regmap
,
596 memif
->data
->reg_ofs_base
+ AFE_BASE_END_OFFSET
,
597 memif
->phys_buf_addr
+ memif
->buffer_size
- 1);
600 if (memif
->data
->mono_shift
>= 0) {
601 unsigned int mono
= (params_channels(params
) == 1) ? 1 : 0;
603 regmap_update_bits(afe
->regmap
, AFE_DAC_CON1
,
604 1 << memif
->data
->mono_shift
,
605 mono
<< memif
->data
->mono_shift
);
609 if (memif
->data
->fs_shift
< 0)
611 if (memif
->data
->id
== MTK_AFE_MEMIF_DAI
||
612 memif
->data
->id
== MTK_AFE_MEMIF_MOD_DAI
) {
615 switch (params_rate(params
)) {
629 if (memif
->data
->id
== MTK_AFE_MEMIF_DAI
)
630 regmap_update_bits(afe
->regmap
, AFE_DAC_CON0
,
631 0x3 << memif
->data
->fs_shift
,
632 val
<< memif
->data
->fs_shift
);
634 regmap_update_bits(afe
->regmap
, AFE_DAC_CON1
,
635 0x3 << memif
->data
->fs_shift
,
636 val
<< memif
->data
->fs_shift
);
639 int fs
= mtk_afe_i2s_fs(params_rate(params
));
644 regmap_update_bits(afe
->regmap
, AFE_DAC_CON1
,
645 0xf << memif
->data
->fs_shift
,
646 fs
<< memif
->data
->fs_shift
);
652 static int mtk_afe_dais_hw_free(struct snd_pcm_substream
*substream
,
653 struct snd_soc_dai
*dai
)
655 return snd_pcm_lib_free_pages(substream
);
658 static int mtk_afe_dais_prepare(struct snd_pcm_substream
*substream
,
659 struct snd_soc_dai
*dai
)
661 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
662 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
665 regmap_update_bits(afe
->regmap
, AFE_DAC_CON0
, 0x1, 0x1);
669 static int mtk_afe_dais_trigger(struct snd_pcm_substream
*substream
, int cmd
,
670 struct snd_soc_dai
*dai
)
672 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
673 struct snd_pcm_runtime
* const runtime
= substream
->runtime
;
674 struct mtk_afe
*afe
= snd_soc_platform_get_drvdata(rtd
->platform
);
675 struct mtk_afe_memif
*memif
= &afe
->memif
[rtd
->cpu_dai
->id
];
676 unsigned int counter
= runtime
->period_size
;
678 dev_info(afe
->dev
, "%s %s cmd=%d\n", __func__
, memif
->data
->name
, cmd
);
681 case SNDRV_PCM_TRIGGER_START
:
682 case SNDRV_PCM_TRIGGER_RESUME
:
683 if (memif
->data
->enable_shift
>= 0)
684 regmap_update_bits(afe
->regmap
, AFE_DAC_CON0
,
685 1 << memif
->data
->enable_shift
,
686 1 << memif
->data
->enable_shift
);
688 /* set irq counter */
689 regmap_update_bits(afe
->regmap
,
690 memif
->data
->irq_reg_cnt
,
691 0x3ffff << memif
->data
->irq_cnt_shift
,
692 counter
<< memif
->data
->irq_cnt_shift
);
695 if (memif
->data
->irq_fs_shift
>= 0) {
696 int fs
= mtk_afe_i2s_fs(runtime
->rate
);
701 regmap_update_bits(afe
->regmap
,
703 0xf << memif
->data
->irq_fs_shift
,
704 fs
<< memif
->data
->irq_fs_shift
);
706 /* enable interrupt */
707 regmap_update_bits(afe
->regmap
, AFE_IRQ_MCU_CON
,
708 1 << memif
->data
->irq_en_shift
,
709 1 << memif
->data
->irq_en_shift
);
712 case SNDRV_PCM_TRIGGER_STOP
:
713 case SNDRV_PCM_TRIGGER_SUSPEND
:
714 if (memif
->data
->enable_shift
>= 0)
715 regmap_update_bits(afe
->regmap
, AFE_DAC_CON0
,
716 1 << memif
->data
->enable_shift
, 0);
717 /* disable interrupt */
718 regmap_update_bits(afe
->regmap
, AFE_IRQ_MCU_CON
,
719 1 << memif
->data
->irq_en_shift
,
720 0 << memif
->data
->irq_en_shift
);
721 /* and clear pending IRQ */
722 regmap_write(afe
->regmap
, AFE_IRQ_CLR
,
723 1 << memif
->data
->irq_clr_shift
);
732 static const struct snd_soc_dai_ops mtk_afe_dai_ops
= {
733 .startup
= mtk_afe_dais_startup
,
734 .shutdown
= mtk_afe_dais_shutdown
,
735 .hw_params
= mtk_afe_dais_hw_params
,
736 .hw_free
= mtk_afe_dais_hw_free
,
737 .prepare
= mtk_afe_dais_prepare
,
738 .trigger
= mtk_afe_dais_trigger
,
742 static const struct snd_soc_dai_ops mtk_afe_i2s_ops
= {
743 .startup
= mtk_afe_i2s_startup
,
744 .shutdown
= mtk_afe_i2s_shutdown
,
745 .prepare
= mtk_afe_i2s_prepare
,
748 static const struct snd_soc_dai_ops mtk_afe_hdmi_ops
= {
749 .startup
= mtk_afe_hdmi_startup
,
750 .shutdown
= mtk_afe_hdmi_shutdown
,
751 .prepare
= mtk_afe_hdmi_prepare
,
752 .trigger
= mtk_afe_hdmi_trigger
,
756 static int mtk_afe_runtime_suspend(struct device
*dev
);
757 static int mtk_afe_runtime_resume(struct device
*dev
);
759 static int mtk_afe_dai_suspend(struct snd_soc_dai
*dai
)
761 struct mtk_afe
*afe
= snd_soc_dai_get_drvdata(dai
);
764 dev_dbg(afe
->dev
, "%s\n", __func__
);
765 if (pm_runtime_status_suspended(afe
->dev
) || afe
->suspended
)
768 for (i
= 0; i
< ARRAY_SIZE(mtk_afe_backup_list
); i
++)
769 regmap_read(afe
->regmap
, mtk_afe_backup_list
[i
],
770 &afe
->backup_regs
[i
]);
772 afe
->suspended
= true;
773 mtk_afe_runtime_suspend(afe
->dev
);
777 static int mtk_afe_dai_resume(struct snd_soc_dai
*dai
)
779 struct mtk_afe
*afe
= snd_soc_dai_get_drvdata(dai
);
782 dev_dbg(afe
->dev
, "%s\n", __func__
);
783 if (pm_runtime_status_suspended(afe
->dev
) || !afe
->suspended
)
786 mtk_afe_runtime_resume(afe
->dev
);
788 for (i
= 0; i
< ARRAY_SIZE(mtk_afe_backup_list
); i
++)
789 regmap_write(afe
->regmap
, mtk_afe_backup_list
[i
],
790 afe
->backup_regs
[i
]);
792 afe
->suspended
= false;
796 static struct snd_soc_dai_driver mtk_afe_pcm_dais
[] = {
797 /* FE DAIs: memory intefaces to CPU */
799 .name
= "DL1", /* downlink 1 */
800 .id
= MTK_AFE_MEMIF_DL1
,
801 .suspend
= mtk_afe_dai_suspend
,
802 .resume
= mtk_afe_dai_resume
,
804 .stream_name
= "DL1",
807 .rates
= SNDRV_PCM_RATE_8000_48000
,
808 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
810 .ops
= &mtk_afe_dai_ops
,
812 .name
= "VUL", /* voice uplink */
813 .id
= MTK_AFE_MEMIF_VUL
,
814 .suspend
= mtk_afe_dai_suspend
,
815 .resume
= mtk_afe_dai_resume
,
817 .stream_name
= "VUL",
820 .rates
= SNDRV_PCM_RATE_8000_48000
,
821 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
823 .ops
= &mtk_afe_dai_ops
,
827 .id
= MTK_AFE_IO_I2S
,
829 .stream_name
= "I2S Playback",
832 .rates
= SNDRV_PCM_RATE_8000_48000
,
833 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
836 .stream_name
= "I2S Capture",
839 .rates
= SNDRV_PCM_RATE_8000_48000
,
840 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
842 .ops
= &mtk_afe_i2s_ops
,
843 .symmetric_rates
= 1,
847 static struct snd_soc_dai_driver mtk_afe_hdmi_dais
[] = {
851 .id
= MTK_AFE_MEMIF_HDMI
,
852 .suspend
= mtk_afe_dai_suspend
,
853 .resume
= mtk_afe_dai_resume
,
855 .stream_name
= "HDMI",
858 .rates
= SNDRV_PCM_RATE_32000
| SNDRV_PCM_RATE_44100
|
859 SNDRV_PCM_RATE_48000
| SNDRV_PCM_RATE_88200
|
860 SNDRV_PCM_RATE_96000
| SNDRV_PCM_RATE_176400
|
861 SNDRV_PCM_RATE_192000
,
862 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
864 .ops
= &mtk_afe_dai_ops
,
868 .id
= MTK_AFE_IO_HDMI
,
870 .stream_name
= "HDMIO Playback",
873 .rates
= SNDRV_PCM_RATE_32000
| SNDRV_PCM_RATE_44100
|
874 SNDRV_PCM_RATE_48000
| SNDRV_PCM_RATE_88200
|
875 SNDRV_PCM_RATE_96000
| SNDRV_PCM_RATE_176400
|
876 SNDRV_PCM_RATE_192000
,
877 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
879 .ops
= &mtk_afe_hdmi_ops
,
883 static const struct snd_kcontrol_new mtk_afe_o03_mix
[] = {
884 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1
, 21, 1, 0),
887 static const struct snd_kcontrol_new mtk_afe_o04_mix
[] = {
888 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2
, 6, 1, 0),
891 static const struct snd_kcontrol_new mtk_afe_o09_mix
[] = {
892 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7
, 30, 1, 0),
895 static const struct snd_kcontrol_new mtk_afe_o10_mix
[] = {
896 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8
, 0, 1, 0),
899 static const struct snd_soc_dapm_widget mtk_afe_pcm_widgets
[] = {
900 /* inter-connections */
901 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM
, 0, 0, NULL
, 0),
902 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM
, 0, 0, NULL
, 0),
903 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM
, 0, 0, NULL
, 0),
904 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM
, 0, 0, NULL
, 0),
906 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM
, 0, 0,
907 mtk_afe_o03_mix
, ARRAY_SIZE(mtk_afe_o03_mix
)),
908 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM
, 0, 0,
909 mtk_afe_o04_mix
, ARRAY_SIZE(mtk_afe_o04_mix
)),
910 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM
, 0, 0,
911 mtk_afe_o09_mix
, ARRAY_SIZE(mtk_afe_o09_mix
)),
912 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM
, 0, 0,
913 mtk_afe_o10_mix
, ARRAY_SIZE(mtk_afe_o10_mix
)),
916 static const struct snd_soc_dapm_route mtk_afe_pcm_routes
[] = {
917 {"I05", NULL
, "DL1"},
918 {"I06", NULL
, "DL1"},
919 {"I2S Playback", NULL
, "O03"},
920 {"I2S Playback", NULL
, "O04"},
921 {"VUL", NULL
, "O09"},
922 {"VUL", NULL
, "O10"},
923 {"I17", NULL
, "I2S Capture"},
924 {"I18", NULL
, "I2S Capture"},
925 { "O03", "I05 Switch", "I05" },
926 { "O04", "I06 Switch", "I06" },
927 { "O09", "I17 Switch", "I17" },
928 { "O10", "I18 Switch", "I18" },
931 static const struct snd_soc_dapm_route mtk_afe_hdmi_routes
[] = {
932 {"HDMIO Playback", NULL
, "HDMI"},
935 static const struct snd_soc_component_driver mtk_afe_pcm_dai_component
= {
936 .name
= "mtk-afe-pcm-dai",
937 .dapm_widgets
= mtk_afe_pcm_widgets
,
938 .num_dapm_widgets
= ARRAY_SIZE(mtk_afe_pcm_widgets
),
939 .dapm_routes
= mtk_afe_pcm_routes
,
940 .num_dapm_routes
= ARRAY_SIZE(mtk_afe_pcm_routes
),
943 static const struct snd_soc_component_driver mtk_afe_hdmi_dai_component
= {
944 .name
= "mtk-afe-hdmi-dai",
945 .dapm_routes
= mtk_afe_hdmi_routes
,
946 .num_dapm_routes
= ARRAY_SIZE(mtk_afe_hdmi_routes
),
949 static const char *aud_clks
[MTK_CLK_NUM
] = {
950 [MTK_CLK_INFRASYS_AUD
] = "infra_sys_audio_clk",
951 [MTK_CLK_TOP_PDN_AUD
] = "top_pdn_audio",
952 [MTK_CLK_TOP_PDN_AUD_BUS
] = "top_pdn_aud_intbus",
953 [MTK_CLK_I2S0_M
] = "i2s0_m",
954 [MTK_CLK_I2S1_M
] = "i2s1_m",
955 [MTK_CLK_I2S2_M
] = "i2s2_m",
956 [MTK_CLK_I2S3_M
] = "i2s3_m",
957 [MTK_CLK_I2S3_B
] = "i2s3_b",
958 [MTK_CLK_BCK0
] = "bck0",
959 [MTK_CLK_BCK1
] = "bck1",
962 static const struct mtk_afe_memif_data memif_data
[MTK_AFE_MEMIF_NUM
] = {
965 .id
= MTK_AFE_MEMIF_DL1
,
966 .reg_ofs_base
= AFE_DL1_BASE
,
967 .reg_ofs_cur
= AFE_DL1_CUR
,
971 .irq_reg_cnt
= AFE_IRQ_CNT1
,
978 .id
= MTK_AFE_MEMIF_DL2
,
979 .reg_ofs_base
= AFE_DL2_BASE
,
980 .reg_ofs_cur
= AFE_DL2_CUR
,
984 .irq_reg_cnt
= AFE_IRQ_CNT1
,
991 .id
= MTK_AFE_MEMIF_VUL
,
992 .reg_ofs_base
= AFE_VUL_BASE
,
993 .reg_ofs_cur
= AFE_VUL_CUR
,
997 .irq_reg_cnt
= AFE_IRQ_CNT2
,
1004 .id
= MTK_AFE_MEMIF_DAI
,
1005 .reg_ofs_base
= AFE_DAI_BASE
,
1006 .reg_ofs_cur
= AFE_DAI_CUR
,
1010 .irq_reg_cnt
= AFE_IRQ_CNT2
,
1011 .irq_cnt_shift
= 20,
1017 .id
= MTK_AFE_MEMIF_AWB
,
1018 .reg_ofs_base
= AFE_AWB_BASE
,
1019 .reg_ofs_cur
= AFE_AWB_CUR
,
1023 .irq_reg_cnt
= AFE_IRQ_CNT7
,
1030 .id
= MTK_AFE_MEMIF_MOD_DAI
,
1031 .reg_ofs_base
= AFE_MOD_PCM_BASE
,
1032 .reg_ofs_cur
= AFE_MOD_PCM_CUR
,
1036 .irq_reg_cnt
= AFE_IRQ_CNT2
,
1037 .irq_cnt_shift
= 20,
1043 .id
= MTK_AFE_MEMIF_HDMI
,
1044 .reg_ofs_base
= AFE_HDMI_OUT_BASE
,
1045 .reg_ofs_cur
= AFE_HDMI_OUT_CUR
,
1049 .irq_reg_cnt
= AFE_IRQ_CNT5
,
1057 static const struct regmap_config mtk_afe_regmap_config
= {
1061 .max_register
= AFE_ADDA2_TOP_CON0
,
1062 .cache_type
= REGCACHE_NONE
,
1065 static irqreturn_t
mtk_afe_irq_handler(int irq
, void *dev_id
)
1067 struct mtk_afe
*afe
= dev_id
;
1068 unsigned int reg_value
, hw_ptr
;
1071 ret
= regmap_read(afe
->regmap
, AFE_IRQ_STATUS
, ®_value
);
1073 dev_err(afe
->dev
, "%s irq status err\n", __func__
);
1074 reg_value
= AFE_IRQ_STATUS_BITS
;
1078 for (i
= 0; i
< MTK_AFE_MEMIF_NUM
; i
++) {
1079 struct mtk_afe_memif
*memif
= &afe
->memif
[i
];
1081 if (!(reg_value
& (1 << memif
->data
->irq_clr_shift
)))
1084 ret
= regmap_read(afe
->regmap
, memif
->data
->reg_ofs_cur
,
1086 if (ret
|| hw_ptr
== 0) {
1087 dev_err(afe
->dev
, "%s hw_ptr err\n", __func__
);
1088 hw_ptr
= memif
->phys_buf_addr
;
1090 memif
->hw_ptr
= hw_ptr
- memif
->phys_buf_addr
;
1091 snd_pcm_period_elapsed(memif
->substream
);
1096 regmap_write(afe
->regmap
, AFE_IRQ_CLR
, reg_value
& AFE_IRQ_STATUS_BITS
);
1101 static int mtk_afe_runtime_suspend(struct device
*dev
)
1103 struct mtk_afe
*afe
= dev_get_drvdata(dev
);
1105 /* disable AFE clk */
1106 regmap_update_bits(afe
->regmap
, AUDIO_TOP_CON0
,
1107 AUD_TCON0_PDN_AFE
, AUD_TCON0_PDN_AFE
);
1109 clk_disable_unprepare(afe
->clocks
[MTK_CLK_BCK0
]);
1110 clk_disable_unprepare(afe
->clocks
[MTK_CLK_BCK1
]);
1111 clk_disable_unprepare(afe
->clocks
[MTK_CLK_TOP_PDN_AUD
]);
1112 clk_disable_unprepare(afe
->clocks
[MTK_CLK_TOP_PDN_AUD_BUS
]);
1113 clk_disable_unprepare(afe
->clocks
[MTK_CLK_INFRASYS_AUD
]);
1117 static int mtk_afe_runtime_resume(struct device
*dev
)
1119 struct mtk_afe
*afe
= dev_get_drvdata(dev
);
1122 ret
= clk_prepare_enable(afe
->clocks
[MTK_CLK_INFRASYS_AUD
]);
1126 ret
= clk_prepare_enable(afe
->clocks
[MTK_CLK_TOP_PDN_AUD_BUS
]);
1130 ret
= clk_prepare_enable(afe
->clocks
[MTK_CLK_TOP_PDN_AUD
]);
1132 goto err_top_aud_bus
;
1134 ret
= clk_prepare_enable(afe
->clocks
[MTK_CLK_BCK0
]);
1138 ret
= clk_prepare_enable(afe
->clocks
[MTK_CLK_BCK1
]);
1142 /* enable AFE clk */
1143 regmap_update_bits(afe
->regmap
, AUDIO_TOP_CON0
, AUD_TCON0_PDN_AFE
, 0);
1145 /* set O3/O4 16bits */
1146 regmap_update_bits(afe
->regmap
, AFE_CONN_24BIT
,
1147 AFE_CONN_24BIT_O03
| AFE_CONN_24BIT_O04
, 0);
1149 /* unmask all IRQs */
1150 regmap_update_bits(afe
->regmap
, AFE_IRQ_MCU_EN
, 0xff, 0xff);
1154 clk_disable_unprepare(afe
->clocks
[MTK_CLK_BCK0
]);
1156 clk_disable_unprepare(afe
->clocks
[MTK_CLK_TOP_PDN_AUD
]);
1158 clk_disable_unprepare(afe
->clocks
[MTK_CLK_TOP_PDN_AUD_BUS
]);
1160 clk_disable_unprepare(afe
->clocks
[MTK_CLK_INFRASYS_AUD
]);
1164 static int mtk_afe_init_audio_clk(struct mtk_afe
*afe
)
1168 for (i
= 0; i
< ARRAY_SIZE(aud_clks
); i
++) {
1169 afe
->clocks
[i
] = devm_clk_get(afe
->dev
, aud_clks
[i
]);
1170 if (IS_ERR(afe
->clocks
[i
])) {
1171 dev_err(afe
->dev
, "%s devm_clk_get %s fail\n",
1172 __func__
, aud_clks
[i
]);
1173 return PTR_ERR(afe
->clocks
[i
]);
1176 clk_set_rate(afe
->clocks
[MTK_CLK_BCK0
], 22579200); /* 22M */
1177 clk_set_rate(afe
->clocks
[MTK_CLK_BCK1
], 24576000); /* 24M */
1181 static int mtk_afe_pcm_dev_probe(struct platform_device
*pdev
)
1184 unsigned int irq_id
;
1185 struct mtk_afe
*afe
;
1186 struct resource
*res
;
1188 afe
= devm_kzalloc(&pdev
->dev
, sizeof(*afe
), GFP_KERNEL
);
1192 afe
->dev
= &pdev
->dev
;
1194 irq_id
= platform_get_irq(pdev
, 0);
1196 dev_err(afe
->dev
, "np %s no irq\n", afe
->dev
->of_node
->name
);
1199 ret
= devm_request_irq(afe
->dev
, irq_id
, mtk_afe_irq_handler
,
1200 0, "Afe_ISR_Handle", (void *)afe
);
1202 dev_err(afe
->dev
, "could not request_irq\n");
1206 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1207 afe
->base_addr
= devm_ioremap_resource(&pdev
->dev
, res
);
1208 if (IS_ERR(afe
->base_addr
))
1209 return PTR_ERR(afe
->base_addr
);
1211 afe
->regmap
= devm_regmap_init_mmio(&pdev
->dev
, afe
->base_addr
,
1212 &mtk_afe_regmap_config
);
1213 if (IS_ERR(afe
->regmap
))
1214 return PTR_ERR(afe
->regmap
);
1216 /* initial audio related clock */
1217 ret
= mtk_afe_init_audio_clk(afe
);
1219 dev_err(afe
->dev
, "mtk_afe_init_audio_clk fail\n");
1223 for (i
= 0; i
< MTK_AFE_MEMIF_NUM
; i
++)
1224 afe
->memif
[i
].data
= &memif_data
[i
];
1226 platform_set_drvdata(pdev
, afe
);
1228 pm_runtime_enable(&pdev
->dev
);
1229 if (!pm_runtime_enabled(&pdev
->dev
)) {
1230 ret
= mtk_afe_runtime_resume(&pdev
->dev
);
1232 goto err_pm_disable
;
1235 ret
= snd_soc_register_platform(&pdev
->dev
, &mtk_afe_pcm_platform
);
1237 goto err_pm_disable
;
1239 ret
= snd_soc_register_component(&pdev
->dev
,
1240 &mtk_afe_pcm_dai_component
,
1242 ARRAY_SIZE(mtk_afe_pcm_dais
));
1246 ret
= snd_soc_register_component(&pdev
->dev
,
1247 &mtk_afe_hdmi_dai_component
,
1249 ARRAY_SIZE(mtk_afe_hdmi_dais
));
1253 dev_info(&pdev
->dev
, "MTK AFE driver initialized.\n");
1257 snd_soc_unregister_component(&pdev
->dev
);
1259 snd_soc_unregister_platform(&pdev
->dev
);
1261 pm_runtime_disable(&pdev
->dev
);
1265 static int mtk_afe_pcm_dev_remove(struct platform_device
*pdev
)
1267 pm_runtime_disable(&pdev
->dev
);
1268 if (!pm_runtime_status_suspended(&pdev
->dev
))
1269 mtk_afe_runtime_suspend(&pdev
->dev
);
1270 snd_soc_unregister_component(&pdev
->dev
);
1271 snd_soc_unregister_platform(&pdev
->dev
);
1275 static const struct of_device_id mtk_afe_pcm_dt_match
[] = {
1276 { .compatible
= "mediatek,mt8173-afe-pcm", },
1279 MODULE_DEVICE_TABLE(of
, mtk_afe_pcm_dt_match
);
1281 static const struct dev_pm_ops mtk_afe_pm_ops
= {
1282 SET_RUNTIME_PM_OPS(mtk_afe_runtime_suspend
, mtk_afe_runtime_resume
,
1286 static struct platform_driver mtk_afe_pcm_driver
= {
1288 .name
= "mtk-afe-pcm",
1289 .of_match_table
= mtk_afe_pcm_dt_match
,
1290 .pm
= &mtk_afe_pm_ops
,
1292 .probe
= mtk_afe_pcm_dev_probe
,
1293 .remove
= mtk_afe_pcm_dev_remove
,
1296 module_platform_driver(mtk_afe_pcm_driver
);
1298 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1299 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1300 MODULE_LICENSE("GPL v2");