2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/module.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/time.h>
29 #include <linux/fsl/mxs-dma.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/soc.h>
35 #include <sound/saif.h>
36 #include <asm/mach-types.h>
37 #include <mach/hardware.h>
42 static struct mxs_saif
*mxs_saif
[2];
45 * SAIF is a little different with other normal SOC DAIs on clock using.
47 * For MXS, two SAIF modules are instantiated on-chip.
48 * Each SAIF has a set of clock pins and can be operating in master
49 * mode simultaneously if they are connected to different off-chip codecs.
50 * Also, one of the two SAIFs can master or drive the clock pins while the
51 * other SAIF, in slave mode, receives clocking from the master SAIF.
52 * This also means that both SAIFs must operate at the same sample rate.
54 * We abstract this as each saif has a master, the master could be
55 * himself or other saifs. In the generic saif driver, saif does not need
56 * to know the different clkmux. Saif only needs to know who is his master
57 * and operating his master to generate the proper clock rate for him.
58 * The master id is provided in mach-specific layer according to different
62 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
63 int clk_id
, unsigned int freq
, int dir
)
65 struct mxs_saif
*saif
= snd_soc_dai_get_drvdata(cpu_dai
);
78 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
79 * is provided by other SAIF, we provide a interface here to get its master
81 * Note that the master could be himself.
83 static inline struct mxs_saif
*mxs_saif_get_master(struct mxs_saif
* saif
)
85 return mxs_saif
[saif
->master_id
];
89 * Set SAIF clock and MCLK
91 static int mxs_saif_set_clk(struct mxs_saif
*saif
,
97 struct mxs_saif
*master_saif
;
99 dev_dbg(saif
->dev
, "mclk %d rate %d\n", mclk
, rate
);
101 /* Set master saif to generate proper clock */
102 master_saif
= mxs_saif_get_master(saif
);
106 dev_dbg(saif
->dev
, "master saif%d\n", master_saif
->id
);
108 /* Checking if can playback and capture simutaneously */
109 if (master_saif
->ongoing
&& rate
!= master_saif
->cur_rate
) {
111 "can not change clock, master saif%d(rate %d) is ongoing\n",
112 master_saif
->id
, master_saif
->cur_rate
);
116 scr
= __raw_readl(master_saif
->base
+ SAIF_CTRL
);
117 scr
&= ~BM_SAIF_CTRL_BITCLK_MULT_RATE
;
118 scr
&= ~BM_SAIF_CTRL_BITCLK_BASE_RATE
;
123 * The SAIF clock should be either 384*fs or 512*fs.
124 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
125 * For 32x mclk, set saif clk as 512*fs.
126 * For 48x mclk, set saif clk as 384*fs.
128 * If MCLK is not used, we just set saif clk to 512*fs.
130 clk_prepare_enable(master_saif
->clk
);
132 if (master_saif
->mclk_in_use
) {
133 if (mclk
% 32 == 0) {
134 scr
&= ~BM_SAIF_CTRL_BITCLK_BASE_RATE
;
135 ret
= clk_set_rate(master_saif
->clk
, 512 * rate
);
136 } else if (mclk
% 48 == 0) {
137 scr
|= BM_SAIF_CTRL_BITCLK_BASE_RATE
;
138 ret
= clk_set_rate(master_saif
->clk
, 384 * rate
);
140 /* SAIF MCLK should be either 32x or 48x */
141 clk_disable_unprepare(master_saif
->clk
);
145 ret
= clk_set_rate(master_saif
->clk
, 512 * rate
);
146 scr
&= ~BM_SAIF_CTRL_BITCLK_BASE_RATE
;
149 clk_disable_unprepare(master_saif
->clk
);
154 master_saif
->cur_rate
= rate
;
156 if (!master_saif
->mclk_in_use
) {
157 __raw_writel(scr
, master_saif
->base
+ SAIF_CTRL
);
162 * Program the over-sample rate for MCLK output
164 * The available MCLK range is 32x, 48x... 512x. The rate
165 * could be from 8kHz to 192kH.
167 switch (mclk
/ rate
) {
169 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
172 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
175 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
178 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
181 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
184 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
187 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
190 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
193 scr
|= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
199 __raw_writel(scr
, master_saif
->base
+ SAIF_CTRL
);
205 * Put and disable MCLK.
207 int mxs_saif_put_mclk(unsigned int saif_id
)
209 struct mxs_saif
*saif
= mxs_saif
[saif_id
];
215 stat
= __raw_readl(saif
->base
+ SAIF_STAT
);
216 if (stat
& BM_SAIF_STAT_BUSY
) {
217 dev_err(saif
->dev
, "error: busy\n");
221 clk_disable_unprepare(saif
->clk
);
223 /* disable MCLK output */
224 __raw_writel(BM_SAIF_CTRL_CLKGATE
,
225 saif
->base
+ SAIF_CTRL
+ MXS_SET_ADDR
);
226 __raw_writel(BM_SAIF_CTRL_RUN
,
227 saif
->base
+ SAIF_CTRL
+ MXS_CLR_ADDR
);
229 saif
->mclk_in_use
= 0;
234 * Get MCLK and set clock rate, then enable it
236 * This interface is used for codecs who are using MCLK provided
239 int mxs_saif_get_mclk(unsigned int saif_id
, unsigned int mclk
,
242 struct mxs_saif
*saif
= mxs_saif
[saif_id
];
245 struct mxs_saif
*master_saif
;
251 __raw_writel(BM_SAIF_CTRL_SFTRST
,
252 saif
->base
+ SAIF_CTRL
+ MXS_CLR_ADDR
);
254 /* FIXME: need clear clk gate for register r/w */
255 __raw_writel(BM_SAIF_CTRL_CLKGATE
,
256 saif
->base
+ SAIF_CTRL
+ MXS_CLR_ADDR
);
258 master_saif
= mxs_saif_get_master(saif
);
259 if (saif
!= master_saif
) {
260 dev_err(saif
->dev
, "can not get mclk from a non-master saif\n");
264 stat
= __raw_readl(saif
->base
+ SAIF_STAT
);
265 if (stat
& BM_SAIF_STAT_BUSY
) {
266 dev_err(saif
->dev
, "error: busy\n");
270 saif
->mclk_in_use
= 1;
271 ret
= mxs_saif_set_clk(saif
, mclk
, rate
);
275 ret
= clk_prepare_enable(saif
->clk
);
279 /* enable MCLK output */
280 __raw_writel(BM_SAIF_CTRL_RUN
,
281 saif
->base
+ SAIF_CTRL
+ MXS_SET_ADDR
);
287 * SAIF DAI format configuration.
288 * Should only be called when port is inactive.
290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai
*cpu_dai
, unsigned int fmt
)
294 struct mxs_saif
*saif
= snd_soc_dai_get_drvdata(cpu_dai
);
296 stat
= __raw_readl(saif
->base
+ SAIF_STAT
);
297 if (stat
& BM_SAIF_STAT_BUSY
) {
298 dev_err(cpu_dai
->dev
, "error: busy\n");
302 scr0
= __raw_readl(saif
->base
+ SAIF_CTRL
);
303 scr0
= scr0
& ~BM_SAIF_CTRL_BITCLK_EDGE
& ~BM_SAIF_CTRL_LRCLK_POLARITY \
304 & ~BM_SAIF_CTRL_JUSTIFY
& ~BM_SAIF_CTRL_DELAY
;
308 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
309 case SND_SOC_DAIFMT_I2S
:
310 /* data frame low 1clk before data */
311 scr
|= BM_SAIF_CTRL_DELAY
;
312 scr
&= ~BM_SAIF_CTRL_LRCLK_POLARITY
;
314 case SND_SOC_DAIFMT_LEFT_J
:
315 /* data frame high with data */
316 scr
&= ~BM_SAIF_CTRL_DELAY
;
317 scr
&= ~BM_SAIF_CTRL_LRCLK_POLARITY
;
318 scr
&= ~BM_SAIF_CTRL_JUSTIFY
;
324 /* DAI clock inversion */
325 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
326 case SND_SOC_DAIFMT_IB_IF
:
327 scr
|= BM_SAIF_CTRL_BITCLK_EDGE
;
328 scr
|= BM_SAIF_CTRL_LRCLK_POLARITY
;
330 case SND_SOC_DAIFMT_IB_NF
:
331 scr
|= BM_SAIF_CTRL_BITCLK_EDGE
;
332 scr
&= ~BM_SAIF_CTRL_LRCLK_POLARITY
;
334 case SND_SOC_DAIFMT_NB_IF
:
335 scr
&= ~BM_SAIF_CTRL_BITCLK_EDGE
;
336 scr
|= BM_SAIF_CTRL_LRCLK_POLARITY
;
338 case SND_SOC_DAIFMT_NB_NF
:
339 scr
&= ~BM_SAIF_CTRL_BITCLK_EDGE
;
340 scr
&= ~BM_SAIF_CTRL_LRCLK_POLARITY
;
345 * Note: We simply just support master mode since SAIF TX can only
347 * Here the master is relative to codec side.
348 * Saif internally could be slave when working on EXTMASTER mode.
349 * We just hide this to machine driver.
351 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
352 case SND_SOC_DAIFMT_CBS_CFS
:
353 if (saif
->id
== saif
->master_id
)
354 scr
&= ~BM_SAIF_CTRL_SLAVE_MODE
;
356 scr
|= BM_SAIF_CTRL_SLAVE_MODE
;
358 __raw_writel(scr
| scr0
, saif
->base
+ SAIF_CTRL
);
367 static int mxs_saif_startup(struct snd_pcm_substream
*substream
,
368 struct snd_soc_dai
*cpu_dai
)
370 struct mxs_saif
*saif
= snd_soc_dai_get_drvdata(cpu_dai
);
371 snd_soc_dai_set_dma_data(cpu_dai
, substream
, &saif
->dma_param
);
373 /* clear error status to 0 for each re-open */
374 saif
->fifo_underrun
= 0;
375 saif
->fifo_overrun
= 0;
377 /* Clear Reset for normal operations */
378 __raw_writel(BM_SAIF_CTRL_SFTRST
,
379 saif
->base
+ SAIF_CTRL
+ MXS_CLR_ADDR
);
381 /* clear clock gate */
382 __raw_writel(BM_SAIF_CTRL_CLKGATE
,
383 saif
->base
+ SAIF_CTRL
+ MXS_CLR_ADDR
);
389 * Should only be called when port is inactive.
390 * although can be called multiple times by upper layers.
392 static int mxs_saif_hw_params(struct snd_pcm_substream
*substream
,
393 struct snd_pcm_hw_params
*params
,
394 struct snd_soc_dai
*cpu_dai
)
396 struct mxs_saif
*saif
= snd_soc_dai_get_drvdata(cpu_dai
);
400 /* mclk should already be set */
401 if (!saif
->mclk
&& saif
->mclk_in_use
) {
402 dev_err(cpu_dai
->dev
, "set mclk first\n");
406 stat
= __raw_readl(saif
->base
+ SAIF_STAT
);
407 if (stat
& BM_SAIF_STAT_BUSY
) {
408 dev_err(cpu_dai
->dev
, "error: busy\n");
413 * Set saif clk based on sample rate.
414 * If mclk is used, we also set mclk, if not, saif->mclk is
415 * default 0, means not used.
417 ret
= mxs_saif_set_clk(saif
, saif
->mclk
, params_rate(params
));
419 dev_err(cpu_dai
->dev
, "unable to get proper clk\n");
423 scr
= __raw_readl(saif
->base
+ SAIF_CTRL
);
425 scr
&= ~BM_SAIF_CTRL_WORD_LENGTH
;
426 scr
&= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE
;
427 switch (params_format(params
)) {
428 case SNDRV_PCM_FORMAT_S16_LE
:
429 scr
|= BF_SAIF_CTRL_WORD_LENGTH(0);
431 case SNDRV_PCM_FORMAT_S20_3LE
:
432 scr
|= BF_SAIF_CTRL_WORD_LENGTH(4);
433 scr
|= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE
;
435 case SNDRV_PCM_FORMAT_S24_LE
:
436 scr
|= BF_SAIF_CTRL_WORD_LENGTH(8);
437 scr
|= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE
;
444 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
446 scr
&= ~BM_SAIF_CTRL_READ_MODE
;
449 scr
|= BM_SAIF_CTRL_READ_MODE
;
452 __raw_writel(scr
, saif
->base
+ SAIF_CTRL
);
456 static int mxs_saif_prepare(struct snd_pcm_substream
*substream
,
457 struct snd_soc_dai
*cpu_dai
)
459 struct mxs_saif
*saif
= snd_soc_dai_get_drvdata(cpu_dai
);
461 /* enable FIFO error irqs */
462 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN
,
463 saif
->base
+ SAIF_CTRL
+ MXS_SET_ADDR
);
468 static int mxs_saif_trigger(struct snd_pcm_substream
*substream
, int cmd
,
469 struct snd_soc_dai
*cpu_dai
)
471 struct mxs_saif
*saif
= snd_soc_dai_get_drvdata(cpu_dai
);
472 struct mxs_saif
*master_saif
;
475 master_saif
= mxs_saif_get_master(saif
);
480 case SNDRV_PCM_TRIGGER_START
:
481 case SNDRV_PCM_TRIGGER_RESUME
:
482 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
483 dev_dbg(cpu_dai
->dev
, "start\n");
485 clk_enable(master_saif
->clk
);
486 if (!master_saif
->mclk_in_use
)
487 __raw_writel(BM_SAIF_CTRL_RUN
,
488 master_saif
->base
+ SAIF_CTRL
+ MXS_SET_ADDR
);
491 * If the saif's master is not himself, we also need to enable
492 * itself clk for its internal basic logic to work.
494 if (saif
!= master_saif
) {
495 clk_enable(saif
->clk
);
496 __raw_writel(BM_SAIF_CTRL_RUN
,
497 saif
->base
+ SAIF_CTRL
+ MXS_SET_ADDR
);
500 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
502 * write a data to saif data register to trigger
505 __raw_writel(0, saif
->base
+ SAIF_DATA
);
508 * read a data from saif data register to trigger
511 __raw_readl(saif
->base
+ SAIF_DATA
);
514 master_saif
->ongoing
= 1;
516 dev_dbg(saif
->dev
, "CTRL 0x%x STAT 0x%x\n",
517 __raw_readl(saif
->base
+ SAIF_CTRL
),
518 __raw_readl(saif
->base
+ SAIF_STAT
));
520 dev_dbg(master_saif
->dev
, "CTRL 0x%x STAT 0x%x\n",
521 __raw_readl(master_saif
->base
+ SAIF_CTRL
),
522 __raw_readl(master_saif
->base
+ SAIF_STAT
));
524 case SNDRV_PCM_TRIGGER_SUSPEND
:
525 case SNDRV_PCM_TRIGGER_STOP
:
526 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
527 dev_dbg(cpu_dai
->dev
, "stop\n");
529 /* wait a while for the current sample to complete */
530 delay
= USEC_PER_SEC
/ master_saif
->cur_rate
;
532 if (!master_saif
->mclk_in_use
) {
533 __raw_writel(BM_SAIF_CTRL_RUN
,
534 master_saif
->base
+ SAIF_CTRL
+ MXS_CLR_ADDR
);
537 clk_disable(master_saif
->clk
);
539 if (saif
!= master_saif
) {
540 __raw_writel(BM_SAIF_CTRL_RUN
,
541 saif
->base
+ SAIF_CTRL
+ MXS_CLR_ADDR
);
543 clk_disable(saif
->clk
);
546 master_saif
->ongoing
= 0;
556 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
557 #define MXS_SAIF_FORMATS \
558 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
559 SNDRV_PCM_FMTBIT_S24_LE)
561 static const struct snd_soc_dai_ops mxs_saif_dai_ops
= {
562 .startup
= mxs_saif_startup
,
563 .trigger
= mxs_saif_trigger
,
564 .prepare
= mxs_saif_prepare
,
565 .hw_params
= mxs_saif_hw_params
,
566 .set_sysclk
= mxs_saif_set_dai_sysclk
,
567 .set_fmt
= mxs_saif_set_dai_fmt
,
570 static int mxs_saif_dai_probe(struct snd_soc_dai
*dai
)
572 struct mxs_saif
*saif
= dev_get_drvdata(dai
->dev
);
574 snd_soc_dai_set_drvdata(dai
, saif
);
579 static struct snd_soc_dai_driver mxs_saif_dai
= {
581 .probe
= mxs_saif_dai_probe
,
585 .rates
= MXS_SAIF_RATES
,
586 .formats
= MXS_SAIF_FORMATS
,
591 .rates
= MXS_SAIF_RATES
,
592 .formats
= MXS_SAIF_FORMATS
,
594 .ops
= &mxs_saif_dai_ops
,
597 static irqreturn_t
mxs_saif_irq(int irq
, void *dev_id
)
599 struct mxs_saif
*saif
= dev_id
;
602 stat
= __raw_readl(saif
->base
+ SAIF_STAT
);
603 if (!(stat
& (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ
|
604 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ
)))
607 if (stat
& BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ
) {
608 dev_dbg(saif
->dev
, "underrun!!! %d\n", ++saif
->fifo_underrun
);
609 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ
,
610 saif
->base
+ SAIF_STAT
+ MXS_CLR_ADDR
);
613 if (stat
& BM_SAIF_STAT_FIFO_OVERFLOW_IRQ
) {
614 dev_dbg(saif
->dev
, "overrun!!! %d\n", ++saif
->fifo_overrun
);
615 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ
,
616 saif
->base
+ SAIF_STAT
+ MXS_CLR_ADDR
);
619 dev_dbg(saif
->dev
, "SAIF_CTRL %x SAIF_STAT %x\n",
620 __raw_readl(saif
->base
+ SAIF_CTRL
),
621 __raw_readl(saif
->base
+ SAIF_STAT
));
626 static int __devinit
mxs_saif_probe(struct platform_device
*pdev
)
628 struct device_node
*np
= pdev
->dev
.of_node
;
629 struct resource
*iores
, *dmares
;
630 struct mxs_saif
*saif
;
631 struct mxs_saif_platform_data
*pdata
;
632 struct pinctrl
*pinctrl
;
636 if (!np
&& pdev
->id
>= ARRAY_SIZE(mxs_saif
))
639 saif
= devm_kzalloc(&pdev
->dev
, sizeof(*saif
), GFP_KERNEL
);
644 struct device_node
*master
;
645 saif
->id
= of_alias_get_id(np
, "saif");
649 * If there is no "fsl,saif-master" phandle, it's a saif
650 * master. Otherwise, it's a slave and its phandle points
653 master
= of_parse_phandle(np
, "fsl,saif-master", 0);
655 saif
->master_id
= saif
->id
;
657 saif
->master_id
= of_alias_get_id(master
, "saif");
658 if (saif
->master_id
< 0)
659 return saif
->master_id
;
663 pdata
= pdev
->dev
.platform_data
;
664 if (pdata
&& !pdata
->master_mode
)
665 saif
->master_id
= pdata
->master_id
;
667 saif
->master_id
= saif
->id
;
670 if (saif
->master_id
< 0 || saif
->master_id
>= ARRAY_SIZE(mxs_saif
)) {
671 dev_err(&pdev
->dev
, "get wrong master id\n");
675 mxs_saif
[saif
->id
] = saif
;
677 pinctrl
= devm_pinctrl_get_select_default(&pdev
->dev
);
678 if (IS_ERR(pinctrl
)) {
679 ret
= PTR_ERR(pinctrl
);
683 saif
->clk
= clk_get(&pdev
->dev
, NULL
);
684 if (IS_ERR(saif
->clk
)) {
685 ret
= PTR_ERR(saif
->clk
);
686 dev_err(&pdev
->dev
, "Cannot get the clock: %d\n",
691 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
693 saif
->base
= devm_request_and_ioremap(&pdev
->dev
, iores
);
695 dev_err(&pdev
->dev
, "ioremap failed\n");
697 goto failed_get_resource
;
700 dmares
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
703 * TODO: This is a temporary solution and should be changed
704 * to use generic DMA binding later when the helplers get in.
706 ret
= of_property_read_u32(np
, "fsl,saif-dma-channel",
707 &saif
->dma_param
.chan_num
);
709 dev_err(&pdev
->dev
, "failed to get dma channel\n");
710 goto failed_get_resource
;
713 saif
->dma_param
.chan_num
= dmares
->start
;
716 saif
->irq
= platform_get_irq(pdev
, 0);
719 dev_err(&pdev
->dev
, "failed to get irq resource: %d\n",
721 goto failed_get_resource
;
724 saif
->dev
= &pdev
->dev
;
725 ret
= devm_request_irq(&pdev
->dev
, saif
->irq
, mxs_saif_irq
, 0,
728 dev_err(&pdev
->dev
, "failed to request irq\n");
729 goto failed_get_resource
;
732 saif
->dma_param
.chan_irq
= platform_get_irq(pdev
, 1);
733 if (saif
->dma_param
.chan_irq
< 0) {
734 ret
= saif
->dma_param
.chan_irq
;
735 dev_err(&pdev
->dev
, "failed to get dma irq resource: %d\n",
737 goto failed_get_resource
;
740 platform_set_drvdata(pdev
, saif
);
742 ret
= snd_soc_register_dai(&pdev
->dev
, &mxs_saif_dai
);
744 dev_err(&pdev
->dev
, "register DAI failed\n");
745 goto failed_get_resource
;
748 ret
= mxs_pcm_platform_register(&pdev
->dev
);
750 dev_err(&pdev
->dev
, "register PCM failed: %d\n", ret
);
751 goto failed_pdev_alloc
;
757 snd_soc_unregister_dai(&pdev
->dev
);
764 static int __devexit
mxs_saif_remove(struct platform_device
*pdev
)
766 struct mxs_saif
*saif
= platform_get_drvdata(pdev
);
768 mxs_pcm_platform_unregister(&pdev
->dev
);
769 snd_soc_unregister_dai(&pdev
->dev
);
775 static const struct of_device_id mxs_saif_dt_ids
[] = {
776 { .compatible
= "fsl,imx28-saif", },
779 MODULE_DEVICE_TABLE(of
, mxs_saif_dt_ids
);
781 static struct platform_driver mxs_saif_driver
= {
782 .probe
= mxs_saif_probe
,
783 .remove
= __devexit_p(mxs_saif_remove
),
787 .owner
= THIS_MODULE
,
788 .of_match_table
= mxs_saif_dt_ids
,
792 module_platform_driver(mxs_saif_driver
);
794 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
795 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
796 MODULE_LICENSE("GPL");