sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33
  34 #include <plat/control.h>
  35 #include <plat/dma.h>
  36 #include <plat/mcbsp.h>
  37 #include "omap-mcbsp.h"
  38 #include "omap-pcm.h"
  39
  40 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  41
  42 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  43         xhandler_get, xhandler_put) \
  44 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  45         .info = omap_mcbsp_st_info_volsw, \
  46         .get = xhandler_get, .put = xhandler_put, \
  47         .private_value = (unsigned long) &(struct soc_mixer_control) \
  48         {.min = xmin, .max = xmax} }
  49
  50 struct omap_mcbsp_data {
  51         unsigned int                    bus_id;
  52         struct omap_mcbsp_reg_cfg       regs;
  53         unsigned int                    fmt;
  54         /*
  55          * Flags indicating is the bus already activated and configured by
  56          * another substream
  57          */
  58         int                             active;
  59         int                             configured;
  60         unsigned int                    in_freq;
  61         int                             clk_div;
  62         int                             wlen;
  63 };
  64
  65 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  66
  67 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  68
  69 /*
  70  * Stream DMA parameters. DMA request line and port address are set runtime
  71  * since they are different between OMAP1 and later OMAPs
  72  */
  73 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  74
  75 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  76 static const int omap1_dma_reqs[][2] = {
  77         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  78         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  79         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  80 };
  81 static const unsigned long omap1_mcbsp_port[][2] = {
  82         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  83           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  84         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  85           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  86         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  87           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  88 };
  89 #else
  90 static const int omap1_dma_reqs[][2] = {};
  91 static const unsigned long omap1_mcbsp_port[][2] = {};
  92 #endif
  93
  94 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  95 static const int omap24xx_dma_reqs[][2] = {
  96         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  97         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  98 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
  99         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
 100         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
 101         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
 102 #endif
 103 };
 104 #else
 105 static const int omap24xx_dma_reqs[][2] = {};
 106 #endif
 107
 108 #if defined(CONFIG_ARCH_OMAP2420)
 109 static const unsigned long omap2420_mcbsp_port[][2] = {
 110         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 111           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 112         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 113           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 114 };
 115 #else
 116 static const unsigned long omap2420_mcbsp_port[][2] = {};
 117 #endif
 118
 119 #if defined(CONFIG_ARCH_OMAP2430)
 120 static const unsigned long omap2430_mcbsp_port[][2] = {
 121         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 122           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 123         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 124           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 125         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 126           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 127         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 128           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 129         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 130           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 131 };
 132 #else
 133 static const unsigned long omap2430_mcbsp_port[][2] = {};
 134 #endif
 135
 136 #if defined(CONFIG_ARCH_OMAP3)
 137 static const unsigned long omap34xx_mcbsp_port[][2] = {
 138         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 139           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 140         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 141           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 142         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 143           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 144         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 145           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 146         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 147           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 148 };
 149 #else
 150 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 151 #endif
 152
 153 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 154 {
 155         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 156         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 157         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 158         struct omap_pcm_dma_data *dma_data;
 159         int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
 160         int words;
 161
 162         dma_data = snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
 163
 164         /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 165         if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 166                 /*
 167                  * Configure McBSP threshold based on either:
 168                  * packet_size, when the sDMA is in packet mode, or
 169                  * based on the period size.
 170                  */
 171                 if (dma_data->packet_size)
 172                         words = dma_data->packet_size;
 173                 else
 174                         words = snd_pcm_lib_period_bytes(substream) /
 175                                                         (mcbsp_data->wlen / 8);
 176         else
 177                 words = 1;
 178
 179         /* Configure McBSP internal buffer usage */
 180         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 181                 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
 182         else
 183                 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
 184 }
 185
 186 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 187                                     struct snd_pcm_hw_rule *rule)
 188 {
 189         struct snd_interval *buffer_size = hw_param_interval(params,
 190                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 191         struct snd_interval *channels = hw_param_interval(params,
 192                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 193         struct omap_mcbsp_data *mcbsp_data = rule->private;
 194         struct snd_interval frames;
 195         int size;
 196
 197         snd_interval_any(&frames);
 198         size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
 199
 200         frames.min = size / channels->min;
 201         frames.integer = 1;
 202         return snd_interval_refine(buffer_size, &frames);
 203 }
 204
 205 static int omap_mcbsp_hwrule_max_periodsize(struct snd_pcm_hw_params *params,
 206                                     struct snd_pcm_hw_rule *rule)
 207 {
 208         struct snd_interval *period_size = hw_param_interval(params,
 209                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
 210         struct snd_interval *channels = hw_param_interval(params,
 211                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 212         struct snd_pcm_substream *substream = rule->private;
 213         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 214         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 215         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 216         struct snd_interval frames;
 217         int size;
 218
 219         snd_interval_any(&frames);
 220         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 221                 size = omap_mcbsp_get_max_tx_threshold(mcbsp_data->bus_id);
 222         else
 223                 size = omap_mcbsp_get_max_rx_threshold(mcbsp_data->bus_id);
 224
 225         frames.max = size / channels->min;
 226         frames.integer = 1;
 227         return snd_interval_refine(period_size, &frames);
 228 }
 229
 230 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 231                                   struct snd_soc_dai *dai)
 232 {
 233         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 234         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 235         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 236         int bus_id = mcbsp_data->bus_id;
 237         int err = 0;
 238
 239         if (!cpu_dai->active)
 240                 err = omap_mcbsp_request(bus_id);
 241
 242         /*
 243          * OMAP3 McBSP FIFO is word structured.
 244          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 245          * McBSP1,3,4,5 has 128 word long buffer
 246          * This means that the size of the FIFO depends on the sample format.
 247          * For example on McBSP3:
 248          * 16bit samples: size is 128 * 2 = 256 bytes
 249          * 32bit samples: size is 128 * 4 = 512 bytes
 250          * It is simpler to place constraint for buffer and period based on
 251          * channels.
 252          * McBSP3 as example again (16 or 32 bit samples):
 253          * 1 channel (mono): size is 128 frames (128 words)
 254          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 255          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 256          */
 257         if (cpu_is_omap343x()) {
 258                 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
 259
 260                 /*
 261                 * The first rule is for the buffer size, we should not allow
 262                 * smaller buffer than the FIFO size to avoid underruns
 263                 */
 264                 snd_pcm_hw_rule_add(substream->runtime, 0,
 265                                     SNDRV_PCM_HW_PARAM_CHANNELS,
 266                                     omap_mcbsp_hwrule_min_buffersize,
 267                                     mcbsp_data,
 268                                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
 269
 270                 /*
 271                  * In case of threshold mode, the rule will ensure, that the
 272                  * period size is not bigger than the maximum allowed threshold
 273                  * value.
 274                  */
 275                 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 276                         snd_pcm_hw_rule_add(substream->runtime, 0,
 277                                             SNDRV_PCM_HW_PARAM_CHANNELS,
 278                                             omap_mcbsp_hwrule_max_periodsize,
 279                                             substream,
 280                                             SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
 281         }
 282
 283         return err;
 284 }
 285
 286 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 287                                     struct snd_soc_dai *dai)
 288 {
 289         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 290         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 291         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 292
 293         if (!cpu_dai->active) {
 294                 omap_mcbsp_free(mcbsp_data->bus_id);
 295                 mcbsp_data->configured = 0;
 296         }
 297 }
 298
 299 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 300                                   struct snd_soc_dai *dai)
 301 {
 302         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 303         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 304         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 305         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 306
 307         switch (cmd) {
 308         case SNDRV_PCM_TRIGGER_START:
 309         case SNDRV_PCM_TRIGGER_RESUME:
 310         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 311                 mcbsp_data->active++;
 312                 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
 313                 break;
 314
 315         case SNDRV_PCM_TRIGGER_STOP:
 316         case SNDRV_PCM_TRIGGER_SUSPEND:
 317         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 318                 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
 319                 mcbsp_data->active--;
 320                 break;
 321         default:
 322                 err = -EINVAL;
 323         }
 324
 325         return err;
 326 }
 327
 328 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 329                         struct snd_pcm_substream *substream,
 330                         struct snd_soc_dai *dai)
 331 {
 332         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 333         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 334         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 335         u16 fifo_use;
 336         snd_pcm_sframes_t delay;
 337
 338         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 339                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
 340         else
 341                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
 342
 343         /*
 344          * Divide the used locations with the channel count to get the
 345          * FIFO usage in samples (don't care about partial samples in the
 346          * buffer).
 347          */
 348         delay = fifo_use / substream->runtime->channels;
 349
 350         return delay;
 351 }
 352
 353 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 354                                     struct snd_pcm_hw_params *params,
 355                                     struct snd_soc_dai *dai)
 356 {
 357         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 358         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 359         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 360         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 361         struct omap_pcm_dma_data *dma_data;
 362         int dma, bus_id = mcbsp_data->bus_id;
 363         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 364         int pkt_size = 0;
 365         unsigned long port;
 366         unsigned int format, div, framesize, master;
 367
 368         dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
 369         if (cpu_class_is_omap1()) {
 370                 dma = omap1_dma_reqs[bus_id][substream->stream];
 371                 port = omap1_mcbsp_port[bus_id][substream->stream];
 372         } else if (cpu_is_omap2420()) {
 373                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 374                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 375         } else if (cpu_is_omap2430()) {
 376                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 377                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 378         } else if (cpu_is_omap343x()) {
 379                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 380                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 381         } else {
 382                 return -ENODEV;
 383         }
 384         switch (params_format(params)) {
 385         case SNDRV_PCM_FORMAT_S16_LE:
 386                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 387                 wlen = 16;
 388                 break;
 389         case SNDRV_PCM_FORMAT_S32_LE:
 390                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 391                 wlen = 32;
 392                 break;
 393         default:
 394                 return -EINVAL;
 395         }
 396         if (cpu_is_omap343x()) {
 397                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 398                 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 399                 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
 400                                                 MCBSP_DMA_MODE_THRESHOLD) {
 401                         int period_words, max_thrsh;
 402
 403                         period_words = params_period_bytes(params) / (wlen / 8);
 404                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 405                                 max_thrsh = omap_mcbsp_get_max_tx_threshold(
 406                                                             mcbsp_data->bus_id);
 407                         else
 408                                 max_thrsh = omap_mcbsp_get_max_rx_threshold(
 409                                                             mcbsp_data->bus_id);
 410                         /*
 411                          * If the period contains less or equal number of words,
 412                          * we are using the original threshold mode setup:
 413                          * McBSP threshold = sDMA frame size = period_size
 414                          * Otherwise we switch to sDMA packet mode:
 415                          * McBSP threshold = sDMA packet size
 416                          * sDMA frame size = period size
 417                          */
 418                         if (period_words > max_thrsh) {
 419                                 int divider = 0;
 420
 421                                 /*
 422                                  * Look for the biggest threshold value, which
 423                                  * divides the period size evenly.
 424                                  */
 425                                 divider = period_words / max_thrsh;
 426                                 if (period_words % max_thrsh)
 427                                         divider++;
 428                                 while (period_words % divider &&
 429                                         divider < period_words)
 430                                         divider++;
 431                                 if (divider == period_words)
 432                                         return -EINVAL;
 433
 434                                 pkt_size = period_words / divider;
 435                                 sync_mode = OMAP_DMA_SYNC_PACKET;
 436                         } else {
 437                                 sync_mode = OMAP_DMA_SYNC_FRAME;
 438                         }
 439                 }
 440         }
 441
 442         dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
 443         dma_data->dma_req = dma;
 444         dma_data->port_addr = port;
 445         dma_data->sync_mode = sync_mode;
 446         dma_data->packet_size = pkt_size;
 447
 448         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 449
 450         if (mcbsp_data->configured) {
 451                 /* McBSP already configured by another stream */
 452                 return 0;
 453         }
 454
 455         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 456         wpf = channels = params_channels(params);
 457         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 458                               format == SND_SOC_DAIFMT_LEFT_J)) {
 459                 /* Use dual-phase frames */
 460                 regs->rcr2      |= RPHASE;
 461                 regs->xcr2      |= XPHASE;
 462                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 463                 wpf--;
 464                 regs->rcr2      |= RFRLEN2(wpf - 1);
 465                 regs->xcr2      |= XFRLEN2(wpf - 1);
 466         }
 467
 468         regs->rcr1      |= RFRLEN1(wpf - 1);
 469         regs->xcr1      |= XFRLEN1(wpf - 1);
 470
 471         switch (params_format(params)) {
 472         case SNDRV_PCM_FORMAT_S16_LE:
 473                 /* Set word lengths */
 474                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 475                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 476                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 477                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 478                 break;
 479         case SNDRV_PCM_FORMAT_S32_LE:
 480                 /* Set word lengths */
 481                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 482                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 483                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 484                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 485                 break;
 486         default:
 487                 /* Unsupported PCM format */
 488                 return -EINVAL;
 489         }
 490
 491         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 492          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 493         master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 494         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 495                 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
 496                 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
 497
 498                 if (framesize < wlen * channels) {
 499                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 500                                         "channels\n", __func__);
 501                         return -EINVAL;
 502                 }
 503         } else
 504                 framesize = wlen * channels;
 505
 506         /* Set FS period and length in terms of bit clock periods */
 507         switch (format) {
 508         case SND_SOC_DAIFMT_I2S:
 509         case SND_SOC_DAIFMT_LEFT_J:
 510                 regs->srgr2     |= FPER(framesize - 1);
 511                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 512                 break;
 513         case SND_SOC_DAIFMT_DSP_A:
 514         case SND_SOC_DAIFMT_DSP_B:
 515                 regs->srgr2     |= FPER(framesize - 1);
 516                 regs->srgr1     |= FWID(0);
 517                 break;
 518         }
 519
 520         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 521         mcbsp_data->wlen = wlen;
 522         mcbsp_data->configured = 1;
 523
 524         return 0;
 525 }
 526
 527 /*
 528  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 529  * cache is initialized here
 530  */
 531 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 532                                       unsigned int fmt)
 533 {
 534         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 535         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 536         unsigned int temp_fmt = fmt;
 537
 538         if (mcbsp_data->configured)
 539                 return 0;
 540
 541         mcbsp_data->fmt = fmt;
 542         memset(regs, 0, sizeof(*regs));
 543         /* Generic McBSP register settings */
 544         regs->spcr2     |= XINTM(3) | FREE;
 545         regs->spcr1     |= RINTM(3);
 546         /* RFIG and XFIG are not defined in 34xx */
 547         if (!cpu_is_omap34xx()) {
 548                 regs->rcr2      |= RFIG;
 549                 regs->xcr2      |= XFIG;
 550         }
 551         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 552                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 553                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 554         }
 555
 556         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 557         case SND_SOC_DAIFMT_I2S:
 558                 /* 1-bit data delay */
 559                 regs->rcr2      |= RDATDLY(1);
 560                 regs->xcr2      |= XDATDLY(1);
 561                 break;
 562         case SND_SOC_DAIFMT_LEFT_J:
 563                 /* 0-bit data delay */
 564                 regs->rcr2      |= RDATDLY(0);
 565                 regs->xcr2      |= XDATDLY(0);
 566                 regs->spcr1     |= RJUST(2);
 567                 /* Invert FS polarity configuration */
 568                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 569                 break;
 570         case SND_SOC_DAIFMT_DSP_A:
 571                 /* 1-bit data delay */
 572                 regs->rcr2      |= RDATDLY(1);
 573                 regs->xcr2      |= XDATDLY(1);
 574                 /* Invert FS polarity configuration */
 575                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 576                 break;
 577         case SND_SOC_DAIFMT_DSP_B:
 578                 /* 0-bit data delay */
 579                 regs->rcr2      |= RDATDLY(0);
 580                 regs->xcr2      |= XDATDLY(0);
 581                 /* Invert FS polarity configuration */
 582                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 583                 break;
 584         default:
 585                 /* Unsupported data format */
 586                 return -EINVAL;
 587         }
 588
 589         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 590         case SND_SOC_DAIFMT_CBS_CFS:
 591                 /* McBSP master. Set FS and bit clocks as outputs */
 592                 regs->pcr0      |= FSXM | FSRM |
 593                                    CLKXM | CLKRM;
 594                 /* Sample rate generator drives the FS */
 595                 regs->srgr2     |= FSGM;
 596                 break;
 597         case SND_SOC_DAIFMT_CBM_CFM:
 598                 /* McBSP slave */
 599                 break;
 600         default:
 601                 /* Unsupported master/slave configuration */
 602                 return -EINVAL;
 603         }
 604
 605         /* Set bit clock (CLKX/CLKR) and FS polarities */
 606         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
 607         case SND_SOC_DAIFMT_NB_NF:
 608                 /*
 609                  * Normal BCLK + FS.
 610                  * FS active low. TX data driven on falling edge of bit clock
 611                  * and RX data sampled on rising edge of bit clock.
 612                  */
 613                 regs->pcr0      |= FSXP | FSRP |
 614                                    CLKXP | CLKRP;
 615                 break;
 616         case SND_SOC_DAIFMT_NB_IF:
 617                 regs->pcr0      |= CLKXP | CLKRP;
 618                 break;
 619         case SND_SOC_DAIFMT_IB_NF:
 620                 regs->pcr0      |= FSXP | FSRP;
 621                 break;
 622         case SND_SOC_DAIFMT_IB_IF:
 623                 break;
 624         default:
 625                 return -EINVAL;
 626         }
 627
 628         return 0;
 629 }
 630
 631 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 632                                      int div_id, int div)
 633 {
 634         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 635         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 636
 637         if (div_id != OMAP_MCBSP_CLKGDV)
 638                 return -ENODEV;
 639
 640         mcbsp_data->clk_div = div;
 641         regs->srgr1     |= CLKGDV(div - 1);
 642
 643         return 0;
 644 }
 645
 646 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 647                                        int clk_id)
 648 {
 649         int sel_bit;
 650         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 651
 652         if (cpu_class_is_omap1()) {
 653                 /* OMAP1's can use only external source clock */
 654                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 655                         return -EINVAL;
 656                 else
 657                         return 0;
 658         }
 659
 660         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 661                 return -EINVAL;
 662
 663         if (cpu_is_omap343x())
 664                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 665
 666         switch (mcbsp_data->bus_id) {
 667         case 0:
 668                 reg = OMAP2_CONTROL_DEVCONF0;
 669                 sel_bit = 2;
 670                 break;
 671         case 1:
 672                 reg = OMAP2_CONTROL_DEVCONF0;
 673                 sel_bit = 6;
 674                 break;
 675         case 2:
 676                 reg = reg_devconf1;
 677                 sel_bit = 0;
 678                 break;
 679         case 3:
 680                 reg = reg_devconf1;
 681                 sel_bit = 2;
 682                 break;
 683         case 4:
 684                 reg = reg_devconf1;
 685                 sel_bit = 4;
 686                 break;
 687         default:
 688                 return -EINVAL;
 689         }
 690
 691         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 692                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 693         else
 694                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 695
 696         return 0;
 697 }
 698
 699 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
 700                                        int clk_id)
 701 {
 702         int sel_bit, set = 0;
 703         u16 reg = OMAP2_CONTROL_DEVCONF0;
 704
 705         if (cpu_class_is_omap1())
 706                 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
 707         if (mcbsp_data->bus_id != 0)
 708                 return -EINVAL;
 709
 710         switch (clk_id) {
 711         case OMAP_MCBSP_CLKR_SRC_CLKX:
 712                 set = 1;
 713         case OMAP_MCBSP_CLKR_SRC_CLKR:
 714                 sel_bit = 3;
 715                 break;
 716         case OMAP_MCBSP_FSR_SRC_FSX:
 717                 set = 1;
 718         case OMAP_MCBSP_FSR_SRC_FSR:
 719                 sel_bit = 4;
 720                 break;
 721         default:
 722                 return -EINVAL;
 723         }
 724
 725         if (set)
 726                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 727         else
 728                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 729
 730         return 0;
 731 }
 732
 733 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 734                                          int clk_id, unsigned int freq,
 735                                          int dir)
 736 {
 737         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 738         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 739         int err = 0;
 740
 741         mcbsp_data->in_freq = freq;
 742
 743         switch (clk_id) {
 744         case OMAP_MCBSP_SYSCLK_CLK:
 745                 regs->srgr2     |= CLKSM;
 746                 break;
 747         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 748         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 749                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 750                 break;
 751
 752         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 753                 regs->srgr2     |= CLKSM;
 754         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 755                 regs->pcr0      |= SCLKME;
 756                 break;
 757
 758         case OMAP_MCBSP_CLKR_SRC_CLKR:
 759         case OMAP_MCBSP_CLKR_SRC_CLKX:
 760         case OMAP_MCBSP_FSR_SRC_FSR:
 761         case OMAP_MCBSP_FSR_SRC_FSX:
 762                 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
 763                 break;
 764         default:
 765                 err = -ENODEV;
 766         }
 767
 768         return err;
 769 }
 770
 771 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
 772         .startup        = omap_mcbsp_dai_startup,
 773         .shutdown       = omap_mcbsp_dai_shutdown,
 774         .trigger        = omap_mcbsp_dai_trigger,
 775         .delay          = omap_mcbsp_dai_delay,
 776         .hw_params      = omap_mcbsp_dai_hw_params,
 777         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 778         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 779         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 780 };
 781
 782 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
 783 {                                                               \
 784         .name = "omap-mcbsp-dai-"#link_id,                      \
 785         .id = (link_id),                                        \
 786         .playback = {                                           \
 787                 .channels_min = 1,                              \
 788                 .channels_max = 16,                             \
 789                 .rates = OMAP_MCBSP_RATES,                      \
 790                 .formats = SNDRV_PCM_FMTBIT_S16_LE |            \
 791                            SNDRV_PCM_FMTBIT_S32_LE,             \
 792         },                                                      \
 793         .capture = {                                            \
 794                 .channels_min = 1,                              \
 795                 .channels_max = 16,                             \
 796                 .rates = OMAP_MCBSP_RATES,                      \
 797                 .formats = SNDRV_PCM_FMTBIT_S16_LE |            \
 798                            SNDRV_PCM_FMTBIT_S32_LE,             \
 799         },                                                      \
 800         .ops = &omap_mcbsp_dai_ops,                             \
 801         .private_data = &mcbsp_data[(link_id)].bus_id,          \
 802 }
 803
 804 struct snd_soc_dai omap_mcbsp_dai[] = {
 805         OMAP_MCBSP_DAI_BUILDER(0),
 806         OMAP_MCBSP_DAI_BUILDER(1),
 807 #if NUM_LINKS >= 3
 808         OMAP_MCBSP_DAI_BUILDER(2),
 809 #endif
 810 #if NUM_LINKS == 5
 811         OMAP_MCBSP_DAI_BUILDER(3),
 812         OMAP_MCBSP_DAI_BUILDER(4),
 813 #endif
 814 };
 815
 816 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 817
 818 int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 819                         struct snd_ctl_elem_info *uinfo)
 820 {
 821         struct soc_mixer_control *mc =
 822                 (struct soc_mixer_control *)kcontrol->private_value;
 823         int max = mc->max;
 824         int min = mc->min;
 825
 826         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 827         uinfo->count = 1;
 828         uinfo->value.integer.min = min;
 829         uinfo->value.integer.max = max;
 830         return 0;
 831 }
 832
 833 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel)                   \
 834 static int                                                              \
 835 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 836                                         struct snd_ctl_elem_value *uc)  \
 837 {                                                                       \
 838         struct soc_mixer_control *mc =                                  \
 839                 (struct soc_mixer_control *)kc->private_value;          \
 840         int max = mc->max;                                              \
 841         int min = mc->min;                                              \
 842         int val = uc->value.integer.value[0];                           \
 843                                                                         \
 844         if (val < min || val > max)                                     \
 845                 return -EINVAL;                                         \
 846                                                                         \
 847         /* OMAP McBSP implementation uses index values 0..4 */          \
 848         return omap_st_set_chgain((id)-1, channel, val);                \
 849 }
 850
 851 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel)                   \
 852 static int                                                              \
 853 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 854                                         struct snd_ctl_elem_value *uc)  \
 855 {                                                                       \
 856         s16 chgain;                                                     \
 857                                                                         \
 858         if (omap_st_get_chgain((id)-1, channel, &chgain))               \
 859                 return -EAGAIN;                                         \
 860                                                                         \
 861         uc->value.integer.value[0] = chgain;                            \
 862         return 0;                                                       \
 863 }
 864
 865 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
 866 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
 867 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
 868 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
 869 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
 870 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
 871 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
 872 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
 873
 874 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 875                                 struct snd_ctl_elem_value *ucontrol)
 876 {
 877         struct soc_mixer_control *mc =
 878                 (struct soc_mixer_control *)kcontrol->private_value;
 879         u8 value = ucontrol->value.integer.value[0];
 880
 881         if (value == omap_st_is_enabled(mc->reg))
 882                 return 0;
 883
 884         if (value)
 885                 omap_st_enable(mc->reg);
 886         else
 887                 omap_st_disable(mc->reg);
 888
 889         return 1;
 890 }
 891
 892 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 893                                 struct snd_ctl_elem_value *ucontrol)
 894 {
 895         struct soc_mixer_control *mc =
 896                 (struct soc_mixer_control *)kcontrol->private_value;
 897
 898         ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
 899         return 0;
 900 }
 901
 902 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
 903         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
 904                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 905         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
 906                                       -32768, 32767,
 907                                       omap_mcbsp2_get_st_ch0_volume,
 908                                       omap_mcbsp2_set_st_ch0_volume),
 909         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
 910                                       -32768, 32767,
 911                                       omap_mcbsp2_get_st_ch1_volume,
 912                                       omap_mcbsp2_set_st_ch1_volume),
 913 };
 914
 915 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
 916         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
 917                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 918         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
 919                                       -32768, 32767,
 920                                       omap_mcbsp3_get_st_ch0_volume,
 921                                       omap_mcbsp3_set_st_ch0_volume),
 922         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
 923                                       -32768, 32767,
 924                                       omap_mcbsp3_get_st_ch1_volume,
 925                                       omap_mcbsp3_set_st_ch1_volume),
 926 };
 927
 928 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
 929 {
 930         if (!cpu_is_omap34xx())
 931                 return -ENODEV;
 932
 933         switch (mcbsp_id) {
 934         case 1: /* McBSP 2 */
 935                 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
 936                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 937         case 2: /* McBSP 3 */
 938                 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
 939                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 940         default:
 941                 break;
 942         }
 943
 944         return -EINVAL;
 945 }
 946 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 947
 948 static int __init snd_omap_mcbsp_init(void)
 949 {
 950         return snd_soc_register_dais(omap_mcbsp_dai,
 951                                      ARRAY_SIZE(omap_mcbsp_dai));
 952 }
 953 module_init(snd_omap_mcbsp_init);
 954
 955 static void __exit snd_omap_mcbsp_exit(void)
 956 {
 957         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
 958 }
 959 module_exit(snd_omap_mcbsp_exit);
 960
 961 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
 962 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 963 MODULE_LICENSE("GPL");