sound/soc/omap/omap-mcpdm.c

   1 /*
   2  * omap-mcpdm.c  --  OMAP ALSA SoC DAI driver using McPDM port
   3  *
   4  * Copyright (C) 2009 - 2011 Texas Instruments
   5  *
   6  * Author: Misael Lopez Cruz <misael.lopez@ti.com>
   7  * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
   8  *          Margarita Olaya <magi.olaya@ti.com>
   9  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * version 2 as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23  * 02110-1301 USA
  24  *
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/slab.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/of_device.h>
  37
  38 #include <sound/core.h>
  39 #include <sound/pcm.h>
  40 #include <sound/pcm_params.h>
  41 #include <sound/soc.h>
  42
  43 #include <plat/dma.h>
  44 #include <plat/omap_hwmod.h>
  45 #include "omap-mcpdm.h"
  46 #include "omap-pcm.h"
  47
  48 struct omap_mcpdm {
  49         struct device *dev;
  50         unsigned long phys_base;
  51         void __iomem *io_base;
  52         int irq;
  53
  54         struct mutex mutex;
  55
  56         /* channel data */
  57         u32 dn_channels;
  58         u32 up_channels;
  59
  60         /* McPDM FIFO thresholds */
  61         u32 dn_threshold;
  62         u32 up_threshold;
  63
  64         /* McPDM dn offsets for rx1, and 2 channels */
  65         u32 dn_rx_offset;
  66 };
  67
  68 /*
  69  * Stream DMA parameters
  70  */
  71 static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
  72         {
  73                 .name = "Audio playback",
  74                 .dma_req = OMAP44XX_DMA_MCPDM_DL,
  75                 .data_type = OMAP_DMA_DATA_TYPE_S32,
  76                 .port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
  77         },
  78         {
  79                 .name = "Audio capture",
  80                 .dma_req = OMAP44XX_DMA_MCPDM_UP,
  81                 .data_type = OMAP_DMA_DATA_TYPE_S32,
  82                 .port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
  83         },
  84 };
  85
  86 static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
  87 {
  88         __raw_writel(val, mcpdm->io_base + reg);
  89 }
  90
  91 static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
  92 {
  93         return __raw_readl(mcpdm->io_base + reg);
  94 }
  95
  96 #ifdef DEBUG
  97 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
  98 {
  99         dev_dbg(mcpdm->dev, "***********************\n");
 100         dev_dbg(mcpdm->dev, "IRQSTATUS_RAW:  0x%04x\n",
 101                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
 102         dev_dbg(mcpdm->dev, "IRQSTATUS:  0x%04x\n",
 103                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
 104         dev_dbg(mcpdm->dev, "IRQENABLE_SET:  0x%04x\n",
 105                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
 106         dev_dbg(mcpdm->dev, "IRQENABLE_CLR:  0x%04x\n",
 107                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
 108         dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
 109                         omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
 110         dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
 111                         omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
 112         dev_dbg(mcpdm->dev, "DMAENABLE_CLR:  0x%04x\n",
 113                         omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
 114         dev_dbg(mcpdm->dev, "DMAWAKEEN:  0x%04x\n",
 115                         omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
 116         dev_dbg(mcpdm->dev, "CTRL:  0x%04x\n",
 117                         omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
 118         dev_dbg(mcpdm->dev, "DN_DATA:  0x%04x\n",
 119                         omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
 120         dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
 121                         omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
 122         dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
 123                         omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
 124         dev_dbg(mcpdm->dev, "FIFO_CTRL_UP:  0x%04x\n",
 125                         omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
 126         dev_dbg(mcpdm->dev, "***********************\n");
 127 }
 128 #else
 129 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
 130 #endif
 131
 132 /*
 133  * Enables the transfer through the PDM interface to/from the Phoenix
 134  * codec by enabling the corresponding UP or DN channels.
 135  */
 136 static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
 137 {
 138         u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
 139
 140         ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
 141         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 142
 143         ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
 144         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 145
 146         ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
 147         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 148 }
 149
 150 /*
 151  * Disables the transfer through the PDM interface to/from the Phoenix
 152  * codec by disabling the corresponding UP or DN channels.
 153  */
 154 static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
 155 {
 156         u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
 157
 158         ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
 159         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 160
 161         ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
 162         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 163
 164         ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
 165         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
 166
 167 }
 168
 169 /*
 170  * Is the physical McPDM interface active.
 171  */
 172 static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
 173 {
 174         return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
 175                                         (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
 176 }
 177
 178 /*
 179  * Configures McPDM uplink, and downlink for audio.
 180  * This function should be called before omap_mcpdm_start.
 181  */
 182 static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
 183 {
 184         omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
 185                         MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
 186                         MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
 187
 188         /* Enable DN RX1/2 offset cancellation feature, if configured */
 189         if (mcpdm->dn_rx_offset) {
 190                 u32 dn_offset = mcpdm->dn_rx_offset;
 191
 192                 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
 193                 dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
 194                 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
 195         }
 196
 197         omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
 198         omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
 199
 200         omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
 201                         MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
 202 }
 203
 204 /*
 205  * Cleans McPDM uplink, and downlink configuration.
 206  * This function should be called when the stream is closed.
 207  */
 208 static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
 209 {
 210         /* Disable irq request generation for downlink */
 211         omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
 212                         MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
 213
 214         /* Disable DMA request generation for downlink */
 215         omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
 216
 217         /* Disable irq request generation for uplink */
 218         omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
 219                         MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
 220
 221         /* Disable DMA request generation for uplink */
 222         omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
 223
 224         /* Disable RX1/2 offset cancellation */
 225         if (mcpdm->dn_rx_offset)
 226                 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
 227 }
 228
 229 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
 230 {
 231         struct omap_mcpdm *mcpdm = dev_id;
 232         int irq_status;
 233
 234         irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
 235
 236         /* Acknowledge irq event */
 237         omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
 238
 239         if (irq_status & MCPDM_DN_IRQ_FULL)
 240                 dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
 241
 242         if (irq_status & MCPDM_DN_IRQ_EMPTY)
 243                 dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
 244
 245         if (irq_status & MCPDM_DN_IRQ)
 246                 dev_dbg(mcpdm->dev, "DN (playback) write request\n");
 247
 248         if (irq_status & MCPDM_UP_IRQ_FULL)
 249                 dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
 250
 251         if (irq_status & MCPDM_UP_IRQ_EMPTY)
 252                 dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
 253
 254         if (irq_status & MCPDM_UP_IRQ)
 255                 dev_dbg(mcpdm->dev, "UP (capture) write request\n");
 256
 257         return IRQ_HANDLED;
 258 }
 259
 260 static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
 261                                   struct snd_soc_dai *dai)
 262 {
 263         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 264
 265         mutex_lock(&mcpdm->mutex);
 266
 267         if (!dai->active) {
 268                 /* Enable watch dog for ES above ES 1.0 to avoid saturation */
 269                 if (omap_rev() != OMAP4430_REV_ES1_0) {
 270                         u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
 271
 272                         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
 273                                          ctrl | MCPDM_WD_EN);
 274                 }
 275                 omap_mcpdm_open_streams(mcpdm);
 276         }
 277
 278         mutex_unlock(&mcpdm->mutex);
 279
 280         return 0;
 281 }
 282
 283 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
 284                                   struct snd_soc_dai *dai)
 285 {
 286         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 287
 288         mutex_lock(&mcpdm->mutex);
 289
 290         if (!dai->active) {
 291                 if (omap_mcpdm_active(mcpdm)) {
 292                         omap_mcpdm_stop(mcpdm);
 293                         omap_mcpdm_close_streams(mcpdm);
 294                 }
 295         }
 296
 297         mutex_unlock(&mcpdm->mutex);
 298 }
 299
 300 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
 301                                     struct snd_pcm_hw_params *params,
 302                                     struct snd_soc_dai *dai)
 303 {
 304         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 305         int stream = substream->stream;
 306         struct omap_pcm_dma_data *dma_data;
 307         int channels;
 308         int link_mask = 0;
 309
 310         channels = params_channels(params);
 311         switch (channels) {
 312         case 5:
 313                 if (stream == SNDRV_PCM_STREAM_CAPTURE)
 314                         /* up to 3 channels for capture */
 315                         return -EINVAL;
 316                 link_mask |= 1 << 4;
 317         case 4:
 318                 if (stream == SNDRV_PCM_STREAM_CAPTURE)
 319                         /* up to 3 channels for capture */
 320                         return -EINVAL;
 321                 link_mask |= 1 << 3;
 322         case 3:
 323                 link_mask |= 1 << 2;
 324         case 2:
 325                 link_mask |= 1 << 1;
 326         case 1:
 327                 link_mask |= 1 << 0;
 328                 break;
 329         default:
 330                 /* unsupported number of channels */
 331                 return -EINVAL;
 332         }
 333
 334         dma_data = &omap_mcpdm_dai_dma_params[stream];
 335
 336         /* Configure McPDM channels, and DMA packet size */
 337         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 338                 mcpdm->dn_channels = link_mask << 3;
 339                 dma_data->packet_size =
 340                         (MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
 341         } else {
 342                 mcpdm->up_channels = link_mask << 0;
 343                 dma_data->packet_size = mcpdm->up_threshold * channels;
 344         }
 345
 346         snd_soc_dai_set_dma_data(dai, substream, dma_data);
 347
 348         return 0;
 349 }
 350
 351 static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
 352                                   struct snd_soc_dai *dai)
 353 {
 354         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 355
 356         if (!omap_mcpdm_active(mcpdm)) {
 357                 omap_mcpdm_start(mcpdm);
 358                 omap_mcpdm_reg_dump(mcpdm);
 359         }
 360
 361         return 0;
 362 }
 363
 364 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
 365         .startup        = omap_mcpdm_dai_startup,
 366         .shutdown       = omap_mcpdm_dai_shutdown,
 367         .hw_params      = omap_mcpdm_dai_hw_params,
 368         .prepare        = omap_mcpdm_prepare,
 369 };
 370
 371 static int omap_mcpdm_probe(struct snd_soc_dai *dai)
 372 {
 373         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 374         int ret;
 375
 376         pm_runtime_enable(mcpdm->dev);
 377
 378         /* Disable lines while request is ongoing */
 379         pm_runtime_get_sync(mcpdm->dev);
 380         omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
 381
 382         ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
 383                                 0, "McPDM", (void *)mcpdm);
 384
 385         pm_runtime_put_sync(mcpdm->dev);
 386
 387         if (ret) {
 388                 dev_err(mcpdm->dev, "Request for IRQ failed\n");
 389                 pm_runtime_disable(mcpdm->dev);
 390         }
 391
 392         /* Configure McPDM threshold values */
 393         mcpdm->dn_threshold = 2;
 394         mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
 395         return ret;
 396 }
 397
 398 static int omap_mcpdm_remove(struct snd_soc_dai *dai)
 399 {
 400         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
 401
 402         free_irq(mcpdm->irq, (void *)mcpdm);
 403         pm_runtime_disable(mcpdm->dev);
 404
 405         return 0;
 406 }
 407
 408 #define OMAP_MCPDM_RATES        (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
 409 #define OMAP_MCPDM_FORMATS      SNDRV_PCM_FMTBIT_S32_LE
 410
 411 static struct snd_soc_dai_driver omap_mcpdm_dai = {
 412         .probe = omap_mcpdm_probe,
 413         .remove = omap_mcpdm_remove,
 414         .probe_order = SND_SOC_COMP_ORDER_LATE,
 415         .remove_order = SND_SOC_COMP_ORDER_EARLY,
 416         .playback = {
 417                 .channels_min = 1,
 418                 .channels_max = 5,
 419                 .rates = OMAP_MCPDM_RATES,
 420                 .formats = OMAP_MCPDM_FORMATS,
 421                 .sig_bits = 24,
 422         },
 423         .capture = {
 424                 .channels_min = 1,
 425                 .channels_max = 3,
 426                 .rates = OMAP_MCPDM_RATES,
 427                 .formats = OMAP_MCPDM_FORMATS,
 428                 .sig_bits = 24,
 429         },
 430         .ops = &omap_mcpdm_dai_ops,
 431 };
 432
 433 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
 434                                     u8 rx1, u8 rx2)
 435 {
 436         struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
 437
 438         mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
 439 }
 440 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
 441
 442 static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
 443 {
 444         struct omap_mcpdm *mcpdm;
 445         struct resource *res;
 446
 447         mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
 448         if (!mcpdm)
 449                 return -ENOMEM;
 450
 451         platform_set_drvdata(pdev, mcpdm);
 452
 453         mutex_init(&mcpdm->mutex);
 454
 455         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 456         if (res == NULL)
 457                 return -ENOMEM;
 458
 459         if (!devm_request_mem_region(&pdev->dev, res->start,
 460                                      resource_size(res), "McPDM"))
 461                 return -EBUSY;
 462
 463         mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
 464                                       resource_size(res));
 465         if (!mcpdm->io_base)
 466                 return -ENOMEM;
 467
 468         mcpdm->irq = platform_get_irq(pdev, 0);
 469         if (mcpdm->irq < 0)
 470                 return mcpdm->irq;
 471
 472         mcpdm->dev = &pdev->dev;
 473
 474         return snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
 475 }
 476
 477 static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
 478 {
 479         snd_soc_unregister_dai(&pdev->dev);
 480         return 0;
 481 }
 482
 483 static const struct of_device_id omap_mcpdm_of_match[] = {
 484         { .compatible = "ti,omap4-mcpdm", },
 485         { }
 486 };
 487 MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
 488
 489 static struct platform_driver asoc_mcpdm_driver = {
 490         .driver = {
 491                 .name   = "omap-mcpdm",
 492                 .owner  = THIS_MODULE,
 493                 .of_match_table = omap_mcpdm_of_match,
 494         },
 495
 496         .probe  = asoc_mcpdm_probe,
 497         .remove = __devexit_p(asoc_mcpdm_remove),
 498 };
 499
 500 module_platform_driver(asoc_mcpdm_driver);
 501
 502 MODULE_ALIAS("platform:omap-mcpdm");
 503 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
 504 MODULE_DESCRIPTION("OMAP PDM SoC Interface");
 505 MODULE_LICENSE("GPL");