2 * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
4 * Copyright (C) 2009 - 2011 Texas Instruments
6 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
7 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
8 * Margarita Olaya <magi.olaya@ti.com>
9 * Peter Ujfalusi <peter.ujfalusi@ti.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/interrupt.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/clk.h>
35 #include <linux/slab.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/of_device.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/soc.h>
43 #include <sound/dmaengine_pcm.h>
44 #include <sound/omap-pcm.h>
46 #include "omap-mcpdm.h"
48 struct mcpdm_link_config
{
49 u32 link_mask
; /* channel mask for the direction */
50 u32 threshold
; /* FIFO threshold */
55 unsigned long phys_base
;
56 void __iomem
*io_base
;
62 /* Playback/Capture configuration */
63 struct mcpdm_link_config config
[2];
65 /* McPDM dn offsets for rx1, and 2 channels */
68 /* McPDM needs to be restarted due to runtime reconfiguration */
71 /* pm state for suspend/resume handling */
74 struct snd_dmaengine_dai_dma_data dma_data
[2];
78 * Stream DMA parameters
81 static inline void omap_mcpdm_write(struct omap_mcpdm
*mcpdm
, u16 reg
, u32 val
)
83 writel_relaxed(val
, mcpdm
->io_base
+ reg
);
86 static inline int omap_mcpdm_read(struct omap_mcpdm
*mcpdm
, u16 reg
)
88 return readl_relaxed(mcpdm
->io_base
+ reg
);
92 static void omap_mcpdm_reg_dump(struct omap_mcpdm
*mcpdm
)
94 dev_dbg(mcpdm
->dev
, "***********************\n");
95 dev_dbg(mcpdm
->dev
, "IRQSTATUS_RAW: 0x%04x\n",
96 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQSTATUS_RAW
));
97 dev_dbg(mcpdm
->dev
, "IRQSTATUS: 0x%04x\n",
98 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQSTATUS
));
99 dev_dbg(mcpdm
->dev
, "IRQENABLE_SET: 0x%04x\n",
100 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQENABLE_SET
));
101 dev_dbg(mcpdm
->dev
, "IRQENABLE_CLR: 0x%04x\n",
102 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQENABLE_CLR
));
103 dev_dbg(mcpdm
->dev
, "IRQWAKE_EN: 0x%04x\n",
104 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQWAKE_EN
));
105 dev_dbg(mcpdm
->dev
, "DMAENABLE_SET: 0x%04x\n",
106 omap_mcpdm_read(mcpdm
, MCPDM_REG_DMAENABLE_SET
));
107 dev_dbg(mcpdm
->dev
, "DMAENABLE_CLR: 0x%04x\n",
108 omap_mcpdm_read(mcpdm
, MCPDM_REG_DMAENABLE_CLR
));
109 dev_dbg(mcpdm
->dev
, "DMAWAKEEN: 0x%04x\n",
110 omap_mcpdm_read(mcpdm
, MCPDM_REG_DMAWAKEEN
));
111 dev_dbg(mcpdm
->dev
, "CTRL: 0x%04x\n",
112 omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
));
113 dev_dbg(mcpdm
->dev
, "DN_DATA: 0x%04x\n",
114 omap_mcpdm_read(mcpdm
, MCPDM_REG_DN_DATA
));
115 dev_dbg(mcpdm
->dev
, "UP_DATA: 0x%04x\n",
116 omap_mcpdm_read(mcpdm
, MCPDM_REG_UP_DATA
));
117 dev_dbg(mcpdm
->dev
, "FIFO_CTRL_DN: 0x%04x\n",
118 omap_mcpdm_read(mcpdm
, MCPDM_REG_FIFO_CTRL_DN
));
119 dev_dbg(mcpdm
->dev
, "FIFO_CTRL_UP: 0x%04x\n",
120 omap_mcpdm_read(mcpdm
, MCPDM_REG_FIFO_CTRL_UP
));
121 dev_dbg(mcpdm
->dev
, "***********************\n");
124 static void omap_mcpdm_reg_dump(struct omap_mcpdm
*mcpdm
) {}
128 * Enables the transfer through the PDM interface to/from the Phoenix
129 * codec by enabling the corresponding UP or DN channels.
131 static void omap_mcpdm_start(struct omap_mcpdm
*mcpdm
)
133 u32 ctrl
= omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
);
134 u32 link_mask
= mcpdm
->config
[0].link_mask
| mcpdm
->config
[1].link_mask
;
136 ctrl
|= (MCPDM_SW_DN_RST
| MCPDM_SW_UP_RST
);
137 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
140 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
142 ctrl
&= ~(MCPDM_SW_DN_RST
| MCPDM_SW_UP_RST
);
143 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
147 * Disables the transfer through the PDM interface to/from the Phoenix
148 * codec by disabling the corresponding UP or DN channels.
150 static void omap_mcpdm_stop(struct omap_mcpdm
*mcpdm
)
152 u32 ctrl
= omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
);
153 u32 link_mask
= MCPDM_PDM_DN_MASK
| MCPDM_PDM_UP_MASK
;
155 ctrl
|= (MCPDM_SW_DN_RST
| MCPDM_SW_UP_RST
);
156 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
158 ctrl
&= ~(link_mask
);
159 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
161 ctrl
&= ~(MCPDM_SW_DN_RST
| MCPDM_SW_UP_RST
);
162 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
167 * Is the physical McPDM interface active.
169 static inline int omap_mcpdm_active(struct omap_mcpdm
*mcpdm
)
171 return omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
) &
172 (MCPDM_PDM_DN_MASK
| MCPDM_PDM_UP_MASK
);
176 * Configures McPDM uplink, and downlink for audio.
177 * This function should be called before omap_mcpdm_start.
179 static void omap_mcpdm_open_streams(struct omap_mcpdm
*mcpdm
)
181 u32 ctrl
= omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
);
183 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
| MCPDM_WD_EN
);
185 omap_mcpdm_write(mcpdm
, MCPDM_REG_IRQENABLE_SET
,
186 MCPDM_DN_IRQ_EMPTY
| MCPDM_DN_IRQ_FULL
|
187 MCPDM_UP_IRQ_EMPTY
| MCPDM_UP_IRQ_FULL
);
189 /* Enable DN RX1/2 offset cancellation feature, if configured */
190 if (mcpdm
->dn_rx_offset
) {
191 u32 dn_offset
= mcpdm
->dn_rx_offset
;
193 omap_mcpdm_write(mcpdm
, MCPDM_REG_DN_OFFSET
, dn_offset
);
194 dn_offset
|= (MCPDM_DN_OFST_RX1_EN
| MCPDM_DN_OFST_RX2_EN
);
195 omap_mcpdm_write(mcpdm
, MCPDM_REG_DN_OFFSET
, dn_offset
);
198 omap_mcpdm_write(mcpdm
, MCPDM_REG_FIFO_CTRL_DN
,
199 mcpdm
->config
[SNDRV_PCM_STREAM_PLAYBACK
].threshold
);
200 omap_mcpdm_write(mcpdm
, MCPDM_REG_FIFO_CTRL_UP
,
201 mcpdm
->config
[SNDRV_PCM_STREAM_CAPTURE
].threshold
);
203 omap_mcpdm_write(mcpdm
, MCPDM_REG_DMAENABLE_SET
,
204 MCPDM_DMA_DN_ENABLE
| MCPDM_DMA_UP_ENABLE
);
208 * Cleans McPDM uplink, and downlink configuration.
209 * This function should be called when the stream is closed.
211 static void omap_mcpdm_close_streams(struct omap_mcpdm
*mcpdm
)
213 /* Disable irq request generation for downlink */
214 omap_mcpdm_write(mcpdm
, MCPDM_REG_IRQENABLE_CLR
,
215 MCPDM_DN_IRQ_EMPTY
| MCPDM_DN_IRQ_FULL
);
217 /* Disable DMA request generation for downlink */
218 omap_mcpdm_write(mcpdm
, MCPDM_REG_DMAENABLE_CLR
, MCPDM_DMA_DN_ENABLE
);
220 /* Disable irq request generation for uplink */
221 omap_mcpdm_write(mcpdm
, MCPDM_REG_IRQENABLE_CLR
,
222 MCPDM_UP_IRQ_EMPTY
| MCPDM_UP_IRQ_FULL
);
224 /* Disable DMA request generation for uplink */
225 omap_mcpdm_write(mcpdm
, MCPDM_REG_DMAENABLE_CLR
, MCPDM_DMA_UP_ENABLE
);
227 /* Disable RX1/2 offset cancellation */
228 if (mcpdm
->dn_rx_offset
)
229 omap_mcpdm_write(mcpdm
, MCPDM_REG_DN_OFFSET
, 0);
232 static irqreturn_t
omap_mcpdm_irq_handler(int irq
, void *dev_id
)
234 struct omap_mcpdm
*mcpdm
= dev_id
;
237 irq_status
= omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQSTATUS
);
239 /* Acknowledge irq event */
240 omap_mcpdm_write(mcpdm
, MCPDM_REG_IRQSTATUS
, irq_status
);
242 if (irq_status
& MCPDM_DN_IRQ_FULL
)
243 dev_dbg(mcpdm
->dev
, "DN (playback) FIFO Full\n");
245 if (irq_status
& MCPDM_DN_IRQ_EMPTY
)
246 dev_dbg(mcpdm
->dev
, "DN (playback) FIFO Empty\n");
248 if (irq_status
& MCPDM_DN_IRQ
)
249 dev_dbg(mcpdm
->dev
, "DN (playback) write request\n");
251 if (irq_status
& MCPDM_UP_IRQ_FULL
)
252 dev_dbg(mcpdm
->dev
, "UP (capture) FIFO Full\n");
254 if (irq_status
& MCPDM_UP_IRQ_EMPTY
)
255 dev_dbg(mcpdm
->dev
, "UP (capture) FIFO Empty\n");
257 if (irq_status
& MCPDM_UP_IRQ
)
258 dev_dbg(mcpdm
->dev
, "UP (capture) write request\n");
263 static int omap_mcpdm_dai_startup(struct snd_pcm_substream
*substream
,
264 struct snd_soc_dai
*dai
)
266 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
268 mutex_lock(&mcpdm
->mutex
);
271 omap_mcpdm_open_streams(mcpdm
);
273 mutex_unlock(&mcpdm
->mutex
);
278 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream
*substream
,
279 struct snd_soc_dai
*dai
)
281 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
283 mutex_lock(&mcpdm
->mutex
);
286 if (omap_mcpdm_active(mcpdm
)) {
287 omap_mcpdm_stop(mcpdm
);
288 omap_mcpdm_close_streams(mcpdm
);
289 mcpdm
->config
[0].link_mask
= 0;
290 mcpdm
->config
[1].link_mask
= 0;
294 mutex_unlock(&mcpdm
->mutex
);
297 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream
*substream
,
298 struct snd_pcm_hw_params
*params
,
299 struct snd_soc_dai
*dai
)
301 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
302 int stream
= substream
->stream
;
303 struct snd_dmaengine_dai_dma_data
*dma_data
;
308 channels
= params_channels(params
);
311 if (stream
== SNDRV_PCM_STREAM_CAPTURE
)
312 /* up to 3 channels for capture */
316 if (stream
== SNDRV_PCM_STREAM_CAPTURE
)
317 /* up to 3 channels for capture */
328 /* unsupported number of channels */
332 dma_data
= snd_soc_dai_get_dma_data(dai
, substream
);
334 threshold
= mcpdm
->config
[stream
].threshold
;
335 /* Configure McPDM channels, and DMA packet size */
336 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
339 /* If capture is not running assume a stereo stream to come */
340 if (!mcpdm
->config
[!stream
].link_mask
)
341 mcpdm
->config
[!stream
].link_mask
= 0x3;
344 (MCPDM_DN_THRES_MAX
- threshold
) * channels
;
346 /* If playback is not running assume a stereo stream to come */
347 if (!mcpdm
->config
[!stream
].link_mask
)
348 mcpdm
->config
[!stream
].link_mask
= (0x3 << 3);
350 dma_data
->maxburst
= threshold
* channels
;
353 /* Check if we need to restart McPDM with this stream */
354 if (mcpdm
->config
[stream
].link_mask
&&
355 mcpdm
->config
[stream
].link_mask
!= link_mask
)
356 mcpdm
->restart
= true;
358 mcpdm
->config
[stream
].link_mask
= link_mask
;
363 static int omap_mcpdm_prepare(struct snd_pcm_substream
*substream
,
364 struct snd_soc_dai
*dai
)
366 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
368 if (!omap_mcpdm_active(mcpdm
)) {
369 omap_mcpdm_start(mcpdm
);
370 omap_mcpdm_reg_dump(mcpdm
);
371 } else if (mcpdm
->restart
) {
372 omap_mcpdm_stop(mcpdm
);
373 omap_mcpdm_start(mcpdm
);
374 mcpdm
->restart
= false;
375 omap_mcpdm_reg_dump(mcpdm
);
381 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops
= {
382 .startup
= omap_mcpdm_dai_startup
,
383 .shutdown
= omap_mcpdm_dai_shutdown
,
384 .hw_params
= omap_mcpdm_dai_hw_params
,
385 .prepare
= omap_mcpdm_prepare
,
388 static int omap_mcpdm_probe(struct snd_soc_dai
*dai
)
390 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
393 clk_prepare_enable(mcpdm
->pdmclk
);
394 pm_runtime_enable(mcpdm
->dev
);
396 /* Disable lines while request is ongoing */
397 pm_runtime_get_sync(mcpdm
->dev
);
398 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, 0x00);
400 ret
= devm_request_irq(mcpdm
->dev
, mcpdm
->irq
, omap_mcpdm_irq_handler
,
401 0, "McPDM", (void *)mcpdm
);
403 pm_runtime_put_sync(mcpdm
->dev
);
406 dev_err(mcpdm
->dev
, "Request for IRQ failed\n");
407 pm_runtime_disable(mcpdm
->dev
);
410 /* Configure McPDM threshold values */
411 mcpdm
->config
[SNDRV_PCM_STREAM_PLAYBACK
].threshold
= 2;
412 mcpdm
->config
[SNDRV_PCM_STREAM_CAPTURE
].threshold
=
413 MCPDM_UP_THRES_MAX
- 3;
415 snd_soc_dai_init_dma_data(dai
,
416 &mcpdm
->dma_data
[SNDRV_PCM_STREAM_PLAYBACK
],
417 &mcpdm
->dma_data
[SNDRV_PCM_STREAM_CAPTURE
]);
422 static int omap_mcpdm_remove(struct snd_soc_dai
*dai
)
424 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
426 pm_runtime_disable(mcpdm
->dev
);
428 clk_disable_unprepare(mcpdm
->pdmclk
);
432 #ifdef CONFIG_PM_SLEEP
433 static int omap_mcpdm_suspend(struct snd_soc_dai
*dai
)
435 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
438 omap_mcpdm_stop(mcpdm
);
439 omap_mcpdm_close_streams(mcpdm
);
442 mcpdm
->pm_active_count
= 0;
443 while (pm_runtime_active(mcpdm
->dev
)) {
444 pm_runtime_put_sync(mcpdm
->dev
);
445 mcpdm
->pm_active_count
++;
448 clk_disable_unprepare(mcpdm
->pdmclk
);
453 static int omap_mcpdm_resume(struct snd_soc_dai
*dai
)
455 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
457 clk_prepare_enable(mcpdm
->pdmclk
);
459 if (mcpdm
->pm_active_count
) {
460 while (mcpdm
->pm_active_count
--)
461 pm_runtime_get_sync(mcpdm
->dev
);
464 omap_mcpdm_open_streams(mcpdm
);
465 omap_mcpdm_start(mcpdm
);
473 #define omap_mcpdm_suspend NULL
474 #define omap_mcpdm_resume NULL
477 #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
478 #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
480 static struct snd_soc_dai_driver omap_mcpdm_dai
= {
481 .probe
= omap_mcpdm_probe
,
482 .remove
= omap_mcpdm_remove
,
483 .suspend
= omap_mcpdm_suspend
,
484 .resume
= omap_mcpdm_resume
,
485 .probe_order
= SND_SOC_COMP_ORDER_LATE
,
486 .remove_order
= SND_SOC_COMP_ORDER_EARLY
,
490 .rates
= OMAP_MCPDM_RATES
,
491 .formats
= OMAP_MCPDM_FORMATS
,
497 .rates
= OMAP_MCPDM_RATES
,
498 .formats
= OMAP_MCPDM_FORMATS
,
501 .ops
= &omap_mcpdm_dai_ops
,
504 static const struct snd_soc_component_driver omap_mcpdm_component
= {
505 .name
= "omap-mcpdm",
508 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime
*rtd
,
511 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
513 mcpdm
->dn_rx_offset
= MCPDM_DNOFST_RX1(rx1
) | MCPDM_DNOFST_RX2(rx2
);
515 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets
);
517 static int asoc_mcpdm_probe(struct platform_device
*pdev
)
519 struct omap_mcpdm
*mcpdm
;
520 struct resource
*res
;
523 mcpdm
= devm_kzalloc(&pdev
->dev
, sizeof(struct omap_mcpdm
), GFP_KERNEL
);
527 platform_set_drvdata(pdev
, mcpdm
);
529 mutex_init(&mcpdm
->mutex
);
531 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dma");
535 mcpdm
->dma_data
[0].addr
= res
->start
+ MCPDM_REG_DN_DATA
;
536 mcpdm
->dma_data
[1].addr
= res
->start
+ MCPDM_REG_UP_DATA
;
538 mcpdm
->dma_data
[0].filter_data
= "dn_link";
539 mcpdm
->dma_data
[1].filter_data
= "up_link";
541 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mpu");
542 mcpdm
->io_base
= devm_ioremap_resource(&pdev
->dev
, res
);
543 if (IS_ERR(mcpdm
->io_base
))
544 return PTR_ERR(mcpdm
->io_base
);
546 mcpdm
->irq
= platform_get_irq(pdev
, 0);
550 mcpdm
->dev
= &pdev
->dev
;
552 mcpdm
->pdmclk
= devm_clk_get(&pdev
->dev
, "pdmclk");
553 if (IS_ERR(mcpdm
->pdmclk
)) {
554 if (PTR_ERR(mcpdm
->pdmclk
) == -EPROBE_DEFER
)
555 return -EPROBE_DEFER
;
556 dev_warn(&pdev
->dev
, "Error getting pdmclk (%ld)!\n",
557 PTR_ERR(mcpdm
->pdmclk
));
558 mcpdm
->pdmclk
= NULL
;
561 ret
= devm_snd_soc_register_component(&pdev
->dev
,
562 &omap_mcpdm_component
,
567 return omap_pcm_platform_register(&pdev
->dev
);
570 static const struct of_device_id omap_mcpdm_of_match
[] = {
571 { .compatible
= "ti,omap4-mcpdm", },
574 MODULE_DEVICE_TABLE(of
, omap_mcpdm_of_match
);
576 static struct platform_driver asoc_mcpdm_driver
= {
578 .name
= "omap-mcpdm",
579 .of_match_table
= omap_mcpdm_of_match
,
582 .probe
= asoc_mcpdm_probe
,
585 module_platform_driver(asoc_mcpdm_driver
);
587 MODULE_ALIAS("platform:omap-mcpdm");
588 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
589 MODULE_DESCRIPTION("OMAP PDM SoC Interface");
590 MODULE_LICENSE("GPL");