2 * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
4 * Copyright (C) 2009 - 2011 Texas Instruments
6 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
7 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
8 * Margarita Olaya <magi.olaya@ti.com>
9 * Peter Ujfalusi <peter.ujfalusi@ti.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/interrupt.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/of_device.h>
38 #include <sound/core.h>
39 #include <sound/pcm.h>
40 #include <sound/pcm_params.h>
41 #include <sound/soc.h>
42 #include <sound/dmaengine_pcm.h>
43 #include <sound/omap-pcm.h>
45 #include "omap-mcpdm.h"
47 struct mcpdm_link_config
{
48 u32 link_mask
; /* channel mask for the direction */
49 u32 threshold
; /* FIFO threshold */
54 unsigned long phys_base
;
55 void __iomem
*io_base
;
60 /* Playback/Capture configuration */
61 struct mcpdm_link_config config
[2];
63 /* McPDM dn offsets for rx1, and 2 channels */
66 /* McPDM needs to be restarted due to runtime reconfiguration */
69 struct snd_dmaengine_dai_dma_data dma_data
[2];
73 * Stream DMA parameters
76 static inline void omap_mcpdm_write(struct omap_mcpdm
*mcpdm
, u16 reg
, u32 val
)
78 writel_relaxed(val
, mcpdm
->io_base
+ reg
);
81 static inline int omap_mcpdm_read(struct omap_mcpdm
*mcpdm
, u16 reg
)
83 return readl_relaxed(mcpdm
->io_base
+ reg
);
87 static void omap_mcpdm_reg_dump(struct omap_mcpdm
*mcpdm
)
89 dev_dbg(mcpdm
->dev
, "***********************\n");
90 dev_dbg(mcpdm
->dev
, "IRQSTATUS_RAW: 0x%04x\n",
91 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQSTATUS_RAW
));
92 dev_dbg(mcpdm
->dev
, "IRQSTATUS: 0x%04x\n",
93 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQSTATUS
));
94 dev_dbg(mcpdm
->dev
, "IRQENABLE_SET: 0x%04x\n",
95 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQENABLE_SET
));
96 dev_dbg(mcpdm
->dev
, "IRQENABLE_CLR: 0x%04x\n",
97 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQENABLE_CLR
));
98 dev_dbg(mcpdm
->dev
, "IRQWAKE_EN: 0x%04x\n",
99 omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQWAKE_EN
));
100 dev_dbg(mcpdm
->dev
, "DMAENABLE_SET: 0x%04x\n",
101 omap_mcpdm_read(mcpdm
, MCPDM_REG_DMAENABLE_SET
));
102 dev_dbg(mcpdm
->dev
, "DMAENABLE_CLR: 0x%04x\n",
103 omap_mcpdm_read(mcpdm
, MCPDM_REG_DMAENABLE_CLR
));
104 dev_dbg(mcpdm
->dev
, "DMAWAKEEN: 0x%04x\n",
105 omap_mcpdm_read(mcpdm
, MCPDM_REG_DMAWAKEEN
));
106 dev_dbg(mcpdm
->dev
, "CTRL: 0x%04x\n",
107 omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
));
108 dev_dbg(mcpdm
->dev
, "DN_DATA: 0x%04x\n",
109 omap_mcpdm_read(mcpdm
, MCPDM_REG_DN_DATA
));
110 dev_dbg(mcpdm
->dev
, "UP_DATA: 0x%04x\n",
111 omap_mcpdm_read(mcpdm
, MCPDM_REG_UP_DATA
));
112 dev_dbg(mcpdm
->dev
, "FIFO_CTRL_DN: 0x%04x\n",
113 omap_mcpdm_read(mcpdm
, MCPDM_REG_FIFO_CTRL_DN
));
114 dev_dbg(mcpdm
->dev
, "FIFO_CTRL_UP: 0x%04x\n",
115 omap_mcpdm_read(mcpdm
, MCPDM_REG_FIFO_CTRL_UP
));
116 dev_dbg(mcpdm
->dev
, "***********************\n");
119 static void omap_mcpdm_reg_dump(struct omap_mcpdm
*mcpdm
) {}
123 * Enables the transfer through the PDM interface to/from the Phoenix
124 * codec by enabling the corresponding UP or DN channels.
126 static void omap_mcpdm_start(struct omap_mcpdm
*mcpdm
)
128 u32 ctrl
= omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
);
129 u32 link_mask
= mcpdm
->config
[0].link_mask
| mcpdm
->config
[1].link_mask
;
131 ctrl
|= (MCPDM_SW_DN_RST
| MCPDM_SW_UP_RST
);
132 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
135 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
137 ctrl
&= ~(MCPDM_SW_DN_RST
| MCPDM_SW_UP_RST
);
138 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
142 * Disables the transfer through the PDM interface to/from the Phoenix
143 * codec by disabling the corresponding UP or DN channels.
145 static void omap_mcpdm_stop(struct omap_mcpdm
*mcpdm
)
147 u32 ctrl
= omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
);
148 u32 link_mask
= MCPDM_PDM_DN_MASK
| MCPDM_PDM_UP_MASK
;
150 ctrl
|= (MCPDM_SW_DN_RST
| MCPDM_SW_UP_RST
);
151 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
153 ctrl
&= ~(link_mask
);
154 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
156 ctrl
&= ~(MCPDM_SW_DN_RST
| MCPDM_SW_UP_RST
);
157 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
);
162 * Is the physical McPDM interface active.
164 static inline int omap_mcpdm_active(struct omap_mcpdm
*mcpdm
)
166 return omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
) &
167 (MCPDM_PDM_DN_MASK
| MCPDM_PDM_UP_MASK
);
171 * Configures McPDM uplink, and downlink for audio.
172 * This function should be called before omap_mcpdm_start.
174 static void omap_mcpdm_open_streams(struct omap_mcpdm
*mcpdm
)
176 u32 ctrl
= omap_mcpdm_read(mcpdm
, MCPDM_REG_CTRL
);
178 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, ctrl
| MCPDM_WD_EN
);
180 omap_mcpdm_write(mcpdm
, MCPDM_REG_IRQENABLE_SET
,
181 MCPDM_DN_IRQ_EMPTY
| MCPDM_DN_IRQ_FULL
|
182 MCPDM_UP_IRQ_EMPTY
| MCPDM_UP_IRQ_FULL
);
184 /* Enable DN RX1/2 offset cancellation feature, if configured */
185 if (mcpdm
->dn_rx_offset
) {
186 u32 dn_offset
= mcpdm
->dn_rx_offset
;
188 omap_mcpdm_write(mcpdm
, MCPDM_REG_DN_OFFSET
, dn_offset
);
189 dn_offset
|= (MCPDM_DN_OFST_RX1_EN
| MCPDM_DN_OFST_RX2_EN
);
190 omap_mcpdm_write(mcpdm
, MCPDM_REG_DN_OFFSET
, dn_offset
);
193 omap_mcpdm_write(mcpdm
, MCPDM_REG_FIFO_CTRL_DN
,
194 mcpdm
->config
[SNDRV_PCM_STREAM_PLAYBACK
].threshold
);
195 omap_mcpdm_write(mcpdm
, MCPDM_REG_FIFO_CTRL_UP
,
196 mcpdm
->config
[SNDRV_PCM_STREAM_CAPTURE
].threshold
);
198 omap_mcpdm_write(mcpdm
, MCPDM_REG_DMAENABLE_SET
,
199 MCPDM_DMA_DN_ENABLE
| MCPDM_DMA_UP_ENABLE
);
203 * Cleans McPDM uplink, and downlink configuration.
204 * This function should be called when the stream is closed.
206 static void omap_mcpdm_close_streams(struct omap_mcpdm
*mcpdm
)
208 /* Disable irq request generation for downlink */
209 omap_mcpdm_write(mcpdm
, MCPDM_REG_IRQENABLE_CLR
,
210 MCPDM_DN_IRQ_EMPTY
| MCPDM_DN_IRQ_FULL
);
212 /* Disable DMA request generation for downlink */
213 omap_mcpdm_write(mcpdm
, MCPDM_REG_DMAENABLE_CLR
, MCPDM_DMA_DN_ENABLE
);
215 /* Disable irq request generation for uplink */
216 omap_mcpdm_write(mcpdm
, MCPDM_REG_IRQENABLE_CLR
,
217 MCPDM_UP_IRQ_EMPTY
| MCPDM_UP_IRQ_FULL
);
219 /* Disable DMA request generation for uplink */
220 omap_mcpdm_write(mcpdm
, MCPDM_REG_DMAENABLE_CLR
, MCPDM_DMA_UP_ENABLE
);
222 /* Disable RX1/2 offset cancellation */
223 if (mcpdm
->dn_rx_offset
)
224 omap_mcpdm_write(mcpdm
, MCPDM_REG_DN_OFFSET
, 0);
227 static irqreturn_t
omap_mcpdm_irq_handler(int irq
, void *dev_id
)
229 struct omap_mcpdm
*mcpdm
= dev_id
;
232 irq_status
= omap_mcpdm_read(mcpdm
, MCPDM_REG_IRQSTATUS
);
234 /* Acknowledge irq event */
235 omap_mcpdm_write(mcpdm
, MCPDM_REG_IRQSTATUS
, irq_status
);
237 if (irq_status
& MCPDM_DN_IRQ_FULL
)
238 dev_dbg(mcpdm
->dev
, "DN (playback) FIFO Full\n");
240 if (irq_status
& MCPDM_DN_IRQ_EMPTY
)
241 dev_dbg(mcpdm
->dev
, "DN (playback) FIFO Empty\n");
243 if (irq_status
& MCPDM_DN_IRQ
)
244 dev_dbg(mcpdm
->dev
, "DN (playback) write request\n");
246 if (irq_status
& MCPDM_UP_IRQ_FULL
)
247 dev_dbg(mcpdm
->dev
, "UP (capture) FIFO Full\n");
249 if (irq_status
& MCPDM_UP_IRQ_EMPTY
)
250 dev_dbg(mcpdm
->dev
, "UP (capture) FIFO Empty\n");
252 if (irq_status
& MCPDM_UP_IRQ
)
253 dev_dbg(mcpdm
->dev
, "UP (capture) write request\n");
258 static int omap_mcpdm_dai_startup(struct snd_pcm_substream
*substream
,
259 struct snd_soc_dai
*dai
)
261 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
263 mutex_lock(&mcpdm
->mutex
);
266 omap_mcpdm_open_streams(mcpdm
);
268 mutex_unlock(&mcpdm
->mutex
);
273 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream
*substream
,
274 struct snd_soc_dai
*dai
)
276 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
278 mutex_lock(&mcpdm
->mutex
);
281 if (omap_mcpdm_active(mcpdm
)) {
282 omap_mcpdm_stop(mcpdm
);
283 omap_mcpdm_close_streams(mcpdm
);
284 mcpdm
->config
[0].link_mask
= 0;
285 mcpdm
->config
[1].link_mask
= 0;
289 mutex_unlock(&mcpdm
->mutex
);
292 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream
*substream
,
293 struct snd_pcm_hw_params
*params
,
294 struct snd_soc_dai
*dai
)
296 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
297 int stream
= substream
->stream
;
298 struct snd_dmaengine_dai_dma_data
*dma_data
;
303 channels
= params_channels(params
);
306 if (stream
== SNDRV_PCM_STREAM_CAPTURE
)
307 /* up to 3 channels for capture */
311 if (stream
== SNDRV_PCM_STREAM_CAPTURE
)
312 /* up to 3 channels for capture */
323 /* unsupported number of channels */
327 dma_data
= snd_soc_dai_get_dma_data(dai
, substream
);
329 threshold
= mcpdm
->config
[stream
].threshold
;
330 /* Configure McPDM channels, and DMA packet size */
331 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
334 /* If capture is not running assume a stereo stream to come */
335 if (!mcpdm
->config
[!stream
].link_mask
)
336 mcpdm
->config
[!stream
].link_mask
= 0x3;
339 (MCPDM_DN_THRES_MAX
- threshold
) * channels
;
341 /* If playback is not running assume a stereo stream to come */
342 if (!mcpdm
->config
[!stream
].link_mask
)
343 mcpdm
->config
[!stream
].link_mask
= (0x3 << 3);
345 dma_data
->maxburst
= threshold
* channels
;
348 /* Check if we need to restart McPDM with this stream */
349 if (mcpdm
->config
[stream
].link_mask
&&
350 mcpdm
->config
[stream
].link_mask
!= link_mask
)
351 mcpdm
->restart
= true;
353 mcpdm
->config
[stream
].link_mask
= link_mask
;
358 static int omap_mcpdm_prepare(struct snd_pcm_substream
*substream
,
359 struct snd_soc_dai
*dai
)
361 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
363 if (!omap_mcpdm_active(mcpdm
)) {
364 omap_mcpdm_start(mcpdm
);
365 omap_mcpdm_reg_dump(mcpdm
);
366 } else if (mcpdm
->restart
) {
367 omap_mcpdm_stop(mcpdm
);
368 omap_mcpdm_start(mcpdm
);
369 mcpdm
->restart
= false;
370 omap_mcpdm_reg_dump(mcpdm
);
376 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops
= {
377 .startup
= omap_mcpdm_dai_startup
,
378 .shutdown
= omap_mcpdm_dai_shutdown
,
379 .hw_params
= omap_mcpdm_dai_hw_params
,
380 .prepare
= omap_mcpdm_prepare
,
383 static int omap_mcpdm_probe(struct snd_soc_dai
*dai
)
385 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
388 pm_runtime_enable(mcpdm
->dev
);
390 /* Disable lines while request is ongoing */
391 pm_runtime_get_sync(mcpdm
->dev
);
392 omap_mcpdm_write(mcpdm
, MCPDM_REG_CTRL
, 0x00);
394 ret
= devm_request_irq(mcpdm
->dev
, mcpdm
->irq
, omap_mcpdm_irq_handler
,
395 0, "McPDM", (void *)mcpdm
);
397 pm_runtime_put_sync(mcpdm
->dev
);
400 dev_err(mcpdm
->dev
, "Request for IRQ failed\n");
401 pm_runtime_disable(mcpdm
->dev
);
404 /* Configure McPDM threshold values */
405 mcpdm
->config
[SNDRV_PCM_STREAM_PLAYBACK
].threshold
= 2;
406 mcpdm
->config
[SNDRV_PCM_STREAM_CAPTURE
].threshold
=
407 MCPDM_UP_THRES_MAX
- 3;
409 snd_soc_dai_init_dma_data(dai
,
410 &mcpdm
->dma_data
[SNDRV_PCM_STREAM_PLAYBACK
],
411 &mcpdm
->dma_data
[SNDRV_PCM_STREAM_CAPTURE
]);
416 static int omap_mcpdm_remove(struct snd_soc_dai
*dai
)
418 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(dai
);
420 pm_runtime_disable(mcpdm
->dev
);
425 #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
426 #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
428 static struct snd_soc_dai_driver omap_mcpdm_dai
= {
429 .probe
= omap_mcpdm_probe
,
430 .remove
= omap_mcpdm_remove
,
431 .probe_order
= SND_SOC_COMP_ORDER_LATE
,
432 .remove_order
= SND_SOC_COMP_ORDER_EARLY
,
436 .rates
= OMAP_MCPDM_RATES
,
437 .formats
= OMAP_MCPDM_FORMATS
,
443 .rates
= OMAP_MCPDM_RATES
,
444 .formats
= OMAP_MCPDM_FORMATS
,
447 .ops
= &omap_mcpdm_dai_ops
,
450 static const struct snd_soc_component_driver omap_mcpdm_component
= {
451 .name
= "omap-mcpdm",
454 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime
*rtd
,
457 struct omap_mcpdm
*mcpdm
= snd_soc_dai_get_drvdata(rtd
->cpu_dai
);
459 mcpdm
->dn_rx_offset
= MCPDM_DNOFST_RX1(rx1
) | MCPDM_DNOFST_RX2(rx2
);
461 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets
);
463 static int asoc_mcpdm_probe(struct platform_device
*pdev
)
465 struct omap_mcpdm
*mcpdm
;
466 struct resource
*res
;
469 mcpdm
= devm_kzalloc(&pdev
->dev
, sizeof(struct omap_mcpdm
), GFP_KERNEL
);
473 platform_set_drvdata(pdev
, mcpdm
);
475 mutex_init(&mcpdm
->mutex
);
477 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dma");
481 mcpdm
->dma_data
[0].addr
= res
->start
+ MCPDM_REG_DN_DATA
;
482 mcpdm
->dma_data
[1].addr
= res
->start
+ MCPDM_REG_UP_DATA
;
484 mcpdm
->dma_data
[0].filter_data
= "dn_link";
485 mcpdm
->dma_data
[1].filter_data
= "up_link";
487 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mpu");
488 mcpdm
->io_base
= devm_ioremap_resource(&pdev
->dev
, res
);
489 if (IS_ERR(mcpdm
->io_base
))
490 return PTR_ERR(mcpdm
->io_base
);
492 mcpdm
->irq
= platform_get_irq(pdev
, 0);
496 mcpdm
->dev
= &pdev
->dev
;
498 ret
= devm_snd_soc_register_component(&pdev
->dev
,
499 &omap_mcpdm_component
,
504 return omap_pcm_platform_register(&pdev
->dev
);
507 static const struct of_device_id omap_mcpdm_of_match
[] = {
508 { .compatible
= "ti,omap4-mcpdm", },
511 MODULE_DEVICE_TABLE(of
, omap_mcpdm_of_match
);
513 static struct platform_driver asoc_mcpdm_driver
= {
515 .name
= "omap-mcpdm",
516 .of_match_table
= omap_mcpdm_of_match
,
519 .probe
= asoc_mcpdm_probe
,
522 module_platform_driver(asoc_mcpdm_driver
);
524 MODULE_ALIAS("platform:omap-mcpdm");
525 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
526 MODULE_DESCRIPTION("OMAP PDM SoC Interface");
527 MODULE_LICENSE("GPL");