sound/soc/pxa/pxa-ssp.c

   1 /*
   2  * pxa-ssp.c  --  ALSA Soc Audio Layer
   3  *
   4  * Copyright 2005,2008 Wolfson Microelectronics PLC.
   5  * Author: Liam Girdwood
   6  *         Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  * TODO:
  14  *  o Test network mode for > 16bit sample size
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/slab.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/pxa2xx_ssp.h>
  24
  25 #include <asm/irq.h>
  26
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/initval.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/pxa2xx-lib.h>
  33
  34 #include <mach/hardware.h>
  35 #include <mach/dma.h>
  36 #include <mach/audio.h>
  37
  38 #include "../../arm/pxa2xx-pcm.h"
  39 #include "pxa-ssp.h"
  40
  41 /*
  42  * SSP audio private data
  43  */
  44 struct ssp_priv {
  45         struct ssp_device *ssp;
  46         unsigned int sysclk;
  47         int dai_fmt;
  48 #ifdef CONFIG_PM
  49         uint32_t        cr0;
  50         uint32_t        cr1;
  51         uint32_t        to;
  52         uint32_t        psp;
  53 #endif
  54 };
  55
  56 static void dump_registers(struct ssp_device *ssp)
  57 {
  58         dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
  59                  pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
  60                  pxa_ssp_read_reg(ssp, SSTO));
  61
  62         dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
  63                  pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
  64                  pxa_ssp_read_reg(ssp, SSACD));
  65 }
  66
  67 static void pxa_ssp_enable(struct ssp_device *ssp)
  68 {
  69         uint32_t sscr0;
  70
  71         sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
  72         __raw_writel(sscr0, ssp->mmio_base + SSCR0);
  73 }
  74
  75 static void pxa_ssp_disable(struct ssp_device *ssp)
  76 {
  77         uint32_t sscr0;
  78
  79         sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
  80         __raw_writel(sscr0, ssp->mmio_base + SSCR0);
  81 }
  82
  83 struct pxa2xx_pcm_dma_data {
  84         struct pxa2xx_pcm_dma_params params;
  85         char name[20];
  86 };
  87
  88 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
  89                         int out, struct pxa2xx_pcm_dma_params *dma_data)
  90 {
  91         struct pxa2xx_pcm_dma_data *dma;
  92
  93         dma = container_of(dma_data, struct pxa2xx_pcm_dma_data, params);
  94
  95         snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
  96                         width4 ? "32-bit" : "16-bit", out ? "out" : "in");
  97
  98         dma->params.name = dma->name;
  99         dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
 100         dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
 101                                   (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
 102                         (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
 103         dma->params.dev_addr = ssp->phys_base + SSDR;
 104 }
 105
 106 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
 107                            struct snd_soc_dai *cpu_dai)
 108 {
 109         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 110         struct ssp_device *ssp = priv->ssp;
 111         struct pxa2xx_pcm_dma_data *dma;
 112         int ret = 0;
 113
 114         if (!cpu_dai->active) {
 115                 clk_enable(ssp->clk);
 116                 pxa_ssp_disable(ssp);
 117         }
 118
 119         dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
 120         if (!dma)
 121                 return -ENOMEM;
 122         snd_soc_dai_set_dma_data(cpu_dai, substream, &dma->params);
 123
 124         return ret;
 125 }
 126
 127 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
 128                              struct snd_soc_dai *cpu_dai)
 129 {
 130         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 131         struct ssp_device *ssp = priv->ssp;
 132
 133         if (!cpu_dai->active) {
 134                 pxa_ssp_disable(ssp);
 135                 clk_disable(ssp->clk);
 136         }
 137
 138         kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
 139         snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
 140 }
 141
 142 #ifdef CONFIG_PM
 143
 144 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
 145 {
 146         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 147         struct ssp_device *ssp = priv->ssp;
 148
 149         if (!cpu_dai->active)
 150                 clk_enable(ssp->clk);
 151
 152         priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
 153         priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
 154         priv->to  = __raw_readl(ssp->mmio_base + SSTO);
 155         priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
 156
 157         pxa_ssp_disable(ssp);
 158         clk_disable(ssp->clk);
 159         return 0;
 160 }
 161
 162 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
 163 {
 164         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 165         struct ssp_device *ssp = priv->ssp;
 166         uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
 167
 168         clk_enable(ssp->clk);
 169
 170         __raw_writel(sssr, ssp->mmio_base + SSSR);
 171         __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
 172         __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
 173         __raw_writel(priv->to,  ssp->mmio_base + SSTO);
 174         __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
 175
 176         if (cpu_dai->active)
 177                 pxa_ssp_enable(ssp);
 178         else
 179                 clk_disable(ssp->clk);
 180
 181         return 0;
 182 }
 183
 184 #else
 185 #define pxa_ssp_suspend NULL
 186 #define pxa_ssp_resume  NULL
 187 #endif
 188
 189 /**
 190  * ssp_set_clkdiv - set SSP clock divider
 191  * @div: serial clock rate divider
 192  */
 193 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
 194 {
 195         u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
 196
 197         if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
 198                 sscr0 &= ~0x0000ff00;
 199                 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
 200         } else {
 201                 sscr0 &= ~0x000fff00;
 202                 sscr0 |= (div - 1) << 8;     /* 1..4096 */
 203         }
 204         pxa_ssp_write_reg(ssp, SSCR0, sscr0);
 205 }
 206
 207 /**
 208  * pxa_ssp_get_clkdiv - get SSP clock divider
 209  */
 210 static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
 211 {
 212         u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
 213         u32 div;
 214
 215         if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
 216                 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
 217         else
 218                 div = ((sscr0 >> 8) & 0xfff) + 1;
 219         return div;
 220 }
 221
 222 /*
 223  * Set the SSP ports SYSCLK.
 224  */
 225 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 226         int clk_id, unsigned int freq, int dir)
 227 {
 228         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 229         struct ssp_device *ssp = priv->ssp;
 230         int val;
 231
 232         u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
 233                 ~(SSCR0_ECS |  SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
 234
 235         dev_dbg(&ssp->pdev->dev,
 236                 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
 237                 cpu_dai->id, clk_id, freq);
 238
 239         switch (clk_id) {
 240         case PXA_SSP_CLK_NET_PLL:
 241                 sscr0 |= SSCR0_MOD;
 242                 break;
 243         case PXA_SSP_CLK_PLL:
 244                 /* Internal PLL is fixed */
 245                 if (cpu_is_pxa25x())
 246                         priv->sysclk = 1843200;
 247                 else
 248                         priv->sysclk = 13000000;
 249                 break;
 250         case PXA_SSP_CLK_EXT:
 251                 priv->sysclk = freq;
 252                 sscr0 |= SSCR0_ECS;
 253                 break;
 254         case PXA_SSP_CLK_NET:
 255                 priv->sysclk = freq;
 256                 sscr0 |= SSCR0_NCS | SSCR0_MOD;
 257                 break;
 258         case PXA_SSP_CLK_AUDIO:
 259                 priv->sysclk = 0;
 260                 pxa_ssp_set_scr(ssp, 1);
 261                 sscr0 |= SSCR0_ACS;
 262                 break;
 263         default:
 264                 return -ENODEV;
 265         }
 266
 267         /* The SSP clock must be disabled when changing SSP clock mode
 268          * on PXA2xx.  On PXA3xx it must be enabled when doing so. */
 269         if (!cpu_is_pxa3xx())
 270                 clk_disable(ssp->clk);
 271         val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
 272         pxa_ssp_write_reg(ssp, SSCR0, val);
 273         if (!cpu_is_pxa3xx())
 274                 clk_enable(ssp->clk);
 275
 276         return 0;
 277 }
 278
 279 /*
 280  * Set the SSP clock dividers.
 281  */
 282 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
 283         int div_id, int div)
 284 {
 285         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 286         struct ssp_device *ssp = priv->ssp;
 287         int val;
 288
 289         switch (div_id) {
 290         case PXA_SSP_AUDIO_DIV_ACDS:
 291                 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
 292                 pxa_ssp_write_reg(ssp, SSACD, val);
 293                 break;
 294         case PXA_SSP_AUDIO_DIV_SCDB:
 295                 val = pxa_ssp_read_reg(ssp, SSACD);
 296                 val &= ~SSACD_SCDB;
 297 #if defined(CONFIG_PXA3xx)
 298                 if (cpu_is_pxa3xx())
 299                         val &= ~SSACD_SCDX8;
 300 #endif
 301                 switch (div) {
 302                 case PXA_SSP_CLK_SCDB_1:
 303                         val |= SSACD_SCDB;
 304                         break;
 305                 case PXA_SSP_CLK_SCDB_4:
 306                         break;
 307 #if defined(CONFIG_PXA3xx)
 308                 case PXA_SSP_CLK_SCDB_8:
 309                         if (cpu_is_pxa3xx())
 310                                 val |= SSACD_SCDX8;
 311                         else
 312                                 return -EINVAL;
 313                         break;
 314 #endif
 315                 default:
 316                         return -EINVAL;
 317                 }
 318                 pxa_ssp_write_reg(ssp, SSACD, val);
 319                 break;
 320         case PXA_SSP_DIV_SCR:
 321                 pxa_ssp_set_scr(ssp, div);
 322                 break;
 323         default:
 324                 return -ENODEV;
 325         }
 326
 327         return 0;
 328 }
 329
 330 /*
 331  * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
 332  */
 333 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
 334         int source, unsigned int freq_in, unsigned int freq_out)
 335 {
 336         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 337         struct ssp_device *ssp = priv->ssp;
 338         u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
 339
 340 #if defined(CONFIG_PXA3xx)
 341         if (cpu_is_pxa3xx())
 342                 pxa_ssp_write_reg(ssp, SSACDD, 0);
 343 #endif
 344
 345         switch (freq_out) {
 346         case 5622000:
 347                 break;
 348         case 11345000:
 349                 ssacd |= (0x1 << 4);
 350                 break;
 351         case 12235000:
 352                 ssacd |= (0x2 << 4);
 353                 break;
 354         case 14857000:
 355                 ssacd |= (0x3 << 4);
 356                 break;
 357         case 32842000:
 358                 ssacd |= (0x4 << 4);
 359                 break;
 360         case 48000000:
 361                 ssacd |= (0x5 << 4);
 362                 break;
 363         case 0:
 364                 /* Disable */
 365                 break;
 366
 367         default:
 368 #ifdef CONFIG_PXA3xx
 369                 /* PXA3xx has a clock ditherer which can be used to generate
 370                  * a wider range of frequencies - calculate a value for it.
 371                  */
 372                 if (cpu_is_pxa3xx()) {
 373                         u32 val;
 374                         u64 tmp = 19968;
 375                         tmp *= 1000000;
 376                         do_div(tmp, freq_out);
 377                         val = tmp;
 378
 379                         val = (val << 16) | 64;
 380                         pxa_ssp_write_reg(ssp, SSACDD, val);
 381
 382                         ssacd |= (0x6 << 4);
 383
 384                         dev_dbg(&ssp->pdev->dev,
 385                                 "Using SSACDD %x to supply %uHz\n",
 386                                 val, freq_out);
 387                         break;
 388                 }
 389 #endif
 390
 391                 return -EINVAL;
 392         }
 393
 394         pxa_ssp_write_reg(ssp, SSACD, ssacd);
 395
 396         return 0;
 397 }
 398
 399 /*
 400  * Set the active slots in TDM/Network mode
 401  */
 402 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
 403         unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
 404 {
 405         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 406         struct ssp_device *ssp = priv->ssp;
 407         u32 sscr0;
 408
 409         sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
 410         sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
 411
 412         /* set slot width */
 413         if (slot_width > 16)
 414                 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
 415         else
 416                 sscr0 |= SSCR0_DataSize(slot_width);
 417
 418         if (slots > 1) {
 419                 /* enable network mode */
 420                 sscr0 |= SSCR0_MOD;
 421
 422                 /* set number of active slots */
 423                 sscr0 |= SSCR0_SlotsPerFrm(slots);
 424
 425                 /* set active slot mask */
 426                 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
 427                 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
 428         }
 429         pxa_ssp_write_reg(ssp, SSCR0, sscr0);
 430
 431         return 0;
 432 }
 433
 434 /*
 435  * Tristate the SSP DAI lines
 436  */
 437 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
 438         int tristate)
 439 {
 440         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 441         struct ssp_device *ssp = priv->ssp;
 442         u32 sscr1;
 443
 444         sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
 445         if (tristate)
 446                 sscr1 &= ~SSCR1_TTE;
 447         else
 448                 sscr1 |= SSCR1_TTE;
 449         pxa_ssp_write_reg(ssp, SSCR1, sscr1);
 450
 451         return 0;
 452 }
 453
 454 /*
 455  * Set up the SSP DAI format.
 456  * The SSP Port must be inactive before calling this function as the
 457  * physical interface format is changed.
 458  */
 459 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 460                 unsigned int fmt)
 461 {
 462         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 463         struct ssp_device *ssp = priv->ssp;
 464         u32 sscr0, sscr1, sspsp, scfr;
 465
 466         /* check if we need to change anything at all */
 467         if (priv->dai_fmt == fmt)
 468                 return 0;
 469
 470         /* we can only change the settings if the port is not in use */
 471         if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
 472                 dev_err(&ssp->pdev->dev,
 473                         "can't change hardware dai format: stream is in use");
 474                 return -EINVAL;
 475         }
 476
 477         /* reset port settings */
 478         sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
 479                 ~(SSCR0_ECS |  SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
 480         sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
 481         sspsp = 0;
 482
 483         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 484         case SND_SOC_DAIFMT_CBM_CFM:
 485                 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
 486                 break;
 487         case SND_SOC_DAIFMT_CBM_CFS:
 488                 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
 489                 break;
 490         case SND_SOC_DAIFMT_CBS_CFS:
 491                 break;
 492         default:
 493                 return -EINVAL;
 494         }
 495
 496         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 497         case SND_SOC_DAIFMT_NB_NF:
 498                 sspsp |= SSPSP_SFRMP;
 499                 break;
 500         case SND_SOC_DAIFMT_NB_IF:
 501                 break;
 502         case SND_SOC_DAIFMT_IB_IF:
 503                 sspsp |= SSPSP_SCMODE(2);
 504                 break;
 505         case SND_SOC_DAIFMT_IB_NF:
 506                 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
 507                 break;
 508         default:
 509                 return -EINVAL;
 510         }
 511
 512         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 513         case SND_SOC_DAIFMT_I2S:
 514                 sscr0 |= SSCR0_PSP;
 515                 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
 516                 /* See hw_params() */
 517                 break;
 518
 519         case SND_SOC_DAIFMT_DSP_A:
 520                 sspsp |= SSPSP_FSRT;
 521         case SND_SOC_DAIFMT_DSP_B:
 522                 sscr0 |= SSCR0_MOD | SSCR0_PSP;
 523                 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
 524                 break;
 525
 526         default:
 527                 return -EINVAL;
 528         }
 529
 530         pxa_ssp_write_reg(ssp, SSCR0, sscr0);
 531         pxa_ssp_write_reg(ssp, SSCR1, sscr1);
 532         pxa_ssp_write_reg(ssp, SSPSP, sspsp);
 533
 534         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 535         case SND_SOC_DAIFMT_CBM_CFM:
 536         case SND_SOC_DAIFMT_CBM_CFS:
 537                 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
 538                 pxa_ssp_write_reg(ssp, SSCR1, scfr);
 539
 540                 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
 541                         cpu_relax();
 542                 break;
 543         }
 544
 545         dump_registers(ssp);
 546
 547         /* Since we are configuring the timings for the format by hand
 548          * we have to defer some things until hw_params() where we
 549          * know parameters like the sample size.
 550          */
 551         priv->dai_fmt = fmt;
 552
 553         return 0;
 554 }
 555
 556 /*
 557  * Set the SSP audio DMA parameters and sample size.
 558  * Can be called multiple times by oss emulation.
 559  */
 560 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
 561                                 struct snd_pcm_hw_params *params,
 562                                 struct snd_soc_dai *cpu_dai)
 563 {
 564         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 565         struct ssp_device *ssp = priv->ssp;
 566         int chn = params_channels(params);
 567         u32 sscr0;
 568         u32 sspsp;
 569         int width = snd_pcm_format_physical_width(params_format(params));
 570         int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
 571         struct pxa2xx_pcm_dma_params *dma_data;
 572
 573         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
 574
 575         /* Network mode with one active slot (ttsa == 1) can be used
 576          * to force 16-bit frame width on the wire (for S16_LE), even
 577          * with two channels. Use 16-bit DMA transfers for this case.
 578          */
 579         pxa_ssp_set_dma_params(ssp,
 580                 ((chn == 2) && (ttsa != 1)) || (width == 32),
 581                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
 582
 583         /* we can only change the settings if the port is not in use */
 584         if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
 585                 return 0;
 586
 587         /* clear selected SSP bits */
 588         sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
 589
 590         /* bit size */
 591         switch (params_format(params)) {
 592         case SNDRV_PCM_FORMAT_S16_LE:
 593 #ifdef CONFIG_PXA3xx
 594                 if (cpu_is_pxa3xx())
 595                         sscr0 |= SSCR0_FPCKE;
 596 #endif
 597                 sscr0 |= SSCR0_DataSize(16);
 598                 break;
 599         case SNDRV_PCM_FORMAT_S24_LE:
 600                 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
 601                 break;
 602         case SNDRV_PCM_FORMAT_S32_LE:
 603                 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
 604                 break;
 605         }
 606         pxa_ssp_write_reg(ssp, SSCR0, sscr0);
 607
 608         switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 609         case SND_SOC_DAIFMT_I2S:
 610                sspsp = pxa_ssp_read_reg(ssp, SSPSP);
 611
 612                 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
 613                         /* This is a special case where the bitclk is 64fs
 614                         * and we're not dealing with 2*32 bits of audio
 615                         * samples.
 616                         *
 617                         * The SSP values used for that are all found out by
 618                         * trying and failing a lot; some of the registers
 619                         * needed for that mode are only available on PXA3xx.
 620                         */
 621
 622 #ifdef CONFIG_PXA3xx
 623                         if (!cpu_is_pxa3xx())
 624                                 return -EINVAL;
 625
 626                         sspsp |= SSPSP_SFRMWDTH(width * 2);
 627                         sspsp |= SSPSP_SFRMDLY(width * 4);
 628                         sspsp |= SSPSP_EDMYSTOP(3);
 629                         sspsp |= SSPSP_DMYSTOP(3);
 630                         sspsp |= SSPSP_DMYSTRT(1);
 631 #else
 632                         return -EINVAL;
 633 #endif
 634                 } else {
 635                         /* The frame width is the width the LRCLK is
 636                          * asserted for; the delay is expressed in
 637                          * half cycle units.  We need the extra cycle
 638                          * because the data starts clocking out one BCLK
 639                          * after LRCLK changes polarity.
 640                          */
 641                         sspsp |= SSPSP_SFRMWDTH(width + 1);
 642                         sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
 643                         sspsp |= SSPSP_DMYSTRT(1);
 644                 }
 645
 646                 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
 647                 break;
 648         default:
 649                 break;
 650         }
 651
 652         /* When we use a network mode, we always require TDM slots
 653          * - complain loudly and fail if they've not been set up yet.
 654          */
 655         if ((sscr0 & SSCR0_MOD) && !ttsa) {
 656                 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
 657                 return -EINVAL;
 658         }
 659
 660         dump_registers(ssp);
 661
 662         return 0;
 663 }
 664
 665 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
 666                                     struct ssp_device *ssp, int value)
 667 {
 668         uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
 669         uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
 670         uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
 671         uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
 672
 673         if (value && (sscr0 & SSCR0_SSE))
 674                 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
 675
 676         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 677                 if (value)
 678                         sscr1 |= SSCR1_TSRE;
 679                 else
 680                         sscr1 &= ~SSCR1_TSRE;
 681         } else {
 682                 if (value)
 683                         sscr1 |= SSCR1_RSRE;
 684                 else
 685                         sscr1 &= ~SSCR1_RSRE;
 686         }
 687
 688         pxa_ssp_write_reg(ssp, SSCR1, sscr1);
 689
 690         if (value) {
 691                 pxa_ssp_write_reg(ssp, SSSR, sssr);
 692                 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
 693                 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
 694         }
 695 }
 696
 697 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
 698                            struct snd_soc_dai *cpu_dai)
 699 {
 700         int ret = 0;
 701         struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
 702         struct ssp_device *ssp = priv->ssp;
 703         int val;
 704
 705         switch (cmd) {
 706         case SNDRV_PCM_TRIGGER_RESUME:
 707                 pxa_ssp_enable(ssp);
 708                 break;
 709         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 710                 pxa_ssp_set_running_bit(substream, ssp, 1);
 711                 val = pxa_ssp_read_reg(ssp, SSSR);
 712                 pxa_ssp_write_reg(ssp, SSSR, val);
 713                 break;
 714         case SNDRV_PCM_TRIGGER_START:
 715                 pxa_ssp_set_running_bit(substream, ssp, 1);
 716                 break;
 717         case SNDRV_PCM_TRIGGER_STOP:
 718                 pxa_ssp_set_running_bit(substream, ssp, 0);
 719                 break;
 720         case SNDRV_PCM_TRIGGER_SUSPEND:
 721                 pxa_ssp_disable(ssp);
 722                 break;
 723         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 724                 pxa_ssp_set_running_bit(substream, ssp, 0);
 725                 break;
 726
 727         default:
 728                 ret = -EINVAL;
 729         }
 730
 731         dump_registers(ssp);
 732
 733         return ret;
 734 }
 735
 736 static int pxa_ssp_probe(struct snd_soc_dai *dai)
 737 {
 738         struct ssp_priv *priv;
 739         int ret;
 740
 741         priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
 742         if (!priv)
 743                 return -ENOMEM;
 744
 745         priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
 746         if (priv->ssp == NULL) {
 747                 ret = -ENODEV;
 748                 goto err_priv;
 749         }
 750
 751         priv->dai_fmt = (unsigned int) -1;
 752         snd_soc_dai_set_drvdata(dai, priv);
 753
 754         return 0;
 755
 756 err_priv:
 757         kfree(priv);
 758         return ret;
 759 }
 760
 761 static int pxa_ssp_remove(struct snd_soc_dai *dai)
 762 {
 763         struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
 764
 765         pxa_ssp_free(priv->ssp);
 766         kfree(priv);
 767         return 0;
 768 }
 769
 770 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 771                           SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
 772                           SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
 773                           SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
 774                           SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
 775
 776 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 777                             SNDRV_PCM_FMTBIT_S24_LE |   \
 778                             SNDRV_PCM_FMTBIT_S32_LE)
 779
 780 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
 781         .startup        = pxa_ssp_startup,
 782         .shutdown       = pxa_ssp_shutdown,
 783         .trigger        = pxa_ssp_trigger,
 784         .hw_params      = pxa_ssp_hw_params,
 785         .set_sysclk     = pxa_ssp_set_dai_sysclk,
 786         .set_clkdiv     = pxa_ssp_set_dai_clkdiv,
 787         .set_pll        = pxa_ssp_set_dai_pll,
 788         .set_fmt        = pxa_ssp_set_dai_fmt,
 789         .set_tdm_slot   = pxa_ssp_set_dai_tdm_slot,
 790         .set_tristate   = pxa_ssp_set_dai_tristate,
 791 };
 792
 793 static struct snd_soc_dai_driver pxa_ssp_dai = {
 794                 .probe = pxa_ssp_probe,
 795                 .remove = pxa_ssp_remove,
 796                 .suspend = pxa_ssp_suspend,
 797                 .resume = pxa_ssp_resume,
 798                 .playback = {
 799                         .channels_min = 1,
 800                         .channels_max = 8,
 801                         .rates = PXA_SSP_RATES,
 802                         .formats = PXA_SSP_FORMATS,
 803                 },
 804                 .capture = {
 805                          .channels_min = 1,
 806                          .channels_max = 8,
 807                         .rates = PXA_SSP_RATES,
 808                         .formats = PXA_SSP_FORMATS,
 809                  },
 810                 .ops = &pxa_ssp_dai_ops,
 811 };
 812
 813 static __devinit int asoc_ssp_probe(struct platform_device *pdev)
 814 {
 815         return snd_soc_register_dai(&pdev->dev, &pxa_ssp_dai);
 816 }
 817
 818 static int __devexit asoc_ssp_remove(struct platform_device *pdev)
 819 {
 820         snd_soc_unregister_dai(&pdev->dev);
 821         return 0;
 822 }
 823
 824 static struct platform_driver asoc_ssp_driver = {
 825         .driver = {
 826                         .name = "pxa-ssp-dai",
 827                         .owner = THIS_MODULE,
 828         },
 829
 830         .probe = asoc_ssp_probe,
 831         .remove = __devexit_p(asoc_ssp_remove),
 832 };
 833
 834 module_platform_driver(asoc_ssp_driver);
 835
 836 /* Module information */
 837 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 838 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
 839 MODULE_LICENSE("GPL");