sound/soc/pxa/pxa2xx-ac97.c

   1 /*
   2  * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
   3  *
   4  * Author:      Nicolas Pitre
   5  * Created:     Dec 02, 2004
   6  * Copyright:   MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/wait.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/ac97_codec.h>
  24 #include <sound/initval.h>
  25 #include <sound/soc.h>
  26
  27 #include <asm/irq.h>
  28 #include <linux/mutex.h>
  29 #include <asm/hardware.h>
  30 #include <asm/arch/pxa-regs.h>
  31 #include <asm/arch/pxa2xx-gpio.h>
  32 #include <asm/arch/audio.h>
  33
  34 #include "pxa2xx-pcm.h"
  35 #include "pxa2xx-ac97.h"
  36
  37 static DEFINE_MUTEX(car_mutex);
  38 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  39 static volatile long gsr_bits;
  40 static struct clk *ac97_clk;
  41 #ifdef CONFIG_PXA27x
  42 static struct clk *ac97conf_clk;
  43 #endif
  44
  45 /*
  46  * Beware PXA27x bugs:
  47  *
  48  *   o Slot 12 read from modem space will hang controller.
  49  *   o CDONE, SDONE interrupt fails after any slot 12 IO.
  50  *
  51  * We therefore have an hybrid approach for waiting on SDONE (interrupt or
  52  * 1 jiffy timeout if interrupt never comes).
  53  */
  54
  55 static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97,
  56         unsigned short reg)
  57 {
  58         unsigned short val = -1;
  59         volatile u32 *reg_addr;
  60
  61         mutex_lock(&car_mutex);
  62
  63         /* set up primary or secondary codec/modem space */
  64 #ifdef CONFIG_PXA27x
  65         reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  66 #else
  67         if (reg == AC97_GPIO_STATUS)
  68                 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
  69         else
  70                 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  71 #endif
  72         reg_addr += (reg >> 1);
  73
  74 #ifndef CONFIG_PXA27x
  75         if (reg == AC97_GPIO_STATUS) {
  76                 /* read from controller cache */
  77                 val = *reg_addr;
  78                 goto out;
  79         }
  80 #endif
  81
  82         /* start read access across the ac97 link */
  83         GSR = GSR_CDONE | GSR_SDONE;
  84         gsr_bits = 0;
  85         val = *reg_addr;
  86
  87         wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
  88         if (!((GSR | gsr_bits) & GSR_SDONE)) {
  89                 printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n",
  90                                 __FUNCTION__, reg, GSR | gsr_bits);
  91                 val = -1;
  92                 goto out;
  93         }
  94
  95         /* valid data now */
  96         GSR = GSR_CDONE | GSR_SDONE;
  97         gsr_bits = 0;
  98         val = *reg_addr;
  99         /* but we've just started another cycle... */
 100         wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
 101
 102 out:    mutex_unlock(&car_mutex);
 103         return val;
 104 }
 105
 106 static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
 107         unsigned short val)
 108 {
 109         volatile u32 *reg_addr;
 110
 111         mutex_lock(&car_mutex);
 112
 113         /* set up primary or secondary codec/modem space */
 114 #ifdef CONFIG_PXA27x
 115         reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
 116 #else
 117         if (reg == AC97_GPIO_STATUS)
 118                 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
 119         else
 120                 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
 121 #endif
 122         reg_addr += (reg >> 1);
 123
 124         GSR = GSR_CDONE | GSR_SDONE;
 125         gsr_bits = 0;
 126         *reg_addr = val;
 127         wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1);
 128         if (!((GSR | gsr_bits) & GSR_CDONE))
 129                 printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n",
 130                                 __FUNCTION__, reg, GSR | gsr_bits);
 131
 132         mutex_unlock(&car_mutex);
 133 }
 134
 135 static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
 136 {
 137         gsr_bits = 0;
 138
 139 #ifdef CONFIG_PXA27x
 140         /* warm reset broken on Bulverde,
 141            so manually keep AC97 reset high */
 142         pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
 143         udelay(10);
 144         GCR |= GCR_WARM_RST;
 145         pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
 146         udelay(500);
 147 #else
 148         GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
 149         wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
 150 #endif
 151
 152         if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
 153                 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
 154                                  __FUNCTION__, gsr_bits);
 155
 156         GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
 157         GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
 158 }
 159
 160 static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
 161 {
 162         GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
 163         GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
 164
 165         gsr_bits = 0;
 166 #ifdef CONFIG_PXA27x
 167         /* PXA27x Developers Manual section 13.5.2.2.1 */
 168         clk_enable(ac97conf_clk);
 169         udelay(5);
 170         clk_disable(ac97conf_clk);
 171         GCR = GCR_COLD_RST;
 172         udelay(50);
 173 #else
 174         GCR = GCR_COLD_RST;
 175         GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
 176         wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
 177 #endif
 178
 179         if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
 180                 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
 181                                  __FUNCTION__, gsr_bits);
 182
 183         GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
 184         GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
 185 }
 186
 187 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
 188 {
 189         long status;
 190
 191         status = GSR;
 192         if (status) {
 193                 GSR = status;
 194                 gsr_bits |= status;
 195                 wake_up(&gsr_wq);
 196
 197 #ifdef CONFIG_PXA27x
 198                 /* Although we don't use those we still need to clear them
 199                    since they tend to spuriously trigger when MMC is used
 200                    (hardware bug? go figure)... */
 201                 MISR = MISR_EOC;
 202                 PISR = PISR_EOC;
 203                 MCSR = MCSR_EOC;
 204 #endif
 205
 206                 return IRQ_HANDLED;
 207         }
 208
 209         return IRQ_NONE;
 210 }
 211
 212 struct snd_ac97_bus_ops soc_ac97_ops = {
 213         .read   = pxa2xx_ac97_read,
 214         .write  = pxa2xx_ac97_write,
 215         .warm_reset     = pxa2xx_ac97_warm_reset,
 216         .reset  = pxa2xx_ac97_cold_reset,
 217 };
 218
 219 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
 220         .name                   = "AC97 PCM Stereo out",
 221         .dev_addr               = __PREG(PCDR),
 222         .drcmr                  = &DRCMRTXPCDR,
 223         .dcmd                   = DCMD_INCSRCADDR | DCMD_FLOWTRG |
 224                                   DCMD_BURST32 | DCMD_WIDTH4,
 225 };
 226
 227 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
 228         .name                   = "AC97 PCM Stereo in",
 229         .dev_addr               = __PREG(PCDR),
 230         .drcmr                  = &DRCMRRXPCDR,
 231         .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
 232                                   DCMD_BURST32 | DCMD_WIDTH4,
 233 };
 234
 235 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
 236         .name                   = "AC97 Aux PCM (Slot 5) Mono out",
 237         .dev_addr               = __PREG(MODR),
 238         .drcmr                  = &DRCMRTXMODR,
 239         .dcmd                   = DCMD_INCSRCADDR | DCMD_FLOWTRG |
 240                                   DCMD_BURST16 | DCMD_WIDTH2,
 241 };
 242
 243 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
 244         .name                   = "AC97 Aux PCM (Slot 5) Mono in",
 245         .dev_addr               = __PREG(MODR),
 246         .drcmr                  = &DRCMRRXMODR,
 247         .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
 248                                   DCMD_BURST16 | DCMD_WIDTH2,
 249 };
 250
 251 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = {
 252         .name                   = "AC97 Mic PCM (Slot 6) Mono in",
 253         .dev_addr               = __PREG(MCDR),
 254         .drcmr                  = &DRCMRRXMCDR,
 255         .dcmd                   = DCMD_INCTRGADDR | DCMD_FLOWSRC |
 256                                   DCMD_BURST16 | DCMD_WIDTH2,
 257 };
 258
 259 #ifdef CONFIG_PM
 260 static int pxa2xx_ac97_suspend(struct platform_device *pdev,
 261         struct snd_soc_cpu_dai *dai)
 262 {
 263         GCR |= GCR_ACLINK_OFF;
 264         clk_disable(ac97_clk);
 265         return 0;
 266 }
 267
 268 static int pxa2xx_ac97_resume(struct platform_device *pdev,
 269         struct snd_soc_cpu_dai *dai)
 270 {
 271         pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
 272         pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
 273         pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
 274         pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
 275 #ifdef CONFIG_PXA27x
 276         /* Use GPIO 113 as AC97 Reset on Bulverde */
 277         pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
 278 #endif
 279         clk_enable(ac97_clk);
 280         return 0;
 281 }
 282
 283 #else
 284 #define pxa2xx_ac97_suspend     NULL
 285 #define pxa2xx_ac97_resume      NULL
 286 #endif
 287
 288 static int pxa2xx_ac97_probe(struct platform_device *pdev)
 289 {
 290         int ret;
 291
 292         ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
 293         if (ret < 0)
 294                 goto err;
 295
 296         pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
 297         pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
 298         pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
 299         pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
 300 #ifdef CONFIG_PXA27x
 301         /* Use GPIO 113 as AC97 Reset on Bulverde */
 302         pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
 303
 304         ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK");
 305         if (IS_ERR(ac97conf_clk)) {
 306                 ret = PTR_ERR(ac97conf_clk);
 307                 ac97conf_clk = NULL;
 308                 goto err_irq;
 309         }
 310 #endif
 311         ac97_clk = clk_get(&pdev->dev, "AC97CLK");
 312         if (IS_ERR(ac97_clk)) {
 313                 ret = PTR_ERR(ac97_clk);
 314                 ac97_clk = NULL;
 315                 goto err_irq;
 316         }
 317         return 0;
 318
 319  err_irq:
 320         GCR |= GCR_ACLINK_OFF;
 321 #ifdef CONFIG_PXA27x
 322         if (ac97conf_clk) {
 323                 clk_put(ac97conf_clk);
 324                 ac97conf_clk = NULL;
 325         }
 326 #endif
 327         free_irq(IRQ_AC97, NULL);
 328  err:
 329         return ret;
 330 }
 331
 332 static void pxa2xx_ac97_remove(struct platform_device *pdev)
 333 {
 334         GCR |= GCR_ACLINK_OFF;
 335         free_irq(IRQ_AC97, NULL);
 336 #ifdef CONFIG_PXA27x
 337         clk_put(ac97conf_clk);
 338         ac97conf_clk = NULL;
 339 #endif
 340         clk_disable(ac97_clk);
 341         clk_put(ac97_clk);
 342         ac97_clk = NULL;
 343 }
 344
 345 static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream,
 346                                 struct snd_pcm_hw_params *params)
 347 {
 348         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 349         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 350
 351         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 352                 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out;
 353         else
 354                 cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in;
 355
 356         return 0;
 357 }
 358
 359 static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream,
 360         struct snd_pcm_hw_params *params)
 361 {
 362         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 363         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 364
 365         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 366                 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out;
 367         else
 368                 cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in;
 369
 370         return 0;
 371 }
 372
 373 static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
 374         struct snd_pcm_hw_params *params)
 375 {
 376         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 377         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 378
 379         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 380                 return -ENODEV;
 381         else
 382                 cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in;
 383
 384         return 0;
 385 }
 386
 387 #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 388                 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
 389                 SNDRV_PCM_RATE_48000)
 390
 391 /*
 392  * There is only 1 physical AC97 interface for pxa2xx, but it
 393  * has extra fifo's that can be used for aux DACs and ADCs.
 394  */
 395 struct snd_soc_cpu_dai pxa_ac97_dai[] = {
 396 {
 397         .name = "pxa2xx-ac97",
 398         .id = 0,
 399         .type = SND_SOC_DAI_AC97,
 400         .probe = pxa2xx_ac97_probe,
 401         .remove = pxa2xx_ac97_remove,
 402         .suspend = pxa2xx_ac97_suspend,
 403         .resume = pxa2xx_ac97_resume,
 404         .playback = {
 405                 .stream_name = "AC97 Playback",
 406                 .channels_min = 2,
 407                 .channels_max = 2,
 408                 .rates = PXA2XX_AC97_RATES,
 409                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 410         .capture = {
 411                 .stream_name = "AC97 Capture",
 412                 .channels_min = 2,
 413                 .channels_max = 2,
 414                 .rates = PXA2XX_AC97_RATES,
 415                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 416         .ops = {
 417                 .hw_params = pxa2xx_ac97_hw_params,},
 418 },
 419 {
 420         .name = "pxa2xx-ac97-aux",
 421         .id = 1,
 422         .type = SND_SOC_DAI_AC97,
 423         .playback = {
 424                 .stream_name = "AC97 Aux Playback",
 425                 .channels_min = 1,
 426                 .channels_max = 1,
 427                 .rates = PXA2XX_AC97_RATES,
 428                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 429         .capture = {
 430                 .stream_name = "AC97 Aux Capture",
 431                 .channels_min = 1,
 432                 .channels_max = 1,
 433                 .rates = PXA2XX_AC97_RATES,
 434                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 435         .ops = {
 436                 .hw_params = pxa2xx_ac97_hw_aux_params,},
 437 },
 438 {
 439         .name = "pxa2xx-ac97-mic",
 440         .id = 2,
 441         .type = SND_SOC_DAI_AC97,
 442         .capture = {
 443                 .stream_name = "AC97 Mic Capture",
 444                 .channels_min = 1,
 445                 .channels_max = 1,
 446                 .rates = PXA2XX_AC97_RATES,
 447                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 448         .ops = {
 449                 .hw_params = pxa2xx_ac97_hw_mic_params,},
 450 },
 451 };
 452
 453 EXPORT_SYMBOL_GPL(pxa_ac97_dai);
 454 EXPORT_SYMBOL_GPL(soc_ac97_ops);
 455
 456 MODULE_AUTHOR("Nicolas Pitre");
 457 MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
 458 MODULE_LICENSE("GPL");