1 /* sound/soc/rockchip/rk_spdif.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
7 * Copyright (c) 2015 Collabora Ltd.
8 * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/of_gpio.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22 #include <sound/pcm_params.h>
23 #include <sound/dmaengine_pcm.h>
25 #include "rockchip_spdif.h"
33 #define RK3288_GRF_SOC_CON2 0x24c
41 struct snd_dmaengine_dai_dma_data playback_dma_data
;
43 struct regmap
*regmap
;
46 static const struct of_device_id rk_spdif_match
[] = {
47 { .compatible
= "rockchip,rk3066-spdif",
48 .data
= (void *) RK_SPDIF_RK3066
},
49 { .compatible
= "rockchip,rk3188-spdif",
50 .data
= (void *) RK_SPDIF_RK3188
},
51 { .compatible
= "rockchip,rk3288-spdif",
52 .data
= (void *) RK_SPDIF_RK3288
},
55 MODULE_DEVICE_TABLE(of
, rk_spdif_match
);
57 static int rk_spdif_runtime_suspend(struct device
*dev
)
59 struct rk_spdif_dev
*spdif
= dev_get_drvdata(dev
);
61 clk_disable_unprepare(spdif
->mclk
);
62 clk_disable_unprepare(spdif
->hclk
);
67 static int rk_spdif_runtime_resume(struct device
*dev
)
69 struct rk_spdif_dev
*spdif
= dev_get_drvdata(dev
);
72 ret
= clk_prepare_enable(spdif
->mclk
);
74 dev_err(spdif
->dev
, "mclk clock enable failed %d\n", ret
);
78 ret
= clk_prepare_enable(spdif
->hclk
);
80 dev_err(spdif
->dev
, "hclk clock enable failed %d\n", ret
);
87 static int rk_spdif_hw_params(struct snd_pcm_substream
*substream
,
88 struct snd_pcm_hw_params
*params
,
89 struct snd_soc_dai
*dai
)
91 struct rk_spdif_dev
*spdif
= snd_soc_dai_get_drvdata(dai
);
92 unsigned int val
= SPDIF_CFGR_HALFWORD_ENABLE
;
96 srate
= params_rate(params
);
101 mclk
= 96000 * 128; /* 12288000 hz */
104 mclk
= 44100 * 256; /* 11289600 hz */
107 mclk
= 192000 * 128; /* 24576000 hz */
113 switch (params_format(params
)) {
114 case SNDRV_PCM_FORMAT_S16_LE
:
115 val
|= SPDIF_CFGR_VDW_16
;
117 case SNDRV_PCM_FORMAT_S20_3LE
:
118 val
|= SPDIF_CFGR_VDW_20
;
120 case SNDRV_PCM_FORMAT_S24_LE
:
121 val
|= SPDIF_CFGR_VDW_24
;
127 /* Set clock and calculate divider */
128 ret
= clk_set_rate(spdif
->mclk
, mclk
);
130 dev_err(spdif
->dev
, "Failed to set module clock rate: %d\n",
135 val
|= SPDIF_CFGR_CLK_DIV(mclk
/(srate
* 256));
136 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_CFGR
,
137 SPDIF_CFGR_CLK_DIV_MASK
| SPDIF_CFGR_HALFWORD_ENABLE
|
144 static int rk_spdif_trigger(struct snd_pcm_substream
*substream
,
145 int cmd
, struct snd_soc_dai
*dai
)
147 struct rk_spdif_dev
*spdif
= snd_soc_dai_get_drvdata(dai
);
151 case SNDRV_PCM_TRIGGER_START
:
152 case SNDRV_PCM_TRIGGER_RESUME
:
153 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
154 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_DMACR
,
155 SPDIF_DMACR_TDE_ENABLE
,
156 SPDIF_DMACR_TDE_ENABLE
);
161 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_XFER
,
162 SPDIF_XFER_TXS_START
,
163 SPDIF_XFER_TXS_START
);
165 case SNDRV_PCM_TRIGGER_SUSPEND
:
166 case SNDRV_PCM_TRIGGER_STOP
:
167 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
168 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_DMACR
,
169 SPDIF_DMACR_TDE_ENABLE
,
170 SPDIF_DMACR_TDE_DISABLE
);
175 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_XFER
,
176 SPDIF_XFER_TXS_START
,
177 SPDIF_XFER_TXS_STOP
);
187 static int rk_spdif_dai_probe(struct snd_soc_dai
*dai
)
189 struct rk_spdif_dev
*spdif
= snd_soc_dai_get_drvdata(dai
);
191 dai
->playback_dma_data
= &spdif
->playback_dma_data
;
196 static const struct snd_soc_dai_ops rk_spdif_dai_ops
= {
197 .hw_params
= rk_spdif_hw_params
,
198 .trigger
= rk_spdif_trigger
,
201 static struct snd_soc_dai_driver rk_spdif_dai
= {
202 .probe
= rk_spdif_dai_probe
,
204 .stream_name
= "Playback",
207 .rates
= (SNDRV_PCM_RATE_32000
|
208 SNDRV_PCM_RATE_44100
|
209 SNDRV_PCM_RATE_48000
|
210 SNDRV_PCM_RATE_96000
|
211 SNDRV_PCM_RATE_192000
),
212 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
213 SNDRV_PCM_FMTBIT_S20_3LE
|
214 SNDRV_PCM_FMTBIT_S24_LE
),
216 .ops
= &rk_spdif_dai_ops
,
219 static const struct snd_soc_component_driver rk_spdif_component
= {
220 .name
= "rockchip-spdif",
223 static bool rk_spdif_wr_reg(struct device
*dev
, unsigned int reg
)
237 static bool rk_spdif_rd_reg(struct device
*dev
, unsigned int reg
)
251 static bool rk_spdif_volatile_reg(struct device
*dev
, unsigned int reg
)
262 static const struct regmap_config rk_spdif_regmap_config
= {
266 .max_register
= SPDIF_SMPDR
,
267 .writeable_reg
= rk_spdif_wr_reg
,
268 .readable_reg
= rk_spdif_rd_reg
,
269 .volatile_reg
= rk_spdif_volatile_reg
,
270 .cache_type
= REGCACHE_FLAT
,
273 static int rk_spdif_probe(struct platform_device
*pdev
)
275 struct device_node
*np
= pdev
->dev
.of_node
;
276 struct rk_spdif_dev
*spdif
;
277 const struct of_device_id
*match
;
278 struct resource
*res
;
282 match
= of_match_node(rk_spdif_match
, np
);
283 if (match
->data
== (void *)RK_SPDIF_RK3288
) {
286 grf
= syscon_regmap_lookup_by_phandle(np
, "rockchip,grf");
289 "rockchip_spdif missing 'rockchip,grf' \n");
293 /* Select the 8 channel SPDIF solution on RK3288 as
294 * the 2 channel one does not appear to work
296 regmap_write(grf
, RK3288_GRF_SOC_CON2
, BIT(1) << 16);
299 spdif
= devm_kzalloc(&pdev
->dev
, sizeof(*spdif
), GFP_KERNEL
);
303 spdif
->hclk
= devm_clk_get(&pdev
->dev
, "hclk");
304 if (IS_ERR(spdif
->hclk
)) {
305 dev_err(&pdev
->dev
, "Can't retrieve rk_spdif bus clock\n");
306 return PTR_ERR(spdif
->hclk
);
308 ret
= clk_prepare_enable(spdif
->hclk
);
310 dev_err(spdif
->dev
, "hclock enable failed %d\n", ret
);
314 spdif
->mclk
= devm_clk_get(&pdev
->dev
, "mclk");
315 if (IS_ERR(spdif
->mclk
)) {
316 dev_err(&pdev
->dev
, "Can't retrieve rk_spdif master clock\n");
317 return PTR_ERR(spdif
->mclk
);
320 ret
= clk_prepare_enable(spdif
->mclk
);
322 dev_err(spdif
->dev
, "clock enable failed %d\n", ret
);
326 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
327 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
329 return PTR_ERR(regs
);
331 spdif
->regmap
= devm_regmap_init_mmio_clk(&pdev
->dev
, "hclk", regs
,
332 &rk_spdif_regmap_config
);
333 if (IS_ERR(spdif
->regmap
)) {
335 "Failed to initialise managed register map\n");
336 return PTR_ERR(spdif
->regmap
);
339 spdif
->playback_dma_data
.addr
= res
->start
+ SPDIF_SMPDR
;
340 spdif
->playback_dma_data
.addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
341 spdif
->playback_dma_data
.maxburst
= 4;
343 spdif
->dev
= &pdev
->dev
;
344 dev_set_drvdata(&pdev
->dev
, spdif
);
346 pm_runtime_set_active(&pdev
->dev
);
347 pm_runtime_enable(&pdev
->dev
);
348 pm_request_idle(&pdev
->dev
);
350 ret
= devm_snd_soc_register_component(&pdev
->dev
,
354 dev_err(&pdev
->dev
, "Could not register DAI\n");
358 ret
= devm_snd_dmaengine_pcm_register(&pdev
->dev
, NULL
, 0);
360 dev_err(&pdev
->dev
, "Could not register PCM\n");
367 pm_runtime_disable(&pdev
->dev
);
372 static int rk_spdif_remove(struct platform_device
*pdev
)
374 struct rk_spdif_dev
*spdif
= dev_get_drvdata(&pdev
->dev
);
376 pm_runtime_disable(&pdev
->dev
);
377 if (!pm_runtime_status_suspended(&pdev
->dev
))
378 rk_spdif_runtime_suspend(&pdev
->dev
);
380 clk_disable_unprepare(spdif
->mclk
);
381 clk_disable_unprepare(spdif
->hclk
);
386 static const struct dev_pm_ops rk_spdif_pm_ops
= {
387 SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend
, rk_spdif_runtime_resume
,
391 static struct platform_driver rk_spdif_driver
= {
392 .probe
= rk_spdif_probe
,
393 .remove
= rk_spdif_remove
,
395 .name
= "rockchip-spdif",
396 .of_match_table
= of_match_ptr(rk_spdif_match
),
397 .pm
= &rk_spdif_pm_ops
,
400 module_platform_driver(rk_spdif_driver
);
402 MODULE_ALIAS("platform:rockchip-spdif");
403 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
404 MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
405 MODULE_LICENSE("GPL v2");