1 /* sound/soc/rockchip/rk_spdif.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
7 * Copyright (c) 2015 Collabora Ltd.
8 * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/of_gpio.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22 #include <sound/pcm_params.h>
23 #include <sound/dmaengine_pcm.h>
25 #include "rockchip_spdif.h"
34 #define RK3288_GRF_SOC_CON2 0x24c
42 struct snd_dmaengine_dai_dma_data playback_dma_data
;
44 struct regmap
*regmap
;
47 static const struct of_device_id rk_spdif_match
[] = {
48 { .compatible
= "rockchip,rk3066-spdif",
49 .data
= (void *)RK_SPDIF_RK3066
},
50 { .compatible
= "rockchip,rk3188-spdif",
51 .data
= (void *)RK_SPDIF_RK3188
},
52 { .compatible
= "rockchip,rk3288-spdif",
53 .data
= (void *)RK_SPDIF_RK3288
},
54 { .compatible
= "rockchip,rk3366-spdif",
55 .data
= (void *)RK_SPDIF_RK3366
},
56 { .compatible
= "rockchip,rk3368-spdif",
57 .data
= (void *)RK_SPDIF_RK3366
},
58 { .compatible
= "rockchip,rk3399-spdif",
59 .data
= (void *)RK_SPDIF_RK3366
},
62 MODULE_DEVICE_TABLE(of
, rk_spdif_match
);
64 static int __maybe_unused
rk_spdif_runtime_suspend(struct device
*dev
)
66 struct rk_spdif_dev
*spdif
= dev_get_drvdata(dev
);
68 clk_disable_unprepare(spdif
->mclk
);
69 clk_disable_unprepare(spdif
->hclk
);
74 static int __maybe_unused
rk_spdif_runtime_resume(struct device
*dev
)
76 struct rk_spdif_dev
*spdif
= dev_get_drvdata(dev
);
79 ret
= clk_prepare_enable(spdif
->mclk
);
81 dev_err(spdif
->dev
, "mclk clock enable failed %d\n", ret
);
85 ret
= clk_prepare_enable(spdif
->hclk
);
87 dev_err(spdif
->dev
, "hclk clock enable failed %d\n", ret
);
94 static int rk_spdif_hw_params(struct snd_pcm_substream
*substream
,
95 struct snd_pcm_hw_params
*params
,
96 struct snd_soc_dai
*dai
)
98 struct rk_spdif_dev
*spdif
= snd_soc_dai_get_drvdata(dai
);
99 unsigned int val
= SPDIF_CFGR_HALFWORD_ENABLE
;
103 srate
= params_rate(params
);
108 mclk
= 96000 * 128; /* 12288000 hz */
111 mclk
= 44100 * 256; /* 11289600 hz */
114 mclk
= 192000 * 128; /* 24576000 hz */
120 switch (params_format(params
)) {
121 case SNDRV_PCM_FORMAT_S16_LE
:
122 val
|= SPDIF_CFGR_VDW_16
;
124 case SNDRV_PCM_FORMAT_S20_3LE
:
125 val
|= SPDIF_CFGR_VDW_20
;
127 case SNDRV_PCM_FORMAT_S24_LE
:
128 val
|= SPDIF_CFGR_VDW_24
;
134 /* Set clock and calculate divider */
135 ret
= clk_set_rate(spdif
->mclk
, mclk
);
137 dev_err(spdif
->dev
, "Failed to set module clock rate: %d\n",
142 val
|= SPDIF_CFGR_CLK_DIV(mclk
/(srate
* 256));
143 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_CFGR
,
144 SPDIF_CFGR_CLK_DIV_MASK
| SPDIF_CFGR_HALFWORD_ENABLE
|
151 static int rk_spdif_trigger(struct snd_pcm_substream
*substream
,
152 int cmd
, struct snd_soc_dai
*dai
)
154 struct rk_spdif_dev
*spdif
= snd_soc_dai_get_drvdata(dai
);
158 case SNDRV_PCM_TRIGGER_START
:
159 case SNDRV_PCM_TRIGGER_RESUME
:
160 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
161 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_DMACR
,
162 SPDIF_DMACR_TDE_ENABLE
|
163 SPDIF_DMACR_TDL_MASK
,
164 SPDIF_DMACR_TDE_ENABLE
|
165 SPDIF_DMACR_TDL(16));
170 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_XFER
,
171 SPDIF_XFER_TXS_START
,
172 SPDIF_XFER_TXS_START
);
174 case SNDRV_PCM_TRIGGER_SUSPEND
:
175 case SNDRV_PCM_TRIGGER_STOP
:
176 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
177 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_DMACR
,
178 SPDIF_DMACR_TDE_ENABLE
,
179 SPDIF_DMACR_TDE_DISABLE
);
184 ret
= regmap_update_bits(spdif
->regmap
, SPDIF_XFER
,
185 SPDIF_XFER_TXS_START
,
186 SPDIF_XFER_TXS_STOP
);
196 static int rk_spdif_dai_probe(struct snd_soc_dai
*dai
)
198 struct rk_spdif_dev
*spdif
= snd_soc_dai_get_drvdata(dai
);
200 dai
->playback_dma_data
= &spdif
->playback_dma_data
;
205 static const struct snd_soc_dai_ops rk_spdif_dai_ops
= {
206 .hw_params
= rk_spdif_hw_params
,
207 .trigger
= rk_spdif_trigger
,
210 static struct snd_soc_dai_driver rk_spdif_dai
= {
211 .probe
= rk_spdif_dai_probe
,
213 .stream_name
= "Playback",
216 .rates
= (SNDRV_PCM_RATE_32000
|
217 SNDRV_PCM_RATE_44100
|
218 SNDRV_PCM_RATE_48000
|
219 SNDRV_PCM_RATE_96000
|
220 SNDRV_PCM_RATE_192000
),
221 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
222 SNDRV_PCM_FMTBIT_S20_3LE
|
223 SNDRV_PCM_FMTBIT_S24_LE
),
225 .ops
= &rk_spdif_dai_ops
,
228 static const struct snd_soc_component_driver rk_spdif_component
= {
229 .name
= "rockchip-spdif",
232 static bool rk_spdif_wr_reg(struct device
*dev
, unsigned int reg
)
246 static bool rk_spdif_rd_reg(struct device
*dev
, unsigned int reg
)
260 static bool rk_spdif_volatile_reg(struct device
*dev
, unsigned int reg
)
271 static const struct regmap_config rk_spdif_regmap_config
= {
275 .max_register
= SPDIF_SMPDR
,
276 .writeable_reg
= rk_spdif_wr_reg
,
277 .readable_reg
= rk_spdif_rd_reg
,
278 .volatile_reg
= rk_spdif_volatile_reg
,
279 .cache_type
= REGCACHE_FLAT
,
282 static int rk_spdif_probe(struct platform_device
*pdev
)
284 struct device_node
*np
= pdev
->dev
.of_node
;
285 struct rk_spdif_dev
*spdif
;
286 const struct of_device_id
*match
;
287 struct resource
*res
;
291 match
= of_match_node(rk_spdif_match
, np
);
292 if (match
->data
== (void *)RK_SPDIF_RK3288
) {
295 grf
= syscon_regmap_lookup_by_phandle(np
, "rockchip,grf");
298 "rockchip_spdif missing 'rockchip,grf' \n");
302 /* Select the 8 channel SPDIF solution on RK3288 as
303 * the 2 channel one does not appear to work
305 regmap_write(grf
, RK3288_GRF_SOC_CON2
, BIT(1) << 16);
308 spdif
= devm_kzalloc(&pdev
->dev
, sizeof(*spdif
), GFP_KERNEL
);
312 spdif
->hclk
= devm_clk_get(&pdev
->dev
, "hclk");
313 if (IS_ERR(spdif
->hclk
)) {
314 dev_err(&pdev
->dev
, "Can't retrieve rk_spdif bus clock\n");
315 return PTR_ERR(spdif
->hclk
);
317 ret
= clk_prepare_enable(spdif
->hclk
);
319 dev_err(spdif
->dev
, "hclock enable failed %d\n", ret
);
323 spdif
->mclk
= devm_clk_get(&pdev
->dev
, "mclk");
324 if (IS_ERR(spdif
->mclk
)) {
325 dev_err(&pdev
->dev
, "Can't retrieve rk_spdif master clock\n");
326 return PTR_ERR(spdif
->mclk
);
329 ret
= clk_prepare_enable(spdif
->mclk
);
331 dev_err(spdif
->dev
, "clock enable failed %d\n", ret
);
335 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
336 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
338 return PTR_ERR(regs
);
340 spdif
->regmap
= devm_regmap_init_mmio_clk(&pdev
->dev
, "hclk", regs
,
341 &rk_spdif_regmap_config
);
342 if (IS_ERR(spdif
->regmap
)) {
344 "Failed to initialise managed register map\n");
345 return PTR_ERR(spdif
->regmap
);
348 spdif
->playback_dma_data
.addr
= res
->start
+ SPDIF_SMPDR
;
349 spdif
->playback_dma_data
.addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
350 spdif
->playback_dma_data
.maxburst
= 4;
352 spdif
->dev
= &pdev
->dev
;
353 dev_set_drvdata(&pdev
->dev
, spdif
);
355 pm_runtime_set_active(&pdev
->dev
);
356 pm_runtime_enable(&pdev
->dev
);
357 pm_request_idle(&pdev
->dev
);
359 ret
= devm_snd_soc_register_component(&pdev
->dev
,
363 dev_err(&pdev
->dev
, "Could not register DAI\n");
367 ret
= devm_snd_dmaengine_pcm_register(&pdev
->dev
, NULL
, 0);
369 dev_err(&pdev
->dev
, "Could not register PCM\n");
376 pm_runtime_disable(&pdev
->dev
);
381 static int rk_spdif_remove(struct platform_device
*pdev
)
383 struct rk_spdif_dev
*spdif
= dev_get_drvdata(&pdev
->dev
);
385 pm_runtime_disable(&pdev
->dev
);
386 if (!pm_runtime_status_suspended(&pdev
->dev
))
387 rk_spdif_runtime_suspend(&pdev
->dev
);
389 clk_disable_unprepare(spdif
->mclk
);
390 clk_disable_unprepare(spdif
->hclk
);
395 static const struct dev_pm_ops rk_spdif_pm_ops
= {
396 SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend
, rk_spdif_runtime_resume
,
400 static struct platform_driver rk_spdif_driver
= {
401 .probe
= rk_spdif_probe
,
402 .remove
= rk_spdif_remove
,
404 .name
= "rockchip-spdif",
405 .of_match_table
= of_match_ptr(rk_spdif_match
),
406 .pm
= &rk_spdif_pm_ops
,
409 module_platform_driver(rk_spdif_driver
);
411 MODULE_ALIAS("platform:rockchip-spdif");
412 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
413 MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
414 MODULE_LICENSE("GPL v2");