1 /* sound/soc/s3c24xx/s3c-i2c-v2.c
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/kernel.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
33 #include <plat/regs-s3c2412-iis.h>
35 #include <plat/audio.h>
38 #include "s3c-i2s-v2.h"
40 #define S3C2412_I2S_DEBUG_CON 0
41 #define S3C2412_I2S_DEBUG 0
44 #define DBG(x...) printk(KERN_INFO x)
46 #define DBG(x...) do { } while (0)
49 static inline struct s3c_i2sv2_info
*to_info(struct snd_soc_dai
*cpu_dai
)
51 return cpu_dai
->private_data
;
54 #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
56 #if S3C2412_I2S_DEBUG_CON
57 static void dbg_showcon(const char *fn
, u32 con
)
59 printk(KERN_DEBUG
"%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn
,
60 bit_set(con
, S3C2412_IISCON_LRINDEX
),
61 bit_set(con
, S3C2412_IISCON_TXFIFO_EMPTY
),
62 bit_set(con
, S3C2412_IISCON_RXFIFO_EMPTY
),
63 bit_set(con
, S3C2412_IISCON_TXFIFO_FULL
),
64 bit_set(con
, S3C2412_IISCON_RXFIFO_FULL
));
66 printk(KERN_DEBUG
"%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
68 bit_set(con
, S3C2412_IISCON_TXDMA_PAUSE
),
69 bit_set(con
, S3C2412_IISCON_RXDMA_PAUSE
),
70 bit_set(con
, S3C2412_IISCON_TXCH_PAUSE
),
71 bit_set(con
, S3C2412_IISCON_RXCH_PAUSE
));
72 printk(KERN_DEBUG
"%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn
,
73 bit_set(con
, S3C2412_IISCON_TXDMA_ACTIVE
),
74 bit_set(con
, S3C2412_IISCON_RXDMA_ACTIVE
),
75 bit_set(con
, S3C2412_IISCON_IIS_ACTIVE
));
78 static inline void dbg_showcon(const char *fn
, u32 con
)
84 /* Turn on or off the transmission path. */
85 void s3c2412_snd_txctrl(struct s3c_i2sv2_info
*i2s
, int on
)
87 void __iomem
*regs
= i2s
->regs
;
90 DBG("%s(%d)\n", __func__
, on
);
92 fic
= readl(regs
+ S3C2412_IISFIC
);
93 con
= readl(regs
+ S3C2412_IISCON
);
94 mod
= readl(regs
+ S3C2412_IISMOD
);
96 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__
, con
, mod
, fic
);
99 con
|= S3C2412_IISCON_TXDMA_ACTIVE
| S3C2412_IISCON_IIS_ACTIVE
;
100 con
&= ~S3C2412_IISCON_TXDMA_PAUSE
;
101 con
&= ~S3C2412_IISCON_TXCH_PAUSE
;
103 switch (mod
& S3C2412_IISMOD_MODE_MASK
) {
104 case S3C2412_IISMOD_MODE_TXONLY
:
105 case S3C2412_IISMOD_MODE_TXRX
:
106 /* do nothing, we are in the right mode */
109 case S3C2412_IISMOD_MODE_RXONLY
:
110 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
111 mod
|= S3C2412_IISMOD_MODE_TXRX
;
115 dev_err(i2s
->dev
, "TXEN: Invalid MODE in IISMOD\n");
118 writel(con
, regs
+ S3C2412_IISCON
);
119 writel(mod
, regs
+ S3C2412_IISMOD
);
121 /* Note, we do not have any indication that the FIFO problems
122 * tha the S3C2410/2440 had apply here, so we should be able
123 * to disable the DMA and TX without resetting the FIFOS.
126 con
|= S3C2412_IISCON_TXDMA_PAUSE
;
127 con
|= S3C2412_IISCON_TXCH_PAUSE
;
128 con
&= ~S3C2412_IISCON_TXDMA_ACTIVE
;
130 switch (mod
& S3C2412_IISMOD_MODE_MASK
) {
131 case S3C2412_IISMOD_MODE_TXRX
:
132 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
133 mod
|= S3C2412_IISMOD_MODE_RXONLY
;
136 case S3C2412_IISMOD_MODE_TXONLY
:
137 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
138 con
&= ~S3C2412_IISCON_IIS_ACTIVE
;
142 dev_err(i2s
->dev
, "TXDIS: Invalid MODE in IISMOD\n");
145 writel(mod
, regs
+ S3C2412_IISMOD
);
146 writel(con
, regs
+ S3C2412_IISCON
);
149 fic
= readl(regs
+ S3C2412_IISFIC
);
150 dbg_showcon(__func__
, con
);
151 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__
, con
, mod
, fic
);
153 EXPORT_SYMBOL_GPL(s3c2412_snd_txctrl
);
155 void s3c2412_snd_rxctrl(struct s3c_i2sv2_info
*i2s
, int on
)
157 void __iomem
*regs
= i2s
->regs
;
160 DBG("%s(%d)\n", __func__
, on
);
162 fic
= readl(regs
+ S3C2412_IISFIC
);
163 con
= readl(regs
+ S3C2412_IISCON
);
164 mod
= readl(regs
+ S3C2412_IISMOD
);
166 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__
, con
, mod
, fic
);
169 con
|= S3C2412_IISCON_RXDMA_ACTIVE
| S3C2412_IISCON_IIS_ACTIVE
;
170 con
&= ~S3C2412_IISCON_RXDMA_PAUSE
;
171 con
&= ~S3C2412_IISCON_RXCH_PAUSE
;
173 switch (mod
& S3C2412_IISMOD_MODE_MASK
) {
174 case S3C2412_IISMOD_MODE_TXRX
:
175 case S3C2412_IISMOD_MODE_RXONLY
:
176 /* do nothing, we are in the right mode */
179 case S3C2412_IISMOD_MODE_TXONLY
:
180 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
181 mod
|= S3C2412_IISMOD_MODE_TXRX
;
185 dev_err(i2s
->dev
, "RXEN: Invalid MODE in IISMOD\n");
188 writel(mod
, regs
+ S3C2412_IISMOD
);
189 writel(con
, regs
+ S3C2412_IISCON
);
191 /* See txctrl notes on FIFOs. */
193 con
&= ~S3C2412_IISCON_RXDMA_ACTIVE
;
194 con
|= S3C2412_IISCON_RXDMA_PAUSE
;
195 con
|= S3C2412_IISCON_RXCH_PAUSE
;
197 switch (mod
& S3C2412_IISMOD_MODE_MASK
) {
198 case S3C2412_IISMOD_MODE_RXONLY
:
199 con
&= ~S3C2412_IISCON_IIS_ACTIVE
;
200 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
203 case S3C2412_IISMOD_MODE_TXRX
:
204 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
205 mod
|= S3C2412_IISMOD_MODE_TXONLY
;
209 dev_err(i2s
->dev
, "RXEN: Invalid MODE in IISMOD\n");
212 writel(con
, regs
+ S3C2412_IISCON
);
213 writel(mod
, regs
+ S3C2412_IISMOD
);
216 fic
= readl(regs
+ S3C2412_IISFIC
);
217 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__
, con
, mod
, fic
);
219 EXPORT_SYMBOL_GPL(s3c2412_snd_rxctrl
);
222 * Wait for the LR signal to allow synchronisation to the L/R clock
223 * from the codec. May only be needed for slave mode.
225 static int s3c2412_snd_lrsync(struct s3c_i2sv2_info
*i2s
)
228 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5);
230 DBG("Entered %s\n", __func__
);
233 iiscon
= readl(i2s
->regs
+ S3C2412_IISCON
);
234 if (iiscon
& S3C2412_IISCON_LRINDEX
)
237 if (timeout
< jiffies
) {
238 printk(KERN_ERR
"%s: timeout\n", __func__
);
247 * Set S3C2412 I2S DAI format
249 static int s3c2412_i2s_set_fmt(struct snd_soc_dai
*cpu_dai
,
252 struct s3c_i2sv2_info
*i2s
= to_info(cpu_dai
);
255 DBG("Entered %s\n", __func__
);
257 iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
258 DBG("hw_params r: IISMOD: %x \n", iismod
);
260 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
261 #define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
262 #define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
263 #define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
266 #if defined(CONFIG_PLAT_S3C64XX)
267 /* From Rev1.1 datasheet, we have two master and two slave modes:
269 * 00 = master mode, fed from PCLK
270 * 01 = master mode, fed from CLKAUDIO
271 * 10 = slave mode, using PCLK
272 * 11 = slave mode, using I2SCLK
274 #define IISMOD_MASTER_MASK (1 << 11)
275 #define IISMOD_SLAVE (1 << 11)
276 #define IISMOD_MASTER (0x0)
279 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
280 case SND_SOC_DAIFMT_CBM_CFM
:
282 iismod
&= ~IISMOD_MASTER_MASK
;
283 iismod
|= IISMOD_SLAVE
;
285 case SND_SOC_DAIFMT_CBS_CFS
:
287 iismod
&= ~IISMOD_MASTER_MASK
;
288 iismod
|= IISMOD_MASTER
;
291 DBG("unknwon master/slave format\n");
295 iismod
&= ~S3C2412_IISMOD_SDF_MASK
;
297 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
298 case SND_SOC_DAIFMT_RIGHT_J
:
299 iismod
|= S3C2412_IISMOD_SDF_MSB
;
301 case SND_SOC_DAIFMT_LEFT_J
:
302 iismod
|= S3C2412_IISMOD_SDF_LSB
;
304 case SND_SOC_DAIFMT_I2S
:
305 iismod
|= S3C2412_IISMOD_SDF_IIS
;
308 DBG("Unknown data format\n");
312 writel(iismod
, i2s
->regs
+ S3C2412_IISMOD
);
313 DBG("hw_params w: IISMOD: %x \n", iismod
);
317 static int s3c2412_i2s_hw_params(struct snd_pcm_substream
*substream
,
318 struct snd_pcm_hw_params
*params
,
319 struct snd_soc_dai
*socdai
)
321 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
322 struct snd_soc_dai_link
*dai
= rtd
->dai
;
323 struct s3c_i2sv2_info
*i2s
= to_info(dai
->cpu_dai
);
326 DBG("Entered %s\n", __func__
);
328 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
329 dai
->cpu_dai
->dma_data
= i2s
->dma_playback
;
331 dai
->cpu_dai
->dma_data
= i2s
->dma_capture
;
333 /* Working copies of register */
334 iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
335 DBG("%s: r: IISMOD: %x\n", __func__
, iismod
);
337 switch (params_format(params
)) {
338 case SNDRV_PCM_FORMAT_S8
:
339 iismod
|= S3C2412_IISMOD_8BIT
;
341 case SNDRV_PCM_FORMAT_S16_LE
:
342 iismod
&= ~S3C2412_IISMOD_8BIT
;
346 writel(iismod
, i2s
->regs
+ S3C2412_IISMOD
);
347 DBG("%s: w: IISMOD: %x\n", __func__
, iismod
);
351 static int s3c2412_i2s_trigger(struct snd_pcm_substream
*substream
, int cmd
,
352 struct snd_soc_dai
*dai
)
354 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
355 struct s3c_i2sv2_info
*i2s
= to_info(rtd
->dai
->cpu_dai
);
356 int capture
= (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
);
360 DBG("Entered %s\n", __func__
);
363 case SNDRV_PCM_TRIGGER_START
:
364 /* On start, ensure that the FIFOs are cleared and reset. */
366 writel(capture
? S3C2412_IISFIC_RXFLUSH
: S3C2412_IISFIC_TXFLUSH
,
367 i2s
->regs
+ S3C2412_IISFIC
);
369 /* clear again, just in case */
370 writel(0x0, i2s
->regs
+ S3C2412_IISFIC
);
372 case SNDRV_PCM_TRIGGER_RESUME
:
373 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
375 ret
= s3c2412_snd_lrsync(i2s
);
380 local_irq_save(irqs
);
383 s3c2412_snd_rxctrl(i2s
, 1);
385 s3c2412_snd_txctrl(i2s
, 1);
387 local_irq_restore(irqs
);
390 case SNDRV_PCM_TRIGGER_STOP
:
391 case SNDRV_PCM_TRIGGER_SUSPEND
:
392 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
393 local_irq_save(irqs
);
396 s3c2412_snd_rxctrl(i2s
, 0);
398 s3c2412_snd_txctrl(i2s
, 0);
400 local_irq_restore(irqs
);
412 * Set S3C2412 Clock dividers
414 static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai
*cpu_dai
,
417 struct s3c_i2sv2_info
*i2s
= to_info(cpu_dai
);
420 DBG("%s(%p, %d, %d)\n", __func__
, cpu_dai
, div_id
, div
);
423 case S3C_I2SV2_DIV_BCLK
:
424 reg
= readl(i2s
->regs
+ S3C2412_IISMOD
);
425 reg
&= ~S3C2412_IISMOD_BCLK_MASK
;
426 writel(reg
| div
, i2s
->regs
+ S3C2412_IISMOD
);
428 DBG("%s: MOD=%08x\n", __func__
, readl(i2s
->regs
+ S3C2412_IISMOD
));
431 case S3C_I2SV2_DIV_RCLK
:
433 /* convert value to bit field */
437 div
= S3C2412_IISMOD_RCLK_256FS
;
441 div
= S3C2412_IISMOD_RCLK_384FS
;
445 div
= S3C2412_IISMOD_RCLK_512FS
;
449 div
= S3C2412_IISMOD_RCLK_768FS
;
457 reg
= readl(i2s
->regs
+ S3C2412_IISMOD
);
458 reg
&= ~S3C2412_IISMOD_RCLK_MASK
;
459 writel(reg
| div
, i2s
->regs
+ S3C2412_IISMOD
);
460 DBG("%s: MOD=%08x\n", __func__
, readl(i2s
->regs
+ S3C2412_IISMOD
));
463 case S3C_I2SV2_DIV_PRESCALER
:
465 writel((div
<< 8) | S3C2412_IISPSR_PSREN
,
466 i2s
->regs
+ S3C2412_IISPSR
);
468 writel(0x0, i2s
->regs
+ S3C2412_IISPSR
);
470 DBG("%s: PSR=%08x\n", __func__
, readl(i2s
->regs
+ S3C2412_IISPSR
));
480 /* default table of all avaialable root fs divisors */
481 static unsigned int iis_fs_tab
[] = { 256, 512, 384, 768 };
483 int s3c2412_iis_calc_rate(struct s3c_i2sv2_rate_calc
*info
,
485 unsigned int rate
, struct clk
*clk
)
487 unsigned long clkrate
= clk_get_rate(clk
);
493 signed int deviation
= 0;
494 unsigned int best_fs
= 0;
495 unsigned int best_div
= 0;
496 unsigned int best_rate
= 0;
497 unsigned int best_deviation
= INT_MAX
;
502 for (fs
= 0; fs
< ARRAY_SIZE(iis_fs_tab
); fs
++) {
503 fsdiv
= iis_fs_tab
[fs
];
505 fsclk
= clkrate
/ fsdiv
;
508 if ((fsclk
% rate
) > (rate
/ 2))
514 actual
= clkrate
/ (fsdiv
* div
);
515 deviation
= actual
- rate
;
517 printk(KERN_DEBUG
"%dfs: div %d => result %d, deviation %d\n",
518 fsdiv
, div
, actual
, deviation
);
520 deviation
= abs(deviation
);
522 if (deviation
< best_deviation
) {
526 best_deviation
= deviation
;
533 printk(KERN_DEBUG
"best: fs=%d, div=%d, rate=%d\n",
534 best_fs
, best_div
, best_rate
);
536 info
->fs_div
= best_fs
;
537 info
->clk_div
= best_div
;
541 EXPORT_SYMBOL_GPL(s3c2412_iis_calc_rate
);
543 int s3c_i2sv2_probe(struct platform_device
*pdev
,
544 struct snd_soc_dai
*dai
,
545 struct s3c_i2sv2_info
*i2s
,
548 struct device
*dev
= &pdev
->dev
;
552 /* record our i2s structure for later use in the callbacks */
553 dai
->private_data
= i2s
;
555 i2s
->regs
= ioremap(base
, 0x100);
556 if (i2s
->regs
== NULL
) {
557 dev_err(dev
, "cannot ioremap registers\n");
561 i2s
->iis_pclk
= clk_get(dev
, "iis");
562 if (i2s
->iis_pclk
== NULL
) {
563 DBG("failed to get iis_clock\n");
568 clk_enable(i2s
->iis_pclk
);
570 s3c2412_snd_txctrl(i2s
, 0);
571 s3c2412_snd_rxctrl(i2s
, 0);
576 EXPORT_SYMBOL_GPL(s3c_i2sv2_probe
);
579 static int s3c2412_i2s_suspend(struct snd_soc_dai
*dai
)
581 struct s3c_i2sv2_info
*i2s
= to_info(dai
);
585 i2s
->suspend_iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
586 i2s
->suspend_iiscon
= readl(i2s
->regs
+ S3C2412_IISCON
);
587 i2s
->suspend_iispsr
= readl(i2s
->regs
+ S3C2412_IISPSR
);
589 /* some basic suspend checks */
591 iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
593 if (iismod
& S3C2412_IISCON_RXDMA_ACTIVE
)
594 pr_warning("%s: RXDMA active?\n", __func__
);
596 if (iismod
& S3C2412_IISCON_TXDMA_ACTIVE
)
597 pr_warning("%s: TXDMA active?\n", __func__
);
599 if (iismod
& S3C2412_IISCON_IIS_ACTIVE
)
600 pr_warning("%s: IIS active\n", __func__
);
606 static int s3c2412_i2s_resume(struct snd_soc_dai
*dai
)
608 struct s3c_i2sv2_info
*i2s
= to_info(dai
);
610 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
611 dai
->active
, i2s
->suspend_iismod
, i2s
->suspend_iiscon
);
614 writel(i2s
->suspend_iiscon
, i2s
->regs
+ S3C2412_IISCON
);
615 writel(i2s
->suspend_iismod
, i2s
->regs
+ S3C2412_IISMOD
);
616 writel(i2s
->suspend_iispsr
, i2s
->regs
+ S3C2412_IISPSR
);
618 writel(S3C2412_IISFIC_RXFLUSH
| S3C2412_IISFIC_TXFLUSH
,
619 i2s
->regs
+ S3C2412_IISFIC
);
622 writel(0x0, i2s
->regs
+ S3C2412_IISFIC
);
628 #define s3c2412_i2s_suspend NULL
629 #define s3c2412_i2s_resume NULL
632 int s3c_i2sv2_register_dai(struct snd_soc_dai
*dai
)
634 dai
->ops
.trigger
= s3c2412_i2s_trigger
;
635 dai
->ops
.hw_params
= s3c2412_i2s_hw_params
;
636 dai
->ops
.set_fmt
= s3c2412_i2s_set_fmt
;
637 dai
->ops
.set_clkdiv
= s3c2412_i2s_set_clkdiv
;
639 dai
->suspend
= s3c2412_i2s_suspend
;
640 dai
->resume
= s3c2412_i2s_resume
;
642 return snd_soc_register_dai(dai
);
645 EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai
);