1 /* sound/soc/s3c24xx/s3c-i2c-v2.c
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/kernel.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
33 #include <plat/regs-s3c2412-iis.h>
35 #include <plat/audio.h>
38 #include "s3c-i2s-v2.h"
40 #undef S3C_IIS_V2_SUPPORTED
42 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
43 #define S3C_IIS_V2_SUPPORTED
46 #ifdef CONFIG_PLAT_S3C64XX
47 #define S3C_IIS_V2_SUPPORTED
50 #ifndef S3C_IIS_V2_SUPPORTED
51 #error Unsupported CPU model
54 #define S3C2412_I2S_DEBUG_CON 0
56 static inline struct s3c_i2sv2_info
*to_info(struct snd_soc_dai
*cpu_dai
)
58 return cpu_dai
->private_data
;
61 #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
63 #if S3C2412_I2S_DEBUG_CON
64 static void dbg_showcon(const char *fn
, u32 con
)
66 printk(KERN_DEBUG
"%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn
,
67 bit_set(con
, S3C2412_IISCON_LRINDEX
),
68 bit_set(con
, S3C2412_IISCON_TXFIFO_EMPTY
),
69 bit_set(con
, S3C2412_IISCON_RXFIFO_EMPTY
),
70 bit_set(con
, S3C2412_IISCON_TXFIFO_FULL
),
71 bit_set(con
, S3C2412_IISCON_RXFIFO_FULL
));
73 printk(KERN_DEBUG
"%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
75 bit_set(con
, S3C2412_IISCON_TXDMA_PAUSE
),
76 bit_set(con
, S3C2412_IISCON_RXDMA_PAUSE
),
77 bit_set(con
, S3C2412_IISCON_TXCH_PAUSE
),
78 bit_set(con
, S3C2412_IISCON_RXCH_PAUSE
));
79 printk(KERN_DEBUG
"%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn
,
80 bit_set(con
, S3C2412_IISCON_TXDMA_ACTIVE
),
81 bit_set(con
, S3C2412_IISCON_RXDMA_ACTIVE
),
82 bit_set(con
, S3C2412_IISCON_IIS_ACTIVE
));
85 static inline void dbg_showcon(const char *fn
, u32 con
)
91 /* Turn on or off the transmission path. */
92 void s3c2412_snd_txctrl(struct s3c_i2sv2_info
*i2s
, int on
)
94 void __iomem
*regs
= i2s
->regs
;
97 pr_debug("%s(%d)\n", __func__
, on
);
99 fic
= readl(regs
+ S3C2412_IISFIC
);
100 con
= readl(regs
+ S3C2412_IISCON
);
101 mod
= readl(regs
+ S3C2412_IISMOD
);
103 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__
, con
, mod
, fic
);
106 con
|= S3C2412_IISCON_TXDMA_ACTIVE
| S3C2412_IISCON_IIS_ACTIVE
;
107 con
&= ~S3C2412_IISCON_TXDMA_PAUSE
;
108 con
&= ~S3C2412_IISCON_TXCH_PAUSE
;
110 switch (mod
& S3C2412_IISMOD_MODE_MASK
) {
111 case S3C2412_IISMOD_MODE_TXONLY
:
112 case S3C2412_IISMOD_MODE_TXRX
:
113 /* do nothing, we are in the right mode */
116 case S3C2412_IISMOD_MODE_RXONLY
:
117 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
118 mod
|= S3C2412_IISMOD_MODE_TXRX
;
122 dev_err(i2s
->dev
, "TXEN: Invalid MODE in IISMOD\n");
125 writel(con
, regs
+ S3C2412_IISCON
);
126 writel(mod
, regs
+ S3C2412_IISMOD
);
128 /* Note, we do not have any indication that the FIFO problems
129 * tha the S3C2410/2440 had apply here, so we should be able
130 * to disable the DMA and TX without resetting the FIFOS.
133 con
|= S3C2412_IISCON_TXDMA_PAUSE
;
134 con
|= S3C2412_IISCON_TXCH_PAUSE
;
135 con
&= ~S3C2412_IISCON_TXDMA_ACTIVE
;
137 switch (mod
& S3C2412_IISMOD_MODE_MASK
) {
138 case S3C2412_IISMOD_MODE_TXRX
:
139 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
140 mod
|= S3C2412_IISMOD_MODE_RXONLY
;
143 case S3C2412_IISMOD_MODE_TXONLY
:
144 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
145 con
&= ~S3C2412_IISCON_IIS_ACTIVE
;
149 dev_err(i2s
->dev
, "TXDIS: Invalid MODE in IISMOD\n");
152 writel(mod
, regs
+ S3C2412_IISMOD
);
153 writel(con
, regs
+ S3C2412_IISCON
);
156 fic
= readl(regs
+ S3C2412_IISFIC
);
157 dbg_showcon(__func__
, con
);
158 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__
, con
, mod
, fic
);
160 EXPORT_SYMBOL_GPL(s3c2412_snd_txctrl
);
162 void s3c2412_snd_rxctrl(struct s3c_i2sv2_info
*i2s
, int on
)
164 void __iomem
*regs
= i2s
->regs
;
167 pr_debug("%s(%d)\n", __func__
, on
);
169 fic
= readl(regs
+ S3C2412_IISFIC
);
170 con
= readl(regs
+ S3C2412_IISCON
);
171 mod
= readl(regs
+ S3C2412_IISMOD
);
173 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__
, con
, mod
, fic
);
176 con
|= S3C2412_IISCON_RXDMA_ACTIVE
| S3C2412_IISCON_IIS_ACTIVE
;
177 con
&= ~S3C2412_IISCON_RXDMA_PAUSE
;
178 con
&= ~S3C2412_IISCON_RXCH_PAUSE
;
180 switch (mod
& S3C2412_IISMOD_MODE_MASK
) {
181 case S3C2412_IISMOD_MODE_TXRX
:
182 case S3C2412_IISMOD_MODE_RXONLY
:
183 /* do nothing, we are in the right mode */
186 case S3C2412_IISMOD_MODE_TXONLY
:
187 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
188 mod
|= S3C2412_IISMOD_MODE_TXRX
;
192 dev_err(i2s
->dev
, "RXEN: Invalid MODE in IISMOD\n");
195 writel(mod
, regs
+ S3C2412_IISMOD
);
196 writel(con
, regs
+ S3C2412_IISCON
);
198 /* See txctrl notes on FIFOs. */
200 con
&= ~S3C2412_IISCON_RXDMA_ACTIVE
;
201 con
|= S3C2412_IISCON_RXDMA_PAUSE
;
202 con
|= S3C2412_IISCON_RXCH_PAUSE
;
204 switch (mod
& S3C2412_IISMOD_MODE_MASK
) {
205 case S3C2412_IISMOD_MODE_RXONLY
:
206 con
&= ~S3C2412_IISCON_IIS_ACTIVE
;
207 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
210 case S3C2412_IISMOD_MODE_TXRX
:
211 mod
&= ~S3C2412_IISMOD_MODE_MASK
;
212 mod
|= S3C2412_IISMOD_MODE_TXONLY
;
216 dev_err(i2s
->dev
, "RXEN: Invalid MODE in IISMOD\n");
219 writel(con
, regs
+ S3C2412_IISCON
);
220 writel(mod
, regs
+ S3C2412_IISMOD
);
223 fic
= readl(regs
+ S3C2412_IISFIC
);
224 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__
, con
, mod
, fic
);
226 EXPORT_SYMBOL_GPL(s3c2412_snd_rxctrl
);
229 * Wait for the LR signal to allow synchronisation to the L/R clock
230 * from the codec. May only be needed for slave mode.
232 static int s3c2412_snd_lrsync(struct s3c_i2sv2_info
*i2s
)
235 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5);
237 pr_debug("Entered %s\n", __func__
);
240 iiscon
= readl(i2s
->regs
+ S3C2412_IISCON
);
241 if (iiscon
& S3C2412_IISCON_LRINDEX
)
244 if (timeout
< jiffies
) {
245 printk(KERN_ERR
"%s: timeout\n", __func__
);
254 * Set S3C2412 I2S DAI format
256 static int s3c2412_i2s_set_fmt(struct snd_soc_dai
*cpu_dai
,
259 struct s3c_i2sv2_info
*i2s
= to_info(cpu_dai
);
262 pr_debug("Entered %s\n", __func__
);
264 iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
265 pr_debug("hw_params r: IISMOD: %x \n", iismod
);
267 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
268 #define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
269 #define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
270 #define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
273 #if defined(CONFIG_PLAT_S3C64XX)
274 /* From Rev1.1 datasheet, we have two master and two slave modes:
276 * 00 = master mode, fed from PCLK
277 * 01 = master mode, fed from CLKAUDIO
278 * 10 = slave mode, using PCLK
279 * 11 = slave mode, using I2SCLK
281 #define IISMOD_MASTER_MASK (1 << 11)
282 #define IISMOD_SLAVE (1 << 11)
283 #define IISMOD_MASTER (0 << 11)
286 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
287 case SND_SOC_DAIFMT_CBM_CFM
:
289 iismod
&= ~IISMOD_MASTER_MASK
;
290 iismod
|= IISMOD_SLAVE
;
292 case SND_SOC_DAIFMT_CBS_CFS
:
294 iismod
&= ~IISMOD_MASTER_MASK
;
295 iismod
|= IISMOD_MASTER
;
298 pr_debug("unknwon master/slave format\n");
302 iismod
&= ~S3C2412_IISMOD_SDF_MASK
;
304 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
305 case SND_SOC_DAIFMT_RIGHT_J
:
306 iismod
|= S3C2412_IISMOD_SDF_MSB
;
308 case SND_SOC_DAIFMT_LEFT_J
:
309 iismod
|= S3C2412_IISMOD_SDF_LSB
;
311 case SND_SOC_DAIFMT_I2S
:
312 iismod
|= S3C2412_IISMOD_SDF_IIS
;
315 pr_debug("Unknown data format\n");
319 writel(iismod
, i2s
->regs
+ S3C2412_IISMOD
);
320 pr_debug("hw_params w: IISMOD: %x \n", iismod
);
324 static int s3c2412_i2s_hw_params(struct snd_pcm_substream
*substream
,
325 struct snd_pcm_hw_params
*params
,
326 struct snd_soc_dai
*socdai
)
328 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
329 struct snd_soc_dai_link
*dai
= rtd
->dai
;
330 struct s3c_i2sv2_info
*i2s
= to_info(dai
->cpu_dai
);
333 pr_debug("Entered %s\n", __func__
);
335 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
336 dai
->cpu_dai
->dma_data
= i2s
->dma_playback
;
338 dai
->cpu_dai
->dma_data
= i2s
->dma_capture
;
340 /* Working copies of register */
341 iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
342 pr_debug("%s: r: IISMOD: %x\n", __func__
, iismod
);
344 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
345 switch (params_format(params
)) {
346 case SNDRV_PCM_FORMAT_S8
:
347 iismod
|= S3C2412_IISMOD_8BIT
;
349 case SNDRV_PCM_FORMAT_S16_LE
:
350 iismod
&= ~S3C2412_IISMOD_8BIT
;
355 #ifdef CONFIG_PLAT_S3C64XX
358 switch (params_format(params
)) {
359 case SNDRV_PCM_FORMAT_S8
:
360 /* 8 bit sample, 16fs BCLK */
363 case SNDRV_PCM_FORMAT_S16_LE
:
364 /* 16 bit sample, 32fs BCLK */
366 case SNDRV_PCM_FORMAT_S24_LE
:
367 /* 24 bit sample, 48fs BCLK */
373 writel(iismod
, i2s
->regs
+ S3C2412_IISMOD
);
374 pr_debug("%s: w: IISMOD: %x\n", __func__
, iismod
);
378 static int s3c2412_i2s_trigger(struct snd_pcm_substream
*substream
, int cmd
,
379 struct snd_soc_dai
*dai
)
381 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
382 struct s3c_i2sv2_info
*i2s
= to_info(rtd
->dai
->cpu_dai
);
383 int capture
= (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
);
387 pr_debug("Entered %s\n", __func__
);
390 case SNDRV_PCM_TRIGGER_START
:
391 /* On start, ensure that the FIFOs are cleared and reset. */
393 writel(capture
? S3C2412_IISFIC_RXFLUSH
: S3C2412_IISFIC_TXFLUSH
,
394 i2s
->regs
+ S3C2412_IISFIC
);
396 /* clear again, just in case */
397 writel(0x0, i2s
->regs
+ S3C2412_IISFIC
);
399 case SNDRV_PCM_TRIGGER_RESUME
:
400 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
402 ret
= s3c2412_snd_lrsync(i2s
);
407 local_irq_save(irqs
);
410 s3c2412_snd_rxctrl(i2s
, 1);
412 s3c2412_snd_txctrl(i2s
, 1);
414 local_irq_restore(irqs
);
417 case SNDRV_PCM_TRIGGER_STOP
:
418 case SNDRV_PCM_TRIGGER_SUSPEND
:
419 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
420 local_irq_save(irqs
);
423 s3c2412_snd_rxctrl(i2s
, 0);
425 s3c2412_snd_txctrl(i2s
, 0);
427 local_irq_restore(irqs
);
439 * Set S3C2412 Clock dividers
441 static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai
*cpu_dai
,
444 struct s3c_i2sv2_info
*i2s
= to_info(cpu_dai
);
447 pr_debug("%s(%p, %d, %d)\n", __func__
, cpu_dai
, div_id
, div
);
450 case S3C_I2SV2_DIV_BCLK
:
451 reg
= readl(i2s
->regs
+ S3C2412_IISMOD
);
452 reg
&= ~S3C2412_IISMOD_BCLK_MASK
;
453 writel(reg
| div
, i2s
->regs
+ S3C2412_IISMOD
);
455 pr_debug("%s: MOD=%08x\n", __func__
, readl(i2s
->regs
+ S3C2412_IISMOD
));
458 case S3C_I2SV2_DIV_RCLK
:
460 /* convert value to bit field */
464 div
= S3C2412_IISMOD_RCLK_256FS
;
468 div
= S3C2412_IISMOD_RCLK_384FS
;
472 div
= S3C2412_IISMOD_RCLK_512FS
;
476 div
= S3C2412_IISMOD_RCLK_768FS
;
484 reg
= readl(i2s
->regs
+ S3C2412_IISMOD
);
485 reg
&= ~S3C2412_IISMOD_RCLK_MASK
;
486 writel(reg
| div
, i2s
->regs
+ S3C2412_IISMOD
);
487 pr_debug("%s: MOD=%08x\n", __func__
, readl(i2s
->regs
+ S3C2412_IISMOD
));
490 case S3C_I2SV2_DIV_PRESCALER
:
492 writel((div
<< 8) | S3C2412_IISPSR_PSREN
,
493 i2s
->regs
+ S3C2412_IISPSR
);
495 writel(0x0, i2s
->regs
+ S3C2412_IISPSR
);
497 pr_debug("%s: PSR=%08x\n", __func__
, readl(i2s
->regs
+ S3C2412_IISPSR
));
507 /* default table of all avaialable root fs divisors */
508 static unsigned int iis_fs_tab
[] = { 256, 512, 384, 768 };
510 int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc
*info
,
512 unsigned int rate
, struct clk
*clk
)
514 unsigned long clkrate
= clk_get_rate(clk
);
520 signed int deviation
= 0;
521 unsigned int best_fs
= 0;
522 unsigned int best_div
= 0;
523 unsigned int best_rate
= 0;
524 unsigned int best_deviation
= INT_MAX
;
529 for (fs
= 0; fs
< ARRAY_SIZE(iis_fs_tab
); fs
++) {
530 fsdiv
= iis_fs_tab
[fs
];
532 fsclk
= clkrate
/ fsdiv
;
535 if ((fsclk
% rate
) > (rate
/ 2))
541 actual
= clkrate
/ (fsdiv
* div
);
542 deviation
= actual
- rate
;
544 printk(KERN_DEBUG
"%dfs: div %d => result %d, deviation %d\n",
545 fsdiv
, div
, actual
, deviation
);
547 deviation
= abs(deviation
);
549 if (deviation
< best_deviation
) {
553 best_deviation
= deviation
;
560 printk(KERN_DEBUG
"best: fs=%d, div=%d, rate=%d\n",
561 best_fs
, best_div
, best_rate
);
563 info
->fs_div
= best_fs
;
564 info
->clk_div
= best_div
;
568 EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate
);
570 int s3c_i2sv2_probe(struct platform_device
*pdev
,
571 struct snd_soc_dai
*dai
,
572 struct s3c_i2sv2_info
*i2s
,
575 struct device
*dev
= &pdev
->dev
;
580 /* record our i2s structure for later use in the callbacks */
581 dai
->private_data
= i2s
;
584 struct resource
*res
= platform_get_resource(pdev
,
588 dev_err(dev
, "Unable to get register resource\n");
592 if (!request_mem_region(res
->start
, resource_size(res
),
594 dev_err(dev
, "Unable to request register region\n");
601 i2s
->regs
= ioremap(base
, 0x100);
602 if (i2s
->regs
== NULL
) {
603 dev_err(dev
, "cannot ioremap registers\n");
607 i2s
->iis_pclk
= clk_get(dev
, "iis");
608 if (i2s
->iis_pclk
== NULL
) {
609 dev_err(dev
, "failed to get iis_clock\n");
614 clk_enable(i2s
->iis_pclk
);
616 /* Mark ourselves as in TXRX mode so we can run through our cleanup
617 * process without warnings. */
618 iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
619 iismod
|= S3C2412_IISMOD_MODE_TXRX
;
620 writel(iismod
, i2s
->regs
+ S3C2412_IISMOD
);
621 s3c2412_snd_txctrl(i2s
, 0);
622 s3c2412_snd_rxctrl(i2s
, 0);
626 EXPORT_SYMBOL_GPL(s3c_i2sv2_probe
);
629 static int s3c2412_i2s_suspend(struct snd_soc_dai
*dai
)
631 struct s3c_i2sv2_info
*i2s
= to_info(dai
);
635 i2s
->suspend_iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
636 i2s
->suspend_iiscon
= readl(i2s
->regs
+ S3C2412_IISCON
);
637 i2s
->suspend_iispsr
= readl(i2s
->regs
+ S3C2412_IISPSR
);
639 /* some basic suspend checks */
641 iismod
= readl(i2s
->regs
+ S3C2412_IISMOD
);
643 if (iismod
& S3C2412_IISCON_RXDMA_ACTIVE
)
644 pr_warning("%s: RXDMA active?\n", __func__
);
646 if (iismod
& S3C2412_IISCON_TXDMA_ACTIVE
)
647 pr_warning("%s: TXDMA active?\n", __func__
);
649 if (iismod
& S3C2412_IISCON_IIS_ACTIVE
)
650 pr_warning("%s: IIS active\n", __func__
);
656 static int s3c2412_i2s_resume(struct snd_soc_dai
*dai
)
658 struct s3c_i2sv2_info
*i2s
= to_info(dai
);
660 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
661 dai
->active
, i2s
->suspend_iismod
, i2s
->suspend_iiscon
);
664 writel(i2s
->suspend_iiscon
, i2s
->regs
+ S3C2412_IISCON
);
665 writel(i2s
->suspend_iismod
, i2s
->regs
+ S3C2412_IISMOD
);
666 writel(i2s
->suspend_iispsr
, i2s
->regs
+ S3C2412_IISPSR
);
668 writel(S3C2412_IISFIC_RXFLUSH
| S3C2412_IISFIC_TXFLUSH
,
669 i2s
->regs
+ S3C2412_IISFIC
);
672 writel(0x0, i2s
->regs
+ S3C2412_IISFIC
);
678 #define s3c2412_i2s_suspend NULL
679 #define s3c2412_i2s_resume NULL
682 int s3c_i2sv2_register_dai(struct snd_soc_dai
*dai
)
684 struct snd_soc_dai_ops
*ops
= dai
->ops
;
686 ops
->trigger
= s3c2412_i2s_trigger
;
687 ops
->hw_params
= s3c2412_i2s_hw_params
;
688 ops
->set_fmt
= s3c2412_i2s_set_fmt
;
689 ops
->set_clkdiv
= s3c2412_i2s_set_clkdiv
;
691 dai
->suspend
= s3c2412_i2s_suspend
;
692 dai
->resume
= s3c2412_i2s_resume
;
694 return snd_soc_register_dai(dai
);
696 EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai
);
698 MODULE_LICENSE("GPL");