sound/soc/s3c24xx/s3c24xx-i2s.c

   1 /*
   2  * s3c24xx-i2s.c  --  ALSA Soc Audio Layer
   3  *
   4  * (c) 2006 Wolfson Microelectronics PLC.
   5  * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
   6  *
   7  * Copyright 2004-2005 Simtec Electronics
   8  *      http://armlinux.simtec.co.uk/
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  *  This program is free software; you can redistribute  it and/or modify it
  12  *  under  the terms of  the GNU General  Public License as published by the
  13  *  Free Software Foundation;  either version 2 of the  License, or (at your
  14  *  option) any later version.
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/device.h>
  20 #include <linux/delay.h>
  21 #include <linux/clk.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25
  26 #include <sound/core.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/initval.h>
  30 #include <sound/soc.h>
  31
  32 #include <mach/hardware.h>
  33 #include <mach/regs-gpio.h>
  34 #include <mach/regs-clock.h>
  35
  36 #include <asm/dma.h>
  37 #include <mach/dma.h>
  38
  39 #include <plat/regs-iis.h>
  40
  41 #include "s3c-dma.h"
  42 #include "s3c24xx-i2s.h"
  43
  44 static struct s3c2410_dma_client s3c24xx_dma_client_out = {
  45         .name = "I2S PCM Stereo out"
  46 };
  47
  48 static struct s3c2410_dma_client s3c24xx_dma_client_in = {
  49         .name = "I2S PCM Stereo in"
  50 };
  51
  52 static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
  53         .client         = &s3c24xx_dma_client_out,
  54         .channel        = DMACH_I2S_OUT,
  55         .dma_addr       = S3C2410_PA_IIS + S3C2410_IISFIFO,
  56         .dma_size       = 2,
  57 };
  58
  59 static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
  60         .client         = &s3c24xx_dma_client_in,
  61         .channel        = DMACH_I2S_IN,
  62         .dma_addr       = S3C2410_PA_IIS + S3C2410_IISFIFO,
  63         .dma_size       = 2,
  64 };
  65
  66 struct s3c24xx_i2s_info {
  67         void __iomem    *regs;
  68         struct clk      *iis_clk;
  69         u32             iiscon;
  70         u32             iismod;
  71         u32             iisfcon;
  72         u32             iispsr;
  73 };
  74 static struct s3c24xx_i2s_info s3c24xx_i2s;
  75
  76 static void s3c24xx_snd_txctrl(int on)
  77 {
  78         u32 iisfcon;
  79         u32 iiscon;
  80         u32 iismod;
  81
  82         pr_debug("Entered %s\n", __func__);
  83
  84         iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
  85         iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
  86         iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
  87
  88         pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
  89
  90         if (on) {
  91                 iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
  92                 iiscon  |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
  93                 iiscon  &= ~S3C2410_IISCON_TXIDLE;
  94                 iismod  |= S3C2410_IISMOD_TXMODE;
  95
  96                 writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
  97                 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
  98                 writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
  99         } else {
 100                 /* note, we have to disable the FIFOs otherwise bad things
 101                  * seem to happen when the DMA stops. According to the
 102                  * Samsung supplied kernel, this should allow the DMA
 103                  * engine and FIFOs to reset. If this isn't allowed, the
 104                  * DMA engine will simply freeze randomly.
 105                  */
 106
 107                 iisfcon &= ~S3C2410_IISFCON_TXENABLE;
 108                 iisfcon &= ~S3C2410_IISFCON_TXDMA;
 109                 iiscon  |=  S3C2410_IISCON_TXIDLE;
 110                 iiscon  &= ~S3C2410_IISCON_TXDMAEN;
 111                 iismod  &= ~S3C2410_IISMOD_TXMODE;
 112
 113                 writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
 114                 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
 115                 writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
 116         }
 117
 118         pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
 119 }
 120
 121 static void s3c24xx_snd_rxctrl(int on)
 122 {
 123         u32 iisfcon;
 124         u32 iiscon;
 125         u32 iismod;
 126
 127         pr_debug("Entered %s\n", __func__);
 128
 129         iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
 130         iiscon  = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
 131         iismod  = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
 132
 133         pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
 134
 135         if (on) {
 136                 iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
 137                 iiscon  |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
 138                 iiscon  &= ~S3C2410_IISCON_RXIDLE;
 139                 iismod  |= S3C2410_IISMOD_RXMODE;
 140
 141                 writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
 142                 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
 143                 writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
 144         } else {
 145                 /* note, we have to disable the FIFOs otherwise bad things
 146                  * seem to happen when the DMA stops. According to the
 147                  * Samsung supplied kernel, this should allow the DMA
 148                  * engine and FIFOs to reset. If this isn't allowed, the
 149                  * DMA engine will simply freeze randomly.
 150                  */
 151
 152                 iisfcon &= ~S3C2410_IISFCON_RXENABLE;
 153                 iisfcon &= ~S3C2410_IISFCON_RXDMA;
 154                 iiscon  |= S3C2410_IISCON_RXIDLE;
 155                 iiscon  &= ~S3C2410_IISCON_RXDMAEN;
 156                 iismod  &= ~S3C2410_IISMOD_RXMODE;
 157
 158                 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
 159                 writel(iiscon,  s3c24xx_i2s.regs + S3C2410_IISCON);
 160                 writel(iismod,  s3c24xx_i2s.regs + S3C2410_IISMOD);
 161         }
 162
 163         pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
 164 }
 165
 166 /*
 167  * Wait for the LR signal to allow synchronisation to the L/R clock
 168  * from the codec. May only be needed for slave mode.
 169  */
 170 static int s3c24xx_snd_lrsync(void)
 171 {
 172         u32 iiscon;
 173         int timeout = 50; /* 5ms */
 174
 175         pr_debug("Entered %s\n", __func__);
 176
 177         while (1) {
 178                 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
 179                 if (iiscon & S3C2410_IISCON_LRINDEX)
 180                         break;
 181
 182                 if (!timeout--)
 183                         return -ETIMEDOUT;
 184                 udelay(100);
 185         }
 186
 187         return 0;
 188 }
 189
 190 /*
 191  * Check whether CPU is the master or slave
 192  */
 193 static inline int s3c24xx_snd_is_clkmaster(void)
 194 {
 195         pr_debug("Entered %s\n", __func__);
 196
 197         return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
 198 }
 199
 200 /*
 201  * Set S3C24xx I2S DAI format
 202  */
 203 static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 204                 unsigned int fmt)
 205 {
 206         u32 iismod;
 207
 208         pr_debug("Entered %s\n", __func__);
 209
 210         iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
 211         pr_debug("hw_params r: IISMOD: %x \n", iismod);
 212
 213         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 214         case SND_SOC_DAIFMT_CBM_CFM:
 215                 iismod |= S3C2410_IISMOD_SLAVE;
 216                 break;
 217         case SND_SOC_DAIFMT_CBS_CFS:
 218                 iismod &= ~S3C2410_IISMOD_SLAVE;
 219                 break;
 220         default:
 221                 return -EINVAL;
 222         }
 223
 224         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 225         case SND_SOC_DAIFMT_LEFT_J:
 226                 iismod |= S3C2410_IISMOD_MSB;
 227                 break;
 228         case SND_SOC_DAIFMT_I2S:
 229                 iismod &= ~S3C2410_IISMOD_MSB;
 230                 break;
 231         default:
 232                 return -EINVAL;
 233         }
 234
 235         writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
 236         pr_debug("hw_params w: IISMOD: %x \n", iismod);
 237         return 0;
 238 }
 239
 240 static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
 241                                  struct snd_pcm_hw_params *params,
 242                                  struct snd_soc_dai *dai)
 243 {
 244         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 245         u32 iismod;
 246
 247         pr_debug("Entered %s\n", __func__);
 248
 249         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 250                 rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
 251         else
 252                 rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
 253
 254         /* Working copies of register */
 255         iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
 256         pr_debug("hw_params r: IISMOD: %x\n", iismod);
 257
 258         switch (params_format(params)) {
 259         case SNDRV_PCM_FORMAT_S8:
 260                 iismod &= ~S3C2410_IISMOD_16BIT;
 261                 ((struct s3c_dma_params *)
 262                   rtd->dai->cpu_dai->dma_data)->dma_size = 1;
 263                 break;
 264         case SNDRV_PCM_FORMAT_S16_LE:
 265                 iismod |= S3C2410_IISMOD_16BIT;
 266                 ((struct s3c_dma_params *)
 267                   rtd->dai->cpu_dai->dma_data)->dma_size = 2;
 268                 break;
 269         default:
 270                 return -EINVAL;
 271         }
 272
 273         writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
 274         pr_debug("hw_params w: IISMOD: %x\n", iismod);
 275         return 0;
 276 }
 277
 278 static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 279                                struct snd_soc_dai *dai)
 280 {
 281         int ret = 0;
 282         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 283         int channel = ((struct s3c_dma_params *)
 284                   rtd->dai->cpu_dai->dma_data)->channel;
 285
 286         pr_debug("Entered %s\n", __func__);
 287
 288         switch (cmd) {
 289         case SNDRV_PCM_TRIGGER_START:
 290         case SNDRV_PCM_TRIGGER_RESUME:
 291         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 292                 if (!s3c24xx_snd_is_clkmaster()) {
 293                         ret = s3c24xx_snd_lrsync();
 294                         if (ret)
 295                                 goto exit_err;
 296                 }
 297
 298                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 299                         s3c24xx_snd_rxctrl(1);
 300                 else
 301                         s3c24xx_snd_txctrl(1);
 302
 303                 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
 304                 break;
 305         case SNDRV_PCM_TRIGGER_STOP:
 306         case SNDRV_PCM_TRIGGER_SUSPEND:
 307         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 308                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 309                         s3c24xx_snd_rxctrl(0);
 310                 else
 311                         s3c24xx_snd_txctrl(0);
 312                 break;
 313         default:
 314                 ret = -EINVAL;
 315                 break;
 316         }
 317
 318 exit_err:
 319         return ret;
 320 }
 321
 322 /*
 323  * Set S3C24xx Clock source
 324  */
 325 static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 326         int clk_id, unsigned int freq, int dir)
 327 {
 328         u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
 329
 330         pr_debug("Entered %s\n", __func__);
 331
 332         iismod &= ~S3C2440_IISMOD_MPLL;
 333
 334         switch (clk_id) {
 335         case S3C24XX_CLKSRC_PCLK:
 336                 break;
 337         case S3C24XX_CLKSRC_MPLL:
 338                 iismod |= S3C2440_IISMOD_MPLL;
 339                 break;
 340         default:
 341                 return -EINVAL;
 342         }
 343
 344         writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
 345         return 0;
 346 }
 347
 348 /*
 349  * Set S3C24xx Clock dividers
 350  */
 351 static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
 352         int div_id, int div)
 353 {
 354         u32 reg;
 355
 356         pr_debug("Entered %s\n", __func__);
 357
 358         switch (div_id) {
 359         case S3C24XX_DIV_BCLK:
 360                 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
 361                 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
 362                 break;
 363         case S3C24XX_DIV_MCLK:
 364                 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
 365                 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
 366                 break;
 367         case S3C24XX_DIV_PRESCALER:
 368                 writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
 369                 reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
 370                 writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
 371                 break;
 372         default:
 373                 return -EINVAL;
 374         }
 375
 376         return 0;
 377 }
 378
 379 /*
 380  * To avoid duplicating clock code, allow machine driver to
 381  * get the clockrate from here.
 382  */
 383 u32 s3c24xx_i2s_get_clockrate(void)
 384 {
 385         return clk_get_rate(s3c24xx_i2s.iis_clk);
 386 }
 387 EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
 388
 389 static int s3c24xx_i2s_probe(struct platform_device *pdev,
 390                              struct snd_soc_dai *dai)
 391 {
 392         pr_debug("Entered %s\n", __func__);
 393
 394         s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
 395         if (s3c24xx_i2s.regs == NULL)
 396                 return -ENXIO;
 397
 398         s3c24xx_i2s.iis_clk = clk_get(&pdev->dev, "iis");
 399         if (s3c24xx_i2s.iis_clk == NULL) {
 400                 pr_err("failed to get iis_clock\n");
 401                 iounmap(s3c24xx_i2s.regs);
 402                 return -ENODEV;
 403         }
 404         clk_enable(s3c24xx_i2s.iis_clk);
 405
 406         /* Configure the I2S pins in correct mode */
 407         s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
 408         s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
 409         s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
 410         s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
 411         s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
 412
 413         writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
 414
 415         s3c24xx_snd_txctrl(0);
 416         s3c24xx_snd_rxctrl(0);
 417
 418         return 0;
 419 }
 420
 421 #ifdef CONFIG_PM
 422 static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
 423 {
 424         pr_debug("Entered %s\n", __func__);
 425
 426         s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
 427         s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
 428         s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
 429         s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
 430
 431         clk_disable(s3c24xx_i2s.iis_clk);
 432
 433         return 0;
 434 }
 435
 436 static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
 437 {
 438         pr_debug("Entered %s\n", __func__);
 439         clk_enable(s3c24xx_i2s.iis_clk);
 440
 441         writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
 442         writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
 443         writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
 444         writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
 445
 446         return 0;
 447 }
 448 #else
 449 #define s3c24xx_i2s_suspend NULL
 450 #define s3c24xx_i2s_resume NULL
 451 #endif
 452
 453
 454 #define S3C24XX_I2S_RATES \
 455         (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
 456         SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
 457         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
 458
 459 static struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
 460         .trigger        = s3c24xx_i2s_trigger,
 461         .hw_params      = s3c24xx_i2s_hw_params,
 462         .set_fmt        = s3c24xx_i2s_set_fmt,
 463         .set_clkdiv     = s3c24xx_i2s_set_clkdiv,
 464         .set_sysclk     = s3c24xx_i2s_set_sysclk,
 465 };
 466
 467 struct snd_soc_dai s3c24xx_i2s_dai = {
 468         .name = "s3c24xx-i2s",
 469         .id = 0,
 470         .probe = s3c24xx_i2s_probe,
 471         .suspend = s3c24xx_i2s_suspend,
 472         .resume = s3c24xx_i2s_resume,
 473         .playback = {
 474                 .channels_min = 2,
 475                 .channels_max = 2,
 476                 .rates = S3C24XX_I2S_RATES,
 477                 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
 478         .capture = {
 479                 .channels_min = 2,
 480                 .channels_max = 2,
 481                 .rates = S3C24XX_I2S_RATES,
 482                 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
 483         .ops = &s3c24xx_i2s_dai_ops,
 484 };
 485 EXPORT_SYMBOL_GPL(s3c24xx_i2s_dai);
 486
 487 static int __init s3c24xx_i2s_init(void)
 488 {
 489         return snd_soc_register_dai(&s3c24xx_i2s_dai);
 490 }
 491 module_init(s3c24xx_i2s_init);
 492
 493 static void __exit s3c24xx_i2s_exit(void)
 494 {
 495         snd_soc_unregister_dai(&s3c24xx_i2s_dai);
 496 }
 497 module_exit(s3c24xx_i2s_exit);
 498
 499 /* Module information */
 500 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
 501 MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
 502 MODULE_LICENSE("GPL");