sound/soc/samsung/pcm.c

   1 /* sound/soc/samsung/pcm.c
   2  *
   3  * ALSA SoC Audio Layer - S3C PCM-Controller driver
   4  *
   5  * Copyright (c) 2009 Samsung Electronics Co. Ltd
   6  * Author: Jaswinder Singh <jassi.brar@samsung.com>
   7  * based upon I2S drivers by Ben Dooks.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17
  18 #include <sound/soc.h>
  19 #include <sound/pcm_params.h>
  20
  21 #include <plat/audio.h>
  22 #include <plat/dma.h>
  23
  24 #include "dma.h"
  25 #include "pcm.h"
  26
  27 /*Register Offsets */
  28 #define S3C_PCM_CTL             0x00
  29 #define S3C_PCM_CLKCTL          0x04
  30 #define S3C_PCM_TXFIFO          0x08
  31 #define S3C_PCM_RXFIFO          0x0C
  32 #define S3C_PCM_IRQCTL          0x10
  33 #define S3C_PCM_IRQSTAT         0x14
  34 #define S3C_PCM_FIFOSTAT        0x18
  35 #define S3C_PCM_CLRINT          0x20
  36
  37 /* PCM_CTL Bit-Fields */
  38 #define S3C_PCM_CTL_TXDIPSTICK_MASK     0x3f
  39 #define S3C_PCM_CTL_TXDIPSTICK_SHIFT    13
  40 #define S3C_PCM_CTL_RXDIPSTICK_MASK     0x3f
  41 #define S3C_PCM_CTL_RXDIPSTICK_SHIFT    7
  42 #define S3C_PCM_CTL_TXDMA_EN            (0x1 << 6)
  43 #define S3C_PCM_CTL_RXDMA_EN            (0x1 << 5)
  44 #define S3C_PCM_CTL_TXMSB_AFTER_FSYNC   (0x1 << 4)
  45 #define S3C_PCM_CTL_RXMSB_AFTER_FSYNC   (0x1 << 3)
  46 #define S3C_PCM_CTL_TXFIFO_EN           (0x1 << 2)
  47 #define S3C_PCM_CTL_RXFIFO_EN           (0x1 << 1)
  48 #define S3C_PCM_CTL_ENABLE              (0x1 << 0)
  49
  50 /* PCM_CLKCTL Bit-Fields */
  51 #define S3C_PCM_CLKCTL_SERCLK_EN        (0x1 << 19)
  52 #define S3C_PCM_CLKCTL_SERCLKSEL_PCLK   (0x1 << 18)
  53 #define S3C_PCM_CLKCTL_SCLKDIV_MASK     0x1ff
  54 #define S3C_PCM_CLKCTL_SYNCDIV_MASK     0x1ff
  55 #define S3C_PCM_CLKCTL_SCLKDIV_SHIFT    9
  56 #define S3C_PCM_CLKCTL_SYNCDIV_SHIFT    0
  57
  58 /* PCM_TXFIFO Bit-Fields */
  59 #define S3C_PCM_TXFIFO_DVALID   (0x1 << 16)
  60 #define S3C_PCM_TXFIFO_DATA_MSK (0xffff << 0)
  61
  62 /* PCM_RXFIFO Bit-Fields */
  63 #define S3C_PCM_RXFIFO_DVALID   (0x1 << 16)
  64 #define S3C_PCM_RXFIFO_DATA_MSK (0xffff << 0)
  65
  66 /* PCM_IRQCTL Bit-Fields */
  67 #define S3C_PCM_IRQCTL_IRQEN            (0x1 << 14)
  68 #define S3C_PCM_IRQCTL_WRDEN            (0x1 << 12)
  69 #define S3C_PCM_IRQCTL_TXEMPTYEN        (0x1 << 11)
  70 #define S3C_PCM_IRQCTL_TXALMSTEMPTYEN   (0x1 << 10)
  71 #define S3C_PCM_IRQCTL_TXFULLEN         (0x1 << 9)
  72 #define S3C_PCM_IRQCTL_TXALMSTFULLEN    (0x1 << 8)
  73 #define S3C_PCM_IRQCTL_TXSTARVEN        (0x1 << 7)
  74 #define S3C_PCM_IRQCTL_TXERROVRFLEN     (0x1 << 6)
  75 #define S3C_PCM_IRQCTL_RXEMPTEN         (0x1 << 5)
  76 #define S3C_PCM_IRQCTL_RXALMSTEMPTEN    (0x1 << 4)
  77 #define S3C_PCM_IRQCTL_RXFULLEN         (0x1 << 3)
  78 #define S3C_PCM_IRQCTL_RXALMSTFULLEN    (0x1 << 2)
  79 #define S3C_PCM_IRQCTL_RXSTARVEN        (0x1 << 1)
  80 #define S3C_PCM_IRQCTL_RXERROVRFLEN     (0x1 << 0)
  81
  82 /* PCM_IRQSTAT Bit-Fields */
  83 #define S3C_PCM_IRQSTAT_IRQPND          (0x1 << 13)
  84 #define S3C_PCM_IRQSTAT_WRD_XFER        (0x1 << 12)
  85 #define S3C_PCM_IRQSTAT_TXEMPTY         (0x1 << 11)
  86 #define S3C_PCM_IRQSTAT_TXALMSTEMPTY    (0x1 << 10)
  87 #define S3C_PCM_IRQSTAT_TXFULL          (0x1 << 9)
  88 #define S3C_PCM_IRQSTAT_TXALMSTFULL     (0x1 << 8)
  89 #define S3C_PCM_IRQSTAT_TXSTARV         (0x1 << 7)
  90 #define S3C_PCM_IRQSTAT_TXERROVRFL      (0x1 << 6)
  91 #define S3C_PCM_IRQSTAT_RXEMPT          (0x1 << 5)
  92 #define S3C_PCM_IRQSTAT_RXALMSTEMPT     (0x1 << 4)
  93 #define S3C_PCM_IRQSTAT_RXFULL          (0x1 << 3)
  94 #define S3C_PCM_IRQSTAT_RXALMSTFULL     (0x1 << 2)
  95 #define S3C_PCM_IRQSTAT_RXSTARV         (0x1 << 1)
  96 #define S3C_PCM_IRQSTAT_RXERROVRFL      (0x1 << 0)
  97
  98 /* PCM_FIFOSTAT Bit-Fields */
  99 #define S3C_PCM_FIFOSTAT_TXCNT_MSK              (0x3f << 14)
 100 #define S3C_PCM_FIFOSTAT_TXFIFOEMPTY            (0x1 << 13)
 101 #define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY       (0x1 << 12)
 102 #define S3C_PCM_FIFOSTAT_TXFIFOFULL             (0x1 << 11)
 103 #define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL        (0x1 << 10)
 104 #define S3C_PCM_FIFOSTAT_RXCNT_MSK              (0x3f << 4)
 105 #define S3C_PCM_FIFOSTAT_RXFIFOEMPTY            (0x1 << 3)
 106 #define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY       (0x1 << 2)
 107 #define S3C_PCM_FIFOSTAT_RXFIFOFULL             (0x1 << 1)
 108 #define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL        (0x1 << 0)
 109
 110 /**
 111  * struct s3c_pcm_info - S3C PCM Controller information
 112  * @dev: The parent device passed to use from the probe.
 113  * @regs: The pointer to the device register block.
 114  * @dma_playback: DMA information for playback channel.
 115  * @dma_capture: DMA information for capture channel.
 116  */
 117 struct s3c_pcm_info {
 118         spinlock_t lock;
 119         struct device   *dev;
 120         void __iomem    *regs;
 121
 122         unsigned int sclk_per_fs;
 123
 124         /* Whether to keep PCMSCLK enabled even when idle(no active xfer) */
 125         unsigned int idleclk;
 126
 127         struct clk      *pclk;
 128         struct clk      *cclk;
 129
 130         struct s3c_dma_params   *dma_playback;
 131         struct s3c_dma_params   *dma_capture;
 132 };
 133
 134 static struct s3c2410_dma_client s3c_pcm_dma_client_out = {
 135         .name           = "PCM Stereo out"
 136 };
 137
 138 static struct s3c2410_dma_client s3c_pcm_dma_client_in = {
 139         .name           = "PCM Stereo in"
 140 };
 141
 142 static struct s3c_dma_params s3c_pcm_stereo_out[] = {
 143         [0] = {
 144                 .client         = &s3c_pcm_dma_client_out,
 145                 .dma_size       = 4,
 146         },
 147         [1] = {
 148                 .client         = &s3c_pcm_dma_client_out,
 149                 .dma_size       = 4,
 150         },
 151 };
 152
 153 static struct s3c_dma_params s3c_pcm_stereo_in[] = {
 154         [0] = {
 155                 .client         = &s3c_pcm_dma_client_in,
 156                 .dma_size       = 4,
 157         },
 158         [1] = {
 159                 .client         = &s3c_pcm_dma_client_in,
 160                 .dma_size       = 4,
 161         },
 162 };
 163
 164 static struct s3c_pcm_info s3c_pcm[2];
 165
 166 static void s3c_pcm_snd_txctrl(struct s3c_pcm_info *pcm, int on)
 167 {
 168         void __iomem *regs = pcm->regs;
 169         u32 ctl, clkctl;
 170
 171         clkctl = readl(regs + S3C_PCM_CLKCTL);
 172         ctl = readl(regs + S3C_PCM_CTL);
 173         ctl &= ~(S3C_PCM_CTL_TXDIPSTICK_MASK
 174                          << S3C_PCM_CTL_TXDIPSTICK_SHIFT);
 175
 176         if (on) {
 177                 ctl |= S3C_PCM_CTL_TXDMA_EN;
 178                 ctl |= S3C_PCM_CTL_TXFIFO_EN;
 179                 ctl |= S3C_PCM_CTL_ENABLE;
 180                 ctl |= (0x4<<S3C_PCM_CTL_TXDIPSTICK_SHIFT);
 181                 clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
 182         } else {
 183                 ctl &= ~S3C_PCM_CTL_TXDMA_EN;
 184                 ctl &= ~S3C_PCM_CTL_TXFIFO_EN;
 185
 186                 if (!(ctl & S3C_PCM_CTL_RXFIFO_EN)) {
 187                         ctl &= ~S3C_PCM_CTL_ENABLE;
 188                         if (!pcm->idleclk)
 189                                 clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
 190                 }
 191         }
 192
 193         writel(clkctl, regs + S3C_PCM_CLKCTL);
 194         writel(ctl, regs + S3C_PCM_CTL);
 195 }
 196
 197 static void s3c_pcm_snd_rxctrl(struct s3c_pcm_info *pcm, int on)
 198 {
 199         void __iomem *regs = pcm->regs;
 200         u32 ctl, clkctl;
 201
 202         ctl = readl(regs + S3C_PCM_CTL);
 203         clkctl = readl(regs + S3C_PCM_CLKCTL);
 204         ctl &= ~(S3C_PCM_CTL_RXDIPSTICK_MASK
 205                          << S3C_PCM_CTL_RXDIPSTICK_SHIFT);
 206
 207         if (on) {
 208                 ctl |= S3C_PCM_CTL_RXDMA_EN;
 209                 ctl |= S3C_PCM_CTL_RXFIFO_EN;
 210                 ctl |= S3C_PCM_CTL_ENABLE;
 211                 ctl |= (0x20<<S3C_PCM_CTL_RXDIPSTICK_SHIFT);
 212                 clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
 213         } else {
 214                 ctl &= ~S3C_PCM_CTL_RXDMA_EN;
 215                 ctl &= ~S3C_PCM_CTL_RXFIFO_EN;
 216
 217                 if (!(ctl & S3C_PCM_CTL_TXFIFO_EN)) {
 218                         ctl &= ~S3C_PCM_CTL_ENABLE;
 219                         if (!pcm->idleclk)
 220                                 clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
 221                 }
 222         }
 223
 224         writel(clkctl, regs + S3C_PCM_CLKCTL);
 225         writel(ctl, regs + S3C_PCM_CTL);
 226 }
 227
 228 static int s3c_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 229                                struct snd_soc_dai *dai)
 230 {
 231         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 232         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
 233         unsigned long flags;
 234
 235         dev_dbg(pcm->dev, "Entered %s\n", __func__);
 236
 237         switch (cmd) {
 238         case SNDRV_PCM_TRIGGER_START:
 239         case SNDRV_PCM_TRIGGER_RESUME:
 240         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 241                 spin_lock_irqsave(&pcm->lock, flags);
 242
 243                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 244                         s3c_pcm_snd_rxctrl(pcm, 1);
 245                 else
 246                         s3c_pcm_snd_txctrl(pcm, 1);
 247
 248                 spin_unlock_irqrestore(&pcm->lock, flags);
 249                 break;
 250
 251         case SNDRV_PCM_TRIGGER_STOP:
 252         case SNDRV_PCM_TRIGGER_SUSPEND:
 253         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 254                 spin_lock_irqsave(&pcm->lock, flags);
 255
 256                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 257                         s3c_pcm_snd_rxctrl(pcm, 0);
 258                 else
 259                         s3c_pcm_snd_txctrl(pcm, 0);
 260
 261                 spin_unlock_irqrestore(&pcm->lock, flags);
 262                 break;
 263
 264         default:
 265                 return -EINVAL;
 266         }
 267
 268         return 0;
 269 }
 270
 271 static int s3c_pcm_hw_params(struct snd_pcm_substream *substream,
 272                                  struct snd_pcm_hw_params *params,
 273                                  struct snd_soc_dai *socdai)
 274 {
 275         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 276         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
 277         struct s3c_dma_params *dma_data;
 278         void __iomem *regs = pcm->regs;
 279         struct clk *clk;
 280         int sclk_div, sync_div;
 281         unsigned long flags;
 282         u32 clkctl;
 283
 284         dev_dbg(pcm->dev, "Entered %s\n", __func__);
 285
 286         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 287                 dma_data = pcm->dma_playback;
 288         else
 289                 dma_data = pcm->dma_capture;
 290
 291         snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_data);
 292
 293         /* Strictly check for sample size */
 294         switch (params_format(params)) {
 295         case SNDRV_PCM_FORMAT_S16_LE:
 296                 break;
 297         default:
 298                 return -EINVAL;
 299         }
 300
 301         spin_lock_irqsave(&pcm->lock, flags);
 302
 303         /* Get hold of the PCMSOURCE_CLK */
 304         clkctl = readl(regs + S3C_PCM_CLKCTL);
 305         if (clkctl & S3C_PCM_CLKCTL_SERCLKSEL_PCLK)
 306                 clk = pcm->pclk;
 307         else
 308                 clk = pcm->cclk;
 309
 310         /* Set the SCLK divider */
 311         sclk_div = clk_get_rate(clk) / pcm->sclk_per_fs /
 312                                         params_rate(params) / 2 - 1;
 313
 314         clkctl &= ~(S3C_PCM_CLKCTL_SCLKDIV_MASK
 315                         << S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
 316         clkctl |= ((sclk_div & S3C_PCM_CLKCTL_SCLKDIV_MASK)
 317                         << S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
 318
 319         /* Set the SYNC divider */
 320         sync_div = pcm->sclk_per_fs - 1;
 321
 322         clkctl &= ~(S3C_PCM_CLKCTL_SYNCDIV_MASK
 323                                 << S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
 324         clkctl |= ((sync_div & S3C_PCM_CLKCTL_SYNCDIV_MASK)
 325                                 << S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
 326
 327         writel(clkctl, regs + S3C_PCM_CLKCTL);
 328
 329         spin_unlock_irqrestore(&pcm->lock, flags);
 330
 331         dev_dbg(pcm->dev, "PCMSOURCE_CLK-%lu SCLK=%ufs SCLK_DIV=%d SYNC_DIV=%d\n",
 332                                 clk_get_rate(clk), pcm->sclk_per_fs,
 333                                 sclk_div, sync_div);
 334
 335         return 0;
 336 }
 337
 338 static int s3c_pcm_set_fmt(struct snd_soc_dai *cpu_dai,
 339                                unsigned int fmt)
 340 {
 341         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
 342         void __iomem *regs = pcm->regs;
 343         unsigned long flags;
 344         int ret = 0;
 345         u32 ctl;
 346
 347         dev_dbg(pcm->dev, "Entered %s\n", __func__);
 348
 349         spin_lock_irqsave(&pcm->lock, flags);
 350
 351         ctl = readl(regs + S3C_PCM_CTL);
 352
 353         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 354         case SND_SOC_DAIFMT_IB_NF:
 355                 /* Nothing to do, IB_NF by default */
 356                 break;
 357         default:
 358                 dev_err(pcm->dev, "Unsupported clock inversion!\n");
 359                 ret = -EINVAL;
 360                 goto exit;
 361         }
 362
 363         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 364         case SND_SOC_DAIFMT_CBS_CFS:
 365                 /* Nothing to do, Master by default */
 366                 break;
 367         default:
 368                 dev_err(pcm->dev, "Unsupported master/slave format!\n");
 369                 ret = -EINVAL;
 370                 goto exit;
 371         }
 372
 373         switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
 374         case SND_SOC_DAIFMT_CONT:
 375                 pcm->idleclk = 1;
 376                 break;
 377         case SND_SOC_DAIFMT_GATED:
 378                 pcm->idleclk = 0;
 379                 break;
 380         default:
 381                 dev_err(pcm->dev, "Invalid Clock gating request!\n");
 382                 ret = -EINVAL;
 383                 goto exit;
 384         }
 385
 386         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 387         case SND_SOC_DAIFMT_DSP_A:
 388                 ctl |= S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
 389                 ctl |= S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
 390                 break;
 391         case SND_SOC_DAIFMT_DSP_B:
 392                 ctl &= ~S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
 393                 ctl &= ~S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
 394                 break;
 395         default:
 396                 dev_err(pcm->dev, "Unsupported data format!\n");
 397                 ret = -EINVAL;
 398                 goto exit;
 399         }
 400
 401         writel(ctl, regs + S3C_PCM_CTL);
 402
 403 exit:
 404         spin_unlock_irqrestore(&pcm->lock, flags);
 405
 406         return ret;
 407 }
 408
 409 static int s3c_pcm_set_clkdiv(struct snd_soc_dai *cpu_dai,
 410                                                 int div_id, int div)
 411 {
 412         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
 413
 414         switch (div_id) {
 415         case S3C_PCM_SCLK_PER_FS:
 416                 pcm->sclk_per_fs = div;
 417                 break;
 418
 419         default:
 420                 return -EINVAL;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int s3c_pcm_set_sysclk(struct snd_soc_dai *cpu_dai,
 427                                   int clk_id, unsigned int freq, int dir)
 428 {
 429         struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
 430         void __iomem *regs = pcm->regs;
 431         u32 clkctl = readl(regs + S3C_PCM_CLKCTL);
 432
 433         switch (clk_id) {
 434         case S3C_PCM_CLKSRC_PCLK:
 435                 clkctl |= S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
 436                 break;
 437
 438         case S3C_PCM_CLKSRC_MUX:
 439                 clkctl &= ~S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
 440
 441                 if (clk_get_rate(pcm->cclk) != freq)
 442                         clk_set_rate(pcm->cclk, freq);
 443
 444                 break;
 445
 446         default:
 447                 return -EINVAL;
 448         }
 449
 450         writel(clkctl, regs + S3C_PCM_CLKCTL);
 451
 452         return 0;
 453 }
 454
 455 static struct snd_soc_dai_ops s3c_pcm_dai_ops = {
 456         .set_sysclk     = s3c_pcm_set_sysclk,
 457         .set_clkdiv     = s3c_pcm_set_clkdiv,
 458         .trigger        = s3c_pcm_trigger,
 459         .hw_params      = s3c_pcm_hw_params,
 460         .set_fmt        = s3c_pcm_set_fmt,
 461 };
 462
 463 #define S3C_PCM_RATES  SNDRV_PCM_RATE_8000_96000
 464
 465 #define S3C_PCM_DAI_DECLARE                     \
 466         .symmetric_rates = 1,                                   \
 467         .ops = &s3c_pcm_dai_ops,                                \
 468         .playback = {                                           \
 469                 .channels_min   = 2,                            \
 470                 .channels_max   = 2,                            \
 471                 .rates          = S3C_PCM_RATES,                \
 472                 .formats        = SNDRV_PCM_FMTBIT_S16_LE,      \
 473         },                                                      \
 474         .capture = {                                            \
 475                 .channels_min   = 2,                            \
 476                 .channels_max   = 2,                            \
 477                 .rates          = S3C_PCM_RATES,                \
 478                 .formats        = SNDRV_PCM_FMTBIT_S16_LE,      \
 479         }
 480
 481 struct snd_soc_dai_driver s3c_pcm_dai[] = {
 482         [0] = {
 483                 .name   = "samsung-pcm.0",
 484                 S3C_PCM_DAI_DECLARE,
 485         },
 486         [1] = {
 487                 .name   = "samsung-pcm.1",
 488                 S3C_PCM_DAI_DECLARE,
 489         },
 490 };
 491 EXPORT_SYMBOL_GPL(s3c_pcm_dai);
 492
 493 static __devinit int s3c_pcm_dev_probe(struct platform_device *pdev)
 494 {
 495         struct s3c_pcm_info *pcm;
 496         struct resource *mem_res, *dmatx_res, *dmarx_res;
 497         struct s3c_audio_pdata *pcm_pdata;
 498         int ret;
 499
 500         /* Check for valid device index */
 501         if ((pdev->id < 0) || pdev->id >= ARRAY_SIZE(s3c_pcm)) {
 502                 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
 503                 return -EINVAL;
 504         }
 505
 506         pcm_pdata = pdev->dev.platform_data;
 507
 508         /* Check for availability of necessary resource */
 509         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 510         if (!dmatx_res) {
 511                 dev_err(&pdev->dev, "Unable to get PCM-TX dma resource\n");
 512                 return -ENXIO;
 513         }
 514
 515         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 516         if (!dmarx_res) {
 517                 dev_err(&pdev->dev, "Unable to get PCM-RX dma resource\n");
 518                 return -ENXIO;
 519         }
 520
 521         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 522         if (!mem_res) {
 523                 dev_err(&pdev->dev, "Unable to get register resource\n");
 524                 return -ENXIO;
 525         }
 526
 527         if (pcm_pdata && pcm_pdata->cfg_gpio && pcm_pdata->cfg_gpio(pdev)) {
 528                 dev_err(&pdev->dev, "Unable to configure gpio\n");
 529                 return -EINVAL;
 530         }
 531
 532         pcm = &s3c_pcm[pdev->id];
 533         pcm->dev = &pdev->dev;
 534
 535         spin_lock_init(&pcm->lock);
 536
 537         /* Default is 128fs */
 538         pcm->sclk_per_fs = 128;
 539
 540         pcm->cclk = clk_get(&pdev->dev, "audio-bus");
 541         if (IS_ERR(pcm->cclk)) {
 542                 dev_err(&pdev->dev, "failed to get audio-bus\n");
 543                 ret = PTR_ERR(pcm->cclk);
 544                 goto err1;
 545         }
 546         clk_enable(pcm->cclk);
 547
 548         /* record our pcm structure for later use in the callbacks */
 549         dev_set_drvdata(&pdev->dev, pcm);
 550
 551         if (!request_mem_region(mem_res->start,
 552                                 resource_size(mem_res), "samsung-pcm")) {
 553                 dev_err(&pdev->dev, "Unable to request register region\n");
 554                 ret = -EBUSY;
 555                 goto err2;
 556         }
 557
 558         pcm->regs = ioremap(mem_res->start, 0x100);
 559         if (pcm->regs == NULL) {
 560                 dev_err(&pdev->dev, "cannot ioremap registers\n");
 561                 ret = -ENXIO;
 562                 goto err3;
 563         }
 564
 565         pcm->pclk = clk_get(&pdev->dev, "pcm");
 566         if (IS_ERR(pcm->pclk)) {
 567                 dev_err(&pdev->dev, "failed to get pcm_clock\n");
 568                 ret = -ENOENT;
 569                 goto err4;
 570         }
 571         clk_enable(pcm->pclk);
 572
 573         ret = snd_soc_register_dai(&pdev->dev, &s3c_pcm_dai[pdev->id]);
 574         if (ret != 0) {
 575                 dev_err(&pdev->dev, "failed to get pcm_clock\n");
 576                 goto err5;
 577         }
 578
 579         s3c_pcm_stereo_in[pdev->id].dma_addr = mem_res->start
 580                                                         + S3C_PCM_RXFIFO;
 581         s3c_pcm_stereo_out[pdev->id].dma_addr = mem_res->start
 582                                                         + S3C_PCM_TXFIFO;
 583
 584         s3c_pcm_stereo_in[pdev->id].channel = dmarx_res->start;
 585         s3c_pcm_stereo_out[pdev->id].channel = dmatx_res->start;
 586
 587         pcm->dma_capture = &s3c_pcm_stereo_in[pdev->id];
 588         pcm->dma_playback = &s3c_pcm_stereo_out[pdev->id];
 589
 590         return 0;
 591
 592 err5:
 593         clk_disable(pcm->pclk);
 594         clk_put(pcm->pclk);
 595 err4:
 596         iounmap(pcm->regs);
 597 err3:
 598         release_mem_region(mem_res->start, resource_size(mem_res));
 599 err2:
 600         clk_disable(pcm->cclk);
 601         clk_put(pcm->cclk);
 602 err1:
 603         return ret;
 604 }
 605
 606 static __devexit int s3c_pcm_dev_remove(struct platform_device *pdev)
 607 {
 608         struct s3c_pcm_info *pcm = &s3c_pcm[pdev->id];
 609         struct resource *mem_res;
 610
 611         snd_soc_unregister_dai(&pdev->dev);
 612
 613         iounmap(pcm->regs);
 614
 615         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 616         release_mem_region(mem_res->start, resource_size(mem_res));
 617
 618         clk_disable(pcm->cclk);
 619         clk_disable(pcm->pclk);
 620         clk_put(pcm->pclk);
 621         clk_put(pcm->cclk);
 622
 623         return 0;
 624 }
 625
 626 static struct platform_driver s3c_pcm_driver = {
 627         .probe  = s3c_pcm_dev_probe,
 628         .remove = __devexit_p(s3c_pcm_dev_remove),
 629         .driver = {
 630                 .name = "samsung-pcm",
 631                 .owner = THIS_MODULE,
 632         },
 633 };
 634
 635 static int __init s3c_pcm_init(void)
 636 {
 637         return platform_driver_register(&s3c_pcm_driver);
 638 }
 639 module_init(s3c_pcm_init);
 640
 641 static void __exit s3c_pcm_exit(void)
 642 {
 643         platform_driver_unregister(&s3c_pcm_driver);
 644 }
 645 module_exit(s3c_pcm_exit);
 646
 647 /* Module information */
 648 MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
 649 MODULE_DESCRIPTION("S3C PCM Controller Driver");
 650 MODULE_LICENSE("GPL");
 651 MODULE_ALIAS("platform:samsung-pcm");