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ASoC: fsi: rename fsi_stream_push/pop() to fsi_stream_init/quit()
[deliverable/linux.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <sound/soc.h>
21 #include <sound/sh_fsi.h>
22
23 /* PortA/PortB register */
24 #define REG_DO_FMT 0x0000
25 #define REG_DOFF_CTL 0x0004
26 #define REG_DOFF_ST 0x0008
27 #define REG_DI_FMT 0x000C
28 #define REG_DIFF_CTL 0x0010
29 #define REG_DIFF_ST 0x0014
30 #define REG_CKG1 0x0018
31 #define REG_CKG2 0x001C
32 #define REG_DIDT 0x0020
33 #define REG_DODT 0x0024
34 #define REG_MUTE_ST 0x0028
35 #define REG_OUT_DMAC 0x002C
36 #define REG_OUT_SEL 0x0030
37 #define REG_IN_DMAC 0x0038
38
39 /* master register */
40 #define MST_CLK_RST 0x0210
41 #define MST_SOFT_RST 0x0214
42 #define MST_FIFO_SZ 0x0218
43
44 /* core register (depend on FSI version) */
45 #define A_MST_CTLR 0x0180
46 #define B_MST_CTLR 0x01A0
47 #define CPU_INT_ST 0x01F4
48 #define CPU_IEMSK 0x01F8
49 #define CPU_IMSK 0x01FC
50 #define INT_ST 0x0200
51 #define IEMSK 0x0204
52 #define IMSK 0x0208
53
54 /* DO_FMT */
55 /* DI_FMT */
56 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
57 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
58 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
59
60 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
61 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
62 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
63
64 #define CR_MONO (0x0 << 4)
65 #define CR_MONO_D (0x1 << 4)
66 #define CR_PCM (0x2 << 4)
67 #define CR_I2S (0x3 << 4)
68 #define CR_TDM (0x4 << 4)
69 #define CR_TDM_D (0x5 << 4)
70
71 /* DOFF_CTL */
72 /* DIFF_CTL */
73 #define IRQ_HALF 0x00100000
74 #define FIFO_CLR 0x00000001
75
76 /* DOFF_ST */
77 #define ERR_OVER 0x00000010
78 #define ERR_UNDER 0x00000001
79 #define ST_ERR (ERR_OVER | ERR_UNDER)
80
81 /* CKG1 */
82 #define ACKMD_MASK 0x00007000
83 #define BPFMD_MASK 0x00000700
84 #define DIMD (1 << 4)
85 #define DOMD (1 << 0)
86
87 /* A/B MST_CTLR */
88 #define BP (1 << 4) /* Fix the signal of Biphase output */
89 #define SE (1 << 0) /* Fix the master clock */
90
91 /* CLK_RST */
92 #define CRB (1 << 4)
93 #define CRA (1 << 0)
94
95 /* IO SHIFT / MACRO */
96 #define BI_SHIFT 12
97 #define BO_SHIFT 8
98 #define AI_SHIFT 4
99 #define AO_SHIFT 0
100 #define AB_IO(param, shift) (param << shift)
101
102 /* SOFT_RST */
103 #define PBSR (1 << 12) /* Port B Software Reset */
104 #define PASR (1 << 8) /* Port A Software Reset */
105 #define IR (1 << 4) /* Interrupt Reset */
106 #define FSISR (1 << 0) /* Software Reset */
107
108 /* OUT_SEL (FSI2) */
109 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
110 /* 1: Biphase and serial */
111
112 /* FIFO_SZ */
113 #define FIFO_SZ_MASK 0x7
114
115 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
116
117 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
118
119 typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable);
120
121 /*
122 * FSI driver use below type name for variable
123 *
124 * xxx_num : number of data
125 * xxx_pos : position of data
126 * xxx_capa : capacity of data
127 */
128
129 /*
130 * period/frame/sample image
131 *
132 * ex) PCM (2ch)
133 *
134 * period pos period pos
135 * [n] [n + 1]
136 * |<-------------------- period--------------------->|
137 * ==|============================================ ... =|==
138 * | |
139 * ||<----- frame ----->|<------ frame ----->| ... |
140 * |+--------------------+--------------------+- ... |
141 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
142 * |+--------------------+--------------------+- ... |
143 * ==|============================================ ... =|==
144 */
145
146 /*
147 * FSI FIFO image
148 *
149 * | |
150 * | |
151 * | [ sample ] |
152 * | [ sample ] |
153 * | [ sample ] |
154 * | [ sample ] |
155 * --> go to codecs
156 */
157
158 /*
159 * struct
160 */
161
162 struct fsi_stream {
163 struct snd_pcm_substream *substream;
164
165 int fifo_sample_capa; /* sample capacity of FSI FIFO */
166 int buff_sample_capa; /* sample capacity of ALSA buffer */
167 int buff_sample_pos; /* sample position of ALSA buffer */
168 int period_samples; /* sample number / 1 period */
169 int period_pos; /* current period position */
170 int sample_width; /* sample width */
171
172 int uerr_num;
173 int oerr_num;
174 };
175
176 struct fsi_priv {
177 void __iomem *base;
178 struct fsi_master *master;
179
180 struct fsi_stream playback;
181 struct fsi_stream capture;
182
183 u32 do_fmt;
184 u32 di_fmt;
185
186 int chan_num:16;
187 int clk_master:1;
188 int spdif:1;
189
190 long rate;
191 };
192
193 struct fsi_core {
194 int ver;
195
196 u32 int_st;
197 u32 iemsk;
198 u32 imsk;
199 u32 a_mclk;
200 u32 b_mclk;
201 };
202
203 struct fsi_master {
204 void __iomem *base;
205 int irq;
206 struct fsi_priv fsia;
207 struct fsi_priv fsib;
208 struct fsi_core *core;
209 struct sh_fsi_platform_info *info;
210 spinlock_t lock;
211 };
212
213 /*
214 * basic read write function
215 */
216
217 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
218 {
219 /* valid data area is 24bit */
220 data &= 0x00ffffff;
221
222 __raw_writel(data, reg);
223 }
224
225 static u32 __fsi_reg_read(u32 __iomem *reg)
226 {
227 return __raw_readl(reg);
228 }
229
230 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
231 {
232 u32 val = __fsi_reg_read(reg);
233
234 val &= ~mask;
235 val |= data & mask;
236
237 __fsi_reg_write(reg, val);
238 }
239
240 #define fsi_reg_write(p, r, d)\
241 __fsi_reg_write((p->base + REG_##r), d)
242
243 #define fsi_reg_read(p, r)\
244 __fsi_reg_read((p->base + REG_##r))
245
246 #define fsi_reg_mask_set(p, r, m, d)\
247 __fsi_reg_mask_set((p->base + REG_##r), m, d)
248
249 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
250 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
251 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
252 {
253 u32 ret;
254 unsigned long flags;
255
256 spin_lock_irqsave(&master->lock, flags);
257 ret = __fsi_reg_read(master->base + reg);
258 spin_unlock_irqrestore(&master->lock, flags);
259
260 return ret;
261 }
262
263 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
264 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
265 static void _fsi_master_mask_set(struct fsi_master *master,
266 u32 reg, u32 mask, u32 data)
267 {
268 unsigned long flags;
269
270 spin_lock_irqsave(&master->lock, flags);
271 __fsi_reg_mask_set(master->base + reg, mask, data);
272 spin_unlock_irqrestore(&master->lock, flags);
273 }
274
275 /*
276 * basic function
277 */
278
279 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
280 {
281 return fsi->master;
282 }
283
284 static int fsi_is_clk_master(struct fsi_priv *fsi)
285 {
286 return fsi->clk_master;
287 }
288
289 static int fsi_is_port_a(struct fsi_priv *fsi)
290 {
291 return fsi->master->base == fsi->base;
292 }
293
294 static int fsi_is_spdif(struct fsi_priv *fsi)
295 {
296 return fsi->spdif;
297 }
298
299 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
300 {
301 struct snd_soc_pcm_runtime *rtd = substream->private_data;
302
303 return rtd->cpu_dai;
304 }
305
306 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
307 {
308 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
309
310 if (dai->id == 0)
311 return &master->fsia;
312 else
313 return &master->fsib;
314 }
315
316 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
317 {
318 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
319 }
320
321 static set_rate_func fsi_get_info_set_rate(struct fsi_master *master)
322 {
323 if (!master->info)
324 return NULL;
325
326 return master->info->set_rate;
327 }
328
329 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
330 {
331 int is_porta = fsi_is_port_a(fsi);
332 struct fsi_master *master = fsi_get_master(fsi);
333
334 if (!master->info)
335 return 0;
336
337 return is_porta ? master->info->porta_flags :
338 master->info->portb_flags;
339 }
340
341 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
342 {
343 int is_porta = fsi_is_port_a(fsi);
344 u32 shift;
345
346 if (is_porta)
347 shift = is_play ? AO_SHIFT : AI_SHIFT;
348 else
349 shift = is_play ? BO_SHIFT : BI_SHIFT;
350
351 return shift;
352 }
353
354 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
355 {
356 return frames * fsi->chan_num;
357 }
358
359 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
360 {
361 return samples / fsi->chan_num;
362 }
363
364 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play)
365 {
366 u32 status;
367 int frames;
368
369 status = is_play ?
370 fsi_reg_read(fsi, DOFF_ST) :
371 fsi_reg_read(fsi, DIFF_ST);
372
373 frames = 0x1ff & (status >> 8);
374
375 return fsi_frame2sample(fsi, frames);
376 }
377
378 static void fsi_count_fifo_err(struct fsi_priv *fsi)
379 {
380 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
381 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
382
383 if (ostatus & ERR_OVER)
384 fsi->playback.oerr_num++;
385
386 if (ostatus & ERR_UNDER)
387 fsi->playback.uerr_num++;
388
389 if (istatus & ERR_OVER)
390 fsi->capture.oerr_num++;
391
392 if (istatus & ERR_UNDER)
393 fsi->capture.uerr_num++;
394
395 fsi_reg_write(fsi, DOFF_ST, 0);
396 fsi_reg_write(fsi, DIFF_ST, 0);
397 }
398
399 /*
400 * fsi_stream_xx() function
401 */
402 #define fsi_is_play(substream) fsi_stream_is_play(substream->stream)
403 static inline int fsi_stream_is_play(int stream)
404 {
405 return stream == SNDRV_PCM_STREAM_PLAYBACK;
406 }
407
408 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
409 int is_play)
410 {
411 return is_play ? &fsi->playback : &fsi->capture;
412 }
413
414 static int fsi_stream_is_working(struct fsi_priv *fsi,
415 int is_play)
416 {
417 struct fsi_stream *io = fsi_stream_get(fsi, is_play);
418 struct fsi_master *master = fsi_get_master(fsi);
419 unsigned long flags;
420 int ret;
421
422 spin_lock_irqsave(&master->lock, flags);
423 ret = !!io->substream;
424 spin_unlock_irqrestore(&master->lock, flags);
425
426 return ret;
427 }
428
429 static void fsi_stream_init(struct fsi_priv *fsi,
430 int is_play,
431 struct snd_pcm_substream *substream)
432 {
433 struct fsi_stream *io = fsi_stream_get(fsi, is_play);
434 struct snd_pcm_runtime *runtime = substream->runtime;
435 struct fsi_master *master = fsi_get_master(fsi);
436 unsigned long flags;
437
438 spin_lock_irqsave(&master->lock, flags);
439 io->substream = substream;
440 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
441 io->buff_sample_pos = 0;
442 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
443 io->period_pos = 0;
444 io->sample_width = samples_to_bytes(runtime, 1);
445 io->oerr_num = -1; /* ignore 1st err */
446 io->uerr_num = -1; /* ignore 1st err */
447 spin_unlock_irqrestore(&master->lock, flags);
448 }
449
450 static void fsi_stream_quit(struct fsi_priv *fsi, int is_play)
451 {
452 struct fsi_stream *io = fsi_stream_get(fsi, is_play);
453 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
454 struct fsi_master *master = fsi_get_master(fsi);
455 unsigned long flags;
456
457 spin_lock_irqsave(&master->lock, flags);
458
459 if (io->oerr_num > 0)
460 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
461
462 if (io->uerr_num > 0)
463 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
464
465 io->substream = NULL;
466 io->buff_sample_capa = 0;
467 io->buff_sample_pos = 0;
468 io->period_samples = 0;
469 io->period_pos = 0;
470 io->sample_width = 0;
471 io->oerr_num = 0;
472 io->uerr_num = 0;
473 spin_unlock_irqrestore(&master->lock, flags);
474 }
475
476 /*
477 * pio function
478 */
479
480 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, int stream)
481 {
482 int is_play = fsi_stream_is_play(stream);
483 struct fsi_stream *io = fsi_stream_get(fsi, is_play);
484 struct snd_pcm_runtime *runtime = io->substream->runtime;
485
486 return runtime->dma_area +
487 samples_to_bytes(runtime, io->buff_sample_pos);
488 }
489
490 static void fsi_pio_push16(struct fsi_priv *fsi, int num)
491 {
492 u16 *start;
493 int i;
494
495 start = (u16 *)fsi_pio_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
496
497 for (i = 0; i < num; i++)
498 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
499 }
500
501 static void fsi_pio_pop16(struct fsi_priv *fsi, int num)
502 {
503 u16 *start;
504 int i;
505
506 start = (u16 *)fsi_pio_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
507
508
509 for (i = 0; i < num; i++)
510 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
511 }
512
513 static void fsi_pio_push32(struct fsi_priv *fsi, int num)
514 {
515 u32 *start;
516 int i;
517
518 start = (u32 *)fsi_pio_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
519
520
521 for (i = 0; i < num; i++)
522 fsi_reg_write(fsi, DODT, *(start + i));
523 }
524
525 static void fsi_pio_pop32(struct fsi_priv *fsi, int num)
526 {
527 u32 *start;
528 int i;
529
530 start = (u32 *)fsi_pio_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
531
532 for (i = 0; i < num; i++)
533 *(start + i) = fsi_reg_read(fsi, DIDT);
534 }
535
536 /*
537 * irq function
538 */
539
540 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
541 {
542 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
543 struct fsi_master *master = fsi_get_master(fsi);
544
545 fsi_core_mask_set(master, imsk, data, data);
546 fsi_core_mask_set(master, iemsk, data, data);
547 }
548
549 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
550 {
551 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
552 struct fsi_master *master = fsi_get_master(fsi);
553
554 fsi_core_mask_set(master, imsk, data, 0);
555 fsi_core_mask_set(master, iemsk, data, 0);
556 }
557
558 static u32 fsi_irq_get_status(struct fsi_master *master)
559 {
560 return fsi_core_read(master, int_st);
561 }
562
563 static void fsi_irq_clear_status(struct fsi_priv *fsi)
564 {
565 u32 data = 0;
566 struct fsi_master *master = fsi_get_master(fsi);
567
568 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
569 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
570
571 /* clear interrupt factor */
572 fsi_core_mask_set(master, int_st, data, 0);
573 }
574
575 /*
576 * SPDIF master clock function
577 *
578 * These functions are used later FSI2
579 */
580 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
581 {
582 struct fsi_master *master = fsi_get_master(fsi);
583 u32 mask, val;
584
585 if (master->core->ver < 2) {
586 pr_err("fsi: register access err (%s)\n", __func__);
587 return;
588 }
589
590 mask = BP | SE;
591 val = enable ? mask : 0;
592
593 fsi_is_port_a(fsi) ?
594 fsi_core_mask_set(master, a_mclk, mask, val) :
595 fsi_core_mask_set(master, b_mclk, mask, val);
596 }
597
598 /*
599 * clock function
600 */
601 static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi,
602 long rate, int enable)
603 {
604 struct fsi_master *master = fsi_get_master(fsi);
605 set_rate_func set_rate = fsi_get_info_set_rate(master);
606 int fsi_ver = master->core->ver;
607 int ret;
608
609 ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable);
610 if (ret < 0) /* error */
611 return ret;
612
613 if (!enable)
614 return 0;
615
616 if (ret > 0) {
617 u32 data = 0;
618
619 switch (ret & SH_FSI_ACKMD_MASK) {
620 default:
621 /* FALL THROUGH */
622 case SH_FSI_ACKMD_512:
623 data |= (0x0 << 12);
624 break;
625 case SH_FSI_ACKMD_256:
626 data |= (0x1 << 12);
627 break;
628 case SH_FSI_ACKMD_128:
629 data |= (0x2 << 12);
630 break;
631 case SH_FSI_ACKMD_64:
632 data |= (0x3 << 12);
633 break;
634 case SH_FSI_ACKMD_32:
635 if (fsi_ver < 2)
636 dev_err(dev, "unsupported ACKMD\n");
637 else
638 data |= (0x4 << 12);
639 break;
640 }
641
642 switch (ret & SH_FSI_BPFMD_MASK) {
643 default:
644 /* FALL THROUGH */
645 case SH_FSI_BPFMD_32:
646 data |= (0x0 << 8);
647 break;
648 case SH_FSI_BPFMD_64:
649 data |= (0x1 << 8);
650 break;
651 case SH_FSI_BPFMD_128:
652 data |= (0x2 << 8);
653 break;
654 case SH_FSI_BPFMD_256:
655 data |= (0x3 << 8);
656 break;
657 case SH_FSI_BPFMD_512:
658 data |= (0x4 << 8);
659 break;
660 case SH_FSI_BPFMD_16:
661 if (fsi_ver < 2)
662 dev_err(dev, "unsupported ACKMD\n");
663 else
664 data |= (0x7 << 8);
665 break;
666 }
667
668 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
669 udelay(10);
670 ret = 0;
671 }
672
673 return ret;
674 }
675
676 #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1)
677 #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0)
678 static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable)
679 {
680 struct fsi_master *master = fsi_get_master(fsi);
681 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
682
683 if (enable)
684 fsi_irq_enable(fsi, is_play);
685 else
686 fsi_irq_disable(fsi, is_play);
687
688 if (fsi_is_clk_master(fsi))
689 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
690 }
691
692 /*
693 * ctrl function
694 */
695 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, struct fsi_stream *io,
696 void (*run16)(struct fsi_priv *fsi, int size),
697 void (*run32)(struct fsi_priv *fsi, int size),
698 int samples)
699 {
700 struct snd_pcm_runtime *runtime;
701 struct snd_pcm_substream *substream;
702 int over_period;
703
704 if (!fsi ||
705 !io->substream ||
706 !io->substream->runtime)
707 return -EINVAL;
708
709 over_period = 0;
710 substream = io->substream;
711 runtime = substream->runtime;
712
713 /* FSI FIFO has limit.
714 * So, this driver can not send periods data at a time
715 */
716 if (io->buff_sample_pos >=
717 io->period_samples * (io->period_pos + 1)) {
718
719 over_period = 1;
720 io->period_pos = (io->period_pos + 1) % runtime->periods;
721
722 if (0 == io->period_pos)
723 io->buff_sample_pos = 0;
724 }
725
726 switch (io->sample_width) {
727 case 2:
728 run16(fsi, samples);
729 break;
730 case 4:
731 run32(fsi, samples);
732 break;
733 default:
734 return -EINVAL;
735 }
736
737 /* update buff_sample_pos */
738 io->buff_sample_pos += samples;
739
740 if (over_period)
741 snd_pcm_period_elapsed(substream);
742
743 return 0;
744 }
745
746 static int fsi_data_pop(struct fsi_priv *fsi)
747 {
748 int is_play = fsi_stream_is_play(SNDRV_PCM_STREAM_CAPTURE);
749 int sample_residues; /* samples in FSI fifo */
750 int sample_space; /* ALSA free samples space */
751 int samples;
752 struct fsi_stream *io = fsi_stream_get(fsi, is_play);
753
754 sample_residues = fsi_get_current_fifo_samples(fsi, is_play);
755 sample_space = io->buff_sample_capa - io->buff_sample_pos;
756
757 samples = min(sample_residues, sample_space);
758
759 return fsi_fifo_data_ctrl(fsi, io,
760 fsi_pio_pop16,
761 fsi_pio_pop32,
762 samples);
763 }
764
765 static int fsi_data_push(struct fsi_priv *fsi)
766 {
767 int is_play = fsi_stream_is_play(SNDRV_PCM_STREAM_PLAYBACK);
768 int sample_residues; /* ALSA residue samples */
769 int sample_space; /* FSI fifo free samples space */
770 int samples;
771 struct fsi_stream *io = fsi_stream_get(fsi, is_play);
772
773 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
774 sample_space = io->fifo_sample_capa -
775 fsi_get_current_fifo_samples(fsi, is_play);
776
777 samples = min(sample_residues, sample_space);
778
779 return fsi_fifo_data_ctrl(fsi, io,
780 fsi_pio_push16,
781 fsi_pio_push32,
782 samples);
783 }
784
785 static irqreturn_t fsi_interrupt(int irq, void *data)
786 {
787 struct fsi_master *master = data;
788 u32 int_st = fsi_irq_get_status(master);
789
790 /* clear irq status */
791 fsi_master_mask_set(master, SOFT_RST, IR, 0);
792 fsi_master_mask_set(master, SOFT_RST, IR, IR);
793
794 if (int_st & AB_IO(1, AO_SHIFT))
795 fsi_data_push(&master->fsia);
796 if (int_st & AB_IO(1, BO_SHIFT))
797 fsi_data_push(&master->fsib);
798 if (int_st & AB_IO(1, AI_SHIFT))
799 fsi_data_pop(&master->fsia);
800 if (int_st & AB_IO(1, BI_SHIFT))
801 fsi_data_pop(&master->fsib);
802
803 fsi_count_fifo_err(&master->fsia);
804 fsi_count_fifo_err(&master->fsib);
805
806 fsi_irq_clear_status(&master->fsia);
807 fsi_irq_clear_status(&master->fsib);
808
809 return IRQ_HANDLED;
810 }
811
812 /*
813 * dai ops
814 */
815 static void fsi_fifo_init(struct fsi_priv *fsi,
816 int is_play,
817 struct device *dev)
818 {
819 struct fsi_master *master = fsi_get_master(fsi);
820 struct fsi_stream *io = fsi_stream_get(fsi, is_play);
821 u32 shift, i;
822 int frame_capa;
823
824 /* get on-chip RAM capacity */
825 shift = fsi_master_read(master, FIFO_SZ);
826 shift >>= fsi_get_port_shift(fsi, is_play);
827 shift &= FIFO_SZ_MASK;
828 frame_capa = 256 << shift;
829 dev_dbg(dev, "fifo = %d words\n", frame_capa);
830
831 /*
832 * The maximum number of sample data varies depending
833 * on the number of channels selected for the format.
834 *
835 * FIFOs are used in 4-channel units in 3-channel mode
836 * and in 8-channel units in 5- to 7-channel mode
837 * meaning that more FIFOs than the required size of DPRAM
838 * are used.
839 *
840 * ex) if 256 words of DP-RAM is connected
841 * 1 channel: 256 (256 x 1 = 256)
842 * 2 channels: 128 (128 x 2 = 256)
843 * 3 channels: 64 ( 64 x 3 = 192)
844 * 4 channels: 64 ( 64 x 4 = 256)
845 * 5 channels: 32 ( 32 x 5 = 160)
846 * 6 channels: 32 ( 32 x 6 = 192)
847 * 7 channels: 32 ( 32 x 7 = 224)
848 * 8 channels: 32 ( 32 x 8 = 256)
849 */
850 for (i = 1; i < fsi->chan_num; i <<= 1)
851 frame_capa >>= 1;
852 dev_dbg(dev, "%d channel %d store\n",
853 fsi->chan_num, frame_capa);
854
855 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
856
857 /*
858 * set interrupt generation factor
859 * clear FIFO
860 */
861 if (is_play) {
862 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
863 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
864 } else {
865 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
866 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
867 }
868 }
869
870 static int fsi_hw_startup(struct fsi_priv *fsi,
871 int is_play,
872 struct device *dev)
873 {
874 struct fsi_master *master = fsi_get_master(fsi);
875 int fsi_ver = master->core->ver;
876 u32 flags = fsi_get_info_flags(fsi);
877 u32 data = 0;
878
879 /* clock setting */
880 if (fsi_is_clk_master(fsi))
881 data = DIMD | DOMD;
882
883 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
884
885 /* clock inversion (CKG2) */
886 data = 0;
887 if (SH_FSI_LRM_INV & flags)
888 data |= 1 << 12;
889 if (SH_FSI_BRM_INV & flags)
890 data |= 1 << 8;
891 if (SH_FSI_LRS_INV & flags)
892 data |= 1 << 4;
893 if (SH_FSI_BRS_INV & flags)
894 data |= 1 << 0;
895
896 fsi_reg_write(fsi, CKG2, data);
897
898 /* set format */
899 fsi_reg_write(fsi, DO_FMT, fsi->do_fmt);
900 fsi_reg_write(fsi, DI_FMT, fsi->di_fmt);
901
902 /* spdif ? */
903 if (fsi_is_spdif(fsi)) {
904 fsi_spdif_clk_ctrl(fsi, 1);
905 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
906 }
907
908 /*
909 * FIXME
910 *
911 * FSI driver assumed that data package is in-back.
912 * FSI2 chip can select it.
913 */
914 if (fsi_ver >= 2) {
915 fsi_reg_write(fsi, OUT_DMAC, (1 << 4));
916 fsi_reg_write(fsi, IN_DMAC, (1 << 4));
917 }
918
919 /* irq clear */
920 fsi_irq_disable(fsi, is_play);
921 fsi_irq_clear_status(fsi);
922
923 /* fifo init */
924 fsi_fifo_init(fsi, is_play, dev);
925
926 return 0;
927 }
928
929 static void fsi_hw_shutdown(struct fsi_priv *fsi,
930 struct device *dev)
931 {
932 if (fsi_is_clk_master(fsi))
933 fsi_set_master_clk(dev, fsi, fsi->rate, 0);
934 }
935
936 static int fsi_dai_startup(struct snd_pcm_substream *substream,
937 struct snd_soc_dai *dai)
938 {
939 struct fsi_priv *fsi = fsi_get_priv(substream);
940 int is_play = fsi_is_play(substream);
941
942 return fsi_hw_startup(fsi, is_play, dai->dev);
943 }
944
945 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
946 struct snd_soc_dai *dai)
947 {
948 struct fsi_priv *fsi = fsi_get_priv(substream);
949
950 fsi_hw_shutdown(fsi, dai->dev);
951 fsi->rate = 0;
952 }
953
954 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
955 struct snd_soc_dai *dai)
956 {
957 struct fsi_priv *fsi = fsi_get_priv(substream);
958 int is_play = fsi_is_play(substream);
959 int ret = 0;
960
961 switch (cmd) {
962 case SNDRV_PCM_TRIGGER_START:
963 fsi_stream_init(fsi, is_play, substream);
964 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
965 fsi_port_start(fsi, is_play);
966 break;
967 case SNDRV_PCM_TRIGGER_STOP:
968 fsi_port_stop(fsi, is_play);
969 fsi_stream_quit(fsi, is_play);
970 break;
971 }
972
973 return ret;
974 }
975
976 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
977 {
978 u32 data = 0;
979
980 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
981 case SND_SOC_DAIFMT_I2S:
982 data = CR_I2S;
983 fsi->chan_num = 2;
984 break;
985 case SND_SOC_DAIFMT_LEFT_J:
986 data = CR_PCM;
987 fsi->chan_num = 2;
988 break;
989 default:
990 return -EINVAL;
991 }
992
993 fsi->do_fmt = data;
994 fsi->di_fmt = data;
995
996 return 0;
997 }
998
999 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1000 {
1001 struct fsi_master *master = fsi_get_master(fsi);
1002 u32 data = 0;
1003
1004 if (master->core->ver < 2)
1005 return -EINVAL;
1006
1007 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
1008 fsi->chan_num = 2;
1009 fsi->spdif = 1;
1010
1011 fsi->do_fmt = data;
1012 fsi->di_fmt = data;
1013
1014 return 0;
1015 }
1016
1017 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1018 {
1019 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1020 struct fsi_master *master = fsi_get_master(fsi);
1021 set_rate_func set_rate = fsi_get_info_set_rate(master);
1022 u32 flags = fsi_get_info_flags(fsi);
1023 int ret;
1024
1025 /* set master/slave audio interface */
1026 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1027 case SND_SOC_DAIFMT_CBM_CFM:
1028 fsi->clk_master = 1;
1029 break;
1030 case SND_SOC_DAIFMT_CBS_CFS:
1031 break;
1032 default:
1033 return -EINVAL;
1034 }
1035
1036 if (fsi_is_clk_master(fsi) && !set_rate) {
1037 dev_err(dai->dev, "platform doesn't have set_rate\n");
1038 return -EINVAL;
1039 }
1040
1041 /* set format */
1042 switch (flags & SH_FSI_FMT_MASK) {
1043 case SH_FSI_FMT_DAI:
1044 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1045 break;
1046 case SH_FSI_FMT_SPDIF:
1047 ret = fsi_set_fmt_spdif(fsi);
1048 break;
1049 default:
1050 ret = -EINVAL;
1051 }
1052
1053 return ret;
1054 }
1055
1056 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1057 struct snd_pcm_hw_params *params,
1058 struct snd_soc_dai *dai)
1059 {
1060 struct fsi_priv *fsi = fsi_get_priv(substream);
1061 long rate = params_rate(params);
1062 int ret;
1063
1064 if (!fsi_is_clk_master(fsi))
1065 return 0;
1066
1067 ret = fsi_set_master_clk(dai->dev, fsi, rate, 1);
1068 if (ret < 0)
1069 return ret;
1070
1071 fsi->rate = rate;
1072
1073 return ret;
1074 }
1075
1076 static const struct snd_soc_dai_ops fsi_dai_ops = {
1077 .startup = fsi_dai_startup,
1078 .shutdown = fsi_dai_shutdown,
1079 .trigger = fsi_dai_trigger,
1080 .set_fmt = fsi_dai_set_fmt,
1081 .hw_params = fsi_dai_hw_params,
1082 };
1083
1084 /*
1085 * pcm ops
1086 */
1087
1088 static struct snd_pcm_hardware fsi_pcm_hardware = {
1089 .info = SNDRV_PCM_INFO_INTERLEAVED |
1090 SNDRV_PCM_INFO_MMAP |
1091 SNDRV_PCM_INFO_MMAP_VALID |
1092 SNDRV_PCM_INFO_PAUSE,
1093 .formats = FSI_FMTS,
1094 .rates = FSI_RATES,
1095 .rate_min = 8000,
1096 .rate_max = 192000,
1097 .channels_min = 1,
1098 .channels_max = 2,
1099 .buffer_bytes_max = 64 * 1024,
1100 .period_bytes_min = 32,
1101 .period_bytes_max = 8192,
1102 .periods_min = 1,
1103 .periods_max = 32,
1104 .fifo_size = 256,
1105 };
1106
1107 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1108 {
1109 struct snd_pcm_runtime *runtime = substream->runtime;
1110 int ret = 0;
1111
1112 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1113
1114 ret = snd_pcm_hw_constraint_integer(runtime,
1115 SNDRV_PCM_HW_PARAM_PERIODS);
1116
1117 return ret;
1118 }
1119
1120 static int fsi_hw_params(struct snd_pcm_substream *substream,
1121 struct snd_pcm_hw_params *hw_params)
1122 {
1123 return snd_pcm_lib_malloc_pages(substream,
1124 params_buffer_bytes(hw_params));
1125 }
1126
1127 static int fsi_hw_free(struct snd_pcm_substream *substream)
1128 {
1129 return snd_pcm_lib_free_pages(substream);
1130 }
1131
1132 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1133 {
1134 struct fsi_priv *fsi = fsi_get_priv(substream);
1135 struct fsi_stream *io = fsi_stream_get(fsi, fsi_is_play(substream));
1136 int samples_pos = io->buff_sample_pos - 1;
1137
1138 if (samples_pos < 0)
1139 samples_pos = 0;
1140
1141 return fsi_sample2frame(fsi, samples_pos);
1142 }
1143
1144 static struct snd_pcm_ops fsi_pcm_ops = {
1145 .open = fsi_pcm_open,
1146 .ioctl = snd_pcm_lib_ioctl,
1147 .hw_params = fsi_hw_params,
1148 .hw_free = fsi_hw_free,
1149 .pointer = fsi_pointer,
1150 };
1151
1152 /*
1153 * snd_soc_platform
1154 */
1155
1156 #define PREALLOC_BUFFER (32 * 1024)
1157 #define PREALLOC_BUFFER_MAX (32 * 1024)
1158
1159 static void fsi_pcm_free(struct snd_pcm *pcm)
1160 {
1161 snd_pcm_lib_preallocate_free_for_all(pcm);
1162 }
1163
1164 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1165 {
1166 struct snd_pcm *pcm = rtd->pcm;
1167
1168 /*
1169 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1170 * in MMAP mode (i.e. aplay -M)
1171 */
1172 return snd_pcm_lib_preallocate_pages_for_all(
1173 pcm,
1174 SNDRV_DMA_TYPE_CONTINUOUS,
1175 snd_dma_continuous_data(GFP_KERNEL),
1176 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1177 }
1178
1179 /*
1180 * alsa struct
1181 */
1182
1183 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1184 {
1185 .name = "fsia-dai",
1186 .playback = {
1187 .rates = FSI_RATES,
1188 .formats = FSI_FMTS,
1189 .channels_min = 1,
1190 .channels_max = 8,
1191 },
1192 .capture = {
1193 .rates = FSI_RATES,
1194 .formats = FSI_FMTS,
1195 .channels_min = 1,
1196 .channels_max = 8,
1197 },
1198 .ops = &fsi_dai_ops,
1199 },
1200 {
1201 .name = "fsib-dai",
1202 .playback = {
1203 .rates = FSI_RATES,
1204 .formats = FSI_FMTS,
1205 .channels_min = 1,
1206 .channels_max = 8,
1207 },
1208 .capture = {
1209 .rates = FSI_RATES,
1210 .formats = FSI_FMTS,
1211 .channels_min = 1,
1212 .channels_max = 8,
1213 },
1214 .ops = &fsi_dai_ops,
1215 },
1216 };
1217
1218 static struct snd_soc_platform_driver fsi_soc_platform = {
1219 .ops = &fsi_pcm_ops,
1220 .pcm_new = fsi_pcm_new,
1221 .pcm_free = fsi_pcm_free,
1222 };
1223
1224 /*
1225 * platform function
1226 */
1227
1228 static int fsi_probe(struct platform_device *pdev)
1229 {
1230 struct fsi_master *master;
1231 const struct platform_device_id *id_entry;
1232 struct resource *res;
1233 unsigned int irq;
1234 int ret;
1235
1236 id_entry = pdev->id_entry;
1237 if (!id_entry) {
1238 dev_err(&pdev->dev, "unknown fsi device\n");
1239 return -ENODEV;
1240 }
1241
1242 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1243 irq = platform_get_irq(pdev, 0);
1244 if (!res || (int)irq <= 0) {
1245 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1246 ret = -ENODEV;
1247 goto exit;
1248 }
1249
1250 master = kzalloc(sizeof(*master), GFP_KERNEL);
1251 if (!master) {
1252 dev_err(&pdev->dev, "Could not allocate master\n");
1253 ret = -ENOMEM;
1254 goto exit;
1255 }
1256
1257 master->base = ioremap_nocache(res->start, resource_size(res));
1258 if (!master->base) {
1259 ret = -ENXIO;
1260 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1261 goto exit_kfree;
1262 }
1263
1264 /* master setting */
1265 master->irq = irq;
1266 master->info = pdev->dev.platform_data;
1267 master->core = (struct fsi_core *)id_entry->driver_data;
1268 spin_lock_init(&master->lock);
1269
1270 /* FSI A setting */
1271 master->fsia.base = master->base;
1272 master->fsia.master = master;
1273
1274 /* FSI B setting */
1275 master->fsib.base = master->base + 0x40;
1276 master->fsib.master = master;
1277
1278 pm_runtime_enable(&pdev->dev);
1279 dev_set_drvdata(&pdev->dev, master);
1280
1281 ret = request_irq(irq, &fsi_interrupt, 0,
1282 id_entry->name, master);
1283 if (ret) {
1284 dev_err(&pdev->dev, "irq request err\n");
1285 goto exit_iounmap;
1286 }
1287
1288 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1289 if (ret < 0) {
1290 dev_err(&pdev->dev, "cannot snd soc register\n");
1291 goto exit_free_irq;
1292 }
1293
1294 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
1295 ARRAY_SIZE(fsi_soc_dai));
1296 if (ret < 0) {
1297 dev_err(&pdev->dev, "cannot snd dai register\n");
1298 goto exit_snd_soc;
1299 }
1300
1301 return ret;
1302
1303 exit_snd_soc:
1304 snd_soc_unregister_platform(&pdev->dev);
1305 exit_free_irq:
1306 free_irq(irq, master);
1307 exit_iounmap:
1308 iounmap(master->base);
1309 pm_runtime_disable(&pdev->dev);
1310 exit_kfree:
1311 kfree(master);
1312 master = NULL;
1313 exit:
1314 return ret;
1315 }
1316
1317 static int fsi_remove(struct platform_device *pdev)
1318 {
1319 struct fsi_master *master;
1320
1321 master = dev_get_drvdata(&pdev->dev);
1322
1323 free_irq(master->irq, master);
1324 pm_runtime_disable(&pdev->dev);
1325
1326 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1327 snd_soc_unregister_platform(&pdev->dev);
1328
1329 iounmap(master->base);
1330 kfree(master);
1331
1332 return 0;
1333 }
1334
1335 static void __fsi_suspend(struct fsi_priv *fsi,
1336 int is_play,
1337 struct device *dev)
1338 {
1339 if (!fsi_stream_is_working(fsi, is_play))
1340 return;
1341
1342 fsi_port_stop(fsi, is_play);
1343 fsi_hw_shutdown(fsi, dev);
1344 }
1345
1346 static void __fsi_resume(struct fsi_priv *fsi,
1347 int is_play,
1348 struct device *dev)
1349 {
1350 if (!fsi_stream_is_working(fsi, is_play))
1351 return;
1352
1353 fsi_hw_startup(fsi, is_play, dev);
1354
1355 if (fsi_is_clk_master(fsi) && fsi->rate)
1356 fsi_set_master_clk(dev, fsi, fsi->rate, 1);
1357
1358 fsi_port_start(fsi, is_play);
1359
1360 }
1361
1362 static int fsi_suspend(struct device *dev)
1363 {
1364 struct fsi_master *master = dev_get_drvdata(dev);
1365 struct fsi_priv *fsia = &master->fsia;
1366 struct fsi_priv *fsib = &master->fsib;
1367
1368 __fsi_suspend(fsia, 1, dev);
1369 __fsi_suspend(fsia, 0, dev);
1370
1371 __fsi_suspend(fsib, 1, dev);
1372 __fsi_suspend(fsib, 0, dev);
1373
1374 return 0;
1375 }
1376
1377 static int fsi_resume(struct device *dev)
1378 {
1379 struct fsi_master *master = dev_get_drvdata(dev);
1380 struct fsi_priv *fsia = &master->fsia;
1381 struct fsi_priv *fsib = &master->fsib;
1382
1383 __fsi_resume(fsia, 1, dev);
1384 __fsi_resume(fsia, 0, dev);
1385
1386 __fsi_resume(fsib, 1, dev);
1387 __fsi_resume(fsib, 0, dev);
1388
1389 return 0;
1390 }
1391
1392 static struct dev_pm_ops fsi_pm_ops = {
1393 .suspend = fsi_suspend,
1394 .resume = fsi_resume,
1395 };
1396
1397 static struct fsi_core fsi1_core = {
1398 .ver = 1,
1399
1400 /* Interrupt */
1401 .int_st = INT_ST,
1402 .iemsk = IEMSK,
1403 .imsk = IMSK,
1404 };
1405
1406 static struct fsi_core fsi2_core = {
1407 .ver = 2,
1408
1409 /* Interrupt */
1410 .int_st = CPU_INT_ST,
1411 .iemsk = CPU_IEMSK,
1412 .imsk = CPU_IMSK,
1413 .a_mclk = A_MST_CTLR,
1414 .b_mclk = B_MST_CTLR,
1415 };
1416
1417 static struct platform_device_id fsi_id_table[] = {
1418 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1419 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1420 {},
1421 };
1422 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1423
1424 static struct platform_driver fsi_driver = {
1425 .driver = {
1426 .name = "fsi-pcm-audio",
1427 .pm = &fsi_pm_ops,
1428 },
1429 .probe = fsi_probe,
1430 .remove = fsi_remove,
1431 .id_table = fsi_id_table,
1432 };
1433
1434 module_platform_driver(fsi_driver);
1435
1436 MODULE_LICENSE("GPL");
1437 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1438 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
1439 MODULE_ALIAS("platform:fsi-pcm-audio");
Linux kernel - Deliverables
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