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Merge tag 'rpmsg-3.19-next' of git://git.kernel.org/pub/scm/linux/kernel/git/ohad...
[deliverable/linux.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/scatterlist.h>
22 #include <linux/sh_dma.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/workqueue.h>
26 #include <sound/soc.h>
27 #include <sound/pcm_params.h>
28 #include <sound/sh_fsi.h>
29
30 /* PortA/PortB register */
31 #define REG_DO_FMT 0x0000
32 #define REG_DOFF_CTL 0x0004
33 #define REG_DOFF_ST 0x0008
34 #define REG_DI_FMT 0x000C
35 #define REG_DIFF_CTL 0x0010
36 #define REG_DIFF_ST 0x0014
37 #define REG_CKG1 0x0018
38 #define REG_CKG2 0x001C
39 #define REG_DIDT 0x0020
40 #define REG_DODT 0x0024
41 #define REG_MUTE_ST 0x0028
42 #define REG_OUT_DMAC 0x002C
43 #define REG_OUT_SEL 0x0030
44 #define REG_IN_DMAC 0x0038
45
46 /* master register */
47 #define MST_CLK_RST 0x0210
48 #define MST_SOFT_RST 0x0214
49 #define MST_FIFO_SZ 0x0218
50
51 /* core register (depend on FSI version) */
52 #define A_MST_CTLR 0x0180
53 #define B_MST_CTLR 0x01A0
54 #define CPU_INT_ST 0x01F4
55 #define CPU_IEMSK 0x01F8
56 #define CPU_IMSK 0x01FC
57 #define INT_ST 0x0200
58 #define IEMSK 0x0204
59 #define IMSK 0x0208
60
61 /* DO_FMT */
62 /* DI_FMT */
63 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
64 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
65 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
66 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
67
68 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
69 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
70 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
71
72 #define CR_MONO (0x0 << 4)
73 #define CR_MONO_D (0x1 << 4)
74 #define CR_PCM (0x2 << 4)
75 #define CR_I2S (0x3 << 4)
76 #define CR_TDM (0x4 << 4)
77 #define CR_TDM_D (0x5 << 4)
78
79 /* OUT_DMAC */
80 /* IN_DMAC */
81 #define VDMD_MASK (0x3 << 4)
82 #define VDMD_FRONT (0x0 << 4) /* Package in front */
83 #define VDMD_BACK (0x1 << 4) /* Package in back */
84 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
85
86 #define DMA_ON (0x1 << 0)
87
88 /* DOFF_CTL */
89 /* DIFF_CTL */
90 #define IRQ_HALF 0x00100000
91 #define FIFO_CLR 0x00000001
92
93 /* DOFF_ST */
94 #define ERR_OVER 0x00000010
95 #define ERR_UNDER 0x00000001
96 #define ST_ERR (ERR_OVER | ERR_UNDER)
97
98 /* CKG1 */
99 #define ACKMD_MASK 0x00007000
100 #define BPFMD_MASK 0x00000700
101 #define DIMD (1 << 4)
102 #define DOMD (1 << 0)
103
104 /* A/B MST_CTLR */
105 #define BP (1 << 4) /* Fix the signal of Biphase output */
106 #define SE (1 << 0) /* Fix the master clock */
107
108 /* CLK_RST */
109 #define CRB (1 << 4)
110 #define CRA (1 << 0)
111
112 /* IO SHIFT / MACRO */
113 #define BI_SHIFT 12
114 #define BO_SHIFT 8
115 #define AI_SHIFT 4
116 #define AO_SHIFT 0
117 #define AB_IO(param, shift) (param << shift)
118
119 /* SOFT_RST */
120 #define PBSR (1 << 12) /* Port B Software Reset */
121 #define PASR (1 << 8) /* Port A Software Reset */
122 #define IR (1 << 4) /* Interrupt Reset */
123 #define FSISR (1 << 0) /* Software Reset */
124
125 /* OUT_SEL (FSI2) */
126 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
127 /* 1: Biphase and serial */
128
129 /* FIFO_SZ */
130 #define FIFO_SZ_MASK 0x7
131
132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
133
134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
135
136 /*
137 * bus options
138 *
139 * 0x000000BA
140 *
141 * A : sample widtht 16bit setting
142 * B : sample widtht 24bit setting
143 */
144
145 #define SHIFT_16DATA 0
146 #define SHIFT_24DATA 4
147
148 #define PACKAGE_24BITBUS_BACK 0
149 #define PACKAGE_24BITBUS_FRONT 1
150 #define PACKAGE_16BITBUS_STREAM 2
151
152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
154
155 /*
156 * FSI driver use below type name for variable
157 *
158 * xxx_num : number of data
159 * xxx_pos : position of data
160 * xxx_capa : capacity of data
161 */
162
163 /*
164 * period/frame/sample image
165 *
166 * ex) PCM (2ch)
167 *
168 * period pos period pos
169 * [n] [n + 1]
170 * |<-------------------- period--------------------->|
171 * ==|============================================ ... =|==
172 * | |
173 * ||<----- frame ----->|<------ frame ----->| ... |
174 * |+--------------------+--------------------+- ... |
175 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
176 * |+--------------------+--------------------+- ... |
177 * ==|============================================ ... =|==
178 */
179
180 /*
181 * FSI FIFO image
182 *
183 * | |
184 * | |
185 * | [ sample ] |
186 * | [ sample ] |
187 * | [ sample ] |
188 * | [ sample ] |
189 * --> go to codecs
190 */
191
192 /*
193 * FSI clock
194 *
195 * FSIxCLK [CPG] (ick) -------> |
196 * |-> FSI_DIV (div)-> FSI2
197 * FSIxCK [external] (xck) ---> |
198 */
199
200 /*
201 * struct
202 */
203
204 struct fsi_stream_handler;
205 struct fsi_stream {
206
207 /*
208 * these are initialized by fsi_stream_init()
209 */
210 struct snd_pcm_substream *substream;
211 int fifo_sample_capa; /* sample capacity of FSI FIFO */
212 int buff_sample_capa; /* sample capacity of ALSA buffer */
213 int buff_sample_pos; /* sample position of ALSA buffer */
214 int period_samples; /* sample number / 1 period */
215 int period_pos; /* current period position */
216 int sample_width; /* sample width */
217 int uerr_num;
218 int oerr_num;
219
220 /*
221 * bus options
222 */
223 u32 bus_option;
224
225 /*
226 * thse are initialized by fsi_handler_init()
227 */
228 struct fsi_stream_handler *handler;
229 struct fsi_priv *priv;
230
231 /*
232 * these are for DMAEngine
233 */
234 struct dma_chan *chan;
235 int dma_id;
236 };
237
238 struct fsi_clk {
239 /* see [FSI clock] */
240 struct clk *own;
241 struct clk *xck;
242 struct clk *ick;
243 struct clk *div;
244 int (*set_rate)(struct device *dev,
245 struct fsi_priv *fsi);
246
247 unsigned long rate;
248 unsigned int count;
249 };
250
251 struct fsi_priv {
252 void __iomem *base;
253 struct fsi_master *master;
254
255 struct fsi_stream playback;
256 struct fsi_stream capture;
257
258 struct fsi_clk clock;
259
260 u32 fmt;
261
262 int chan_num:16;
263 unsigned int clk_master:1;
264 unsigned int clk_cpg:1;
265 unsigned int spdif:1;
266 unsigned int enable_stream:1;
267 unsigned int bit_clk_inv:1;
268 unsigned int lr_clk_inv:1;
269 };
270
271 struct fsi_stream_handler {
272 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
273 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
274 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
275 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
276 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
277 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
278 int enable);
279 };
280 #define fsi_stream_handler_call(io, func, args...) \
281 (!(io) ? -ENODEV : \
282 !((io)->handler->func) ? 0 : \
283 (io)->handler->func(args))
284
285 struct fsi_core {
286 int ver;
287
288 u32 int_st;
289 u32 iemsk;
290 u32 imsk;
291 u32 a_mclk;
292 u32 b_mclk;
293 };
294
295 struct fsi_master {
296 void __iomem *base;
297 struct fsi_priv fsia;
298 struct fsi_priv fsib;
299 const struct fsi_core *core;
300 spinlock_t lock;
301 };
302
303 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
304
305 /*
306 * basic read write function
307 */
308
309 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
310 {
311 /* valid data area is 24bit */
312 data &= 0x00ffffff;
313
314 __raw_writel(data, reg);
315 }
316
317 static u32 __fsi_reg_read(u32 __iomem *reg)
318 {
319 return __raw_readl(reg);
320 }
321
322 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
323 {
324 u32 val = __fsi_reg_read(reg);
325
326 val &= ~mask;
327 val |= data & mask;
328
329 __fsi_reg_write(reg, val);
330 }
331
332 #define fsi_reg_write(p, r, d)\
333 __fsi_reg_write((p->base + REG_##r), d)
334
335 #define fsi_reg_read(p, r)\
336 __fsi_reg_read((p->base + REG_##r))
337
338 #define fsi_reg_mask_set(p, r, m, d)\
339 __fsi_reg_mask_set((p->base + REG_##r), m, d)
340
341 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
342 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
343 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
344 {
345 u32 ret;
346 unsigned long flags;
347
348 spin_lock_irqsave(&master->lock, flags);
349 ret = __fsi_reg_read(master->base + reg);
350 spin_unlock_irqrestore(&master->lock, flags);
351
352 return ret;
353 }
354
355 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
356 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
357 static void _fsi_master_mask_set(struct fsi_master *master,
358 u32 reg, u32 mask, u32 data)
359 {
360 unsigned long flags;
361
362 spin_lock_irqsave(&master->lock, flags);
363 __fsi_reg_mask_set(master->base + reg, mask, data);
364 spin_unlock_irqrestore(&master->lock, flags);
365 }
366
367 /*
368 * basic function
369 */
370 static int fsi_version(struct fsi_master *master)
371 {
372 return master->core->ver;
373 }
374
375 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
376 {
377 return fsi->master;
378 }
379
380 static int fsi_is_clk_master(struct fsi_priv *fsi)
381 {
382 return fsi->clk_master;
383 }
384
385 static int fsi_is_port_a(struct fsi_priv *fsi)
386 {
387 return fsi->master->base == fsi->base;
388 }
389
390 static int fsi_is_spdif(struct fsi_priv *fsi)
391 {
392 return fsi->spdif;
393 }
394
395 static int fsi_is_enable_stream(struct fsi_priv *fsi)
396 {
397 return fsi->enable_stream;
398 }
399
400 static int fsi_is_play(struct snd_pcm_substream *substream)
401 {
402 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
403 }
404
405 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
406 {
407 struct snd_soc_pcm_runtime *rtd = substream->private_data;
408
409 return rtd->cpu_dai;
410 }
411
412 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
413 {
414 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
415
416 if (dai->id == 0)
417 return &master->fsia;
418 else
419 return &master->fsib;
420 }
421
422 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
423 {
424 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
425 }
426
427 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
428 {
429 int is_play = fsi_stream_is_play(fsi, io);
430 int is_porta = fsi_is_port_a(fsi);
431 u32 shift;
432
433 if (is_porta)
434 shift = is_play ? AO_SHIFT : AI_SHIFT;
435 else
436 shift = is_play ? BO_SHIFT : BI_SHIFT;
437
438 return shift;
439 }
440
441 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
442 {
443 return frames * fsi->chan_num;
444 }
445
446 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
447 {
448 return samples / fsi->chan_num;
449 }
450
451 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
452 struct fsi_stream *io)
453 {
454 int is_play = fsi_stream_is_play(fsi, io);
455 u32 status;
456 int frames;
457
458 status = is_play ?
459 fsi_reg_read(fsi, DOFF_ST) :
460 fsi_reg_read(fsi, DIFF_ST);
461
462 frames = 0x1ff & (status >> 8);
463
464 return fsi_frame2sample(fsi, frames);
465 }
466
467 static void fsi_count_fifo_err(struct fsi_priv *fsi)
468 {
469 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
470 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
471
472 if (ostatus & ERR_OVER)
473 fsi->playback.oerr_num++;
474
475 if (ostatus & ERR_UNDER)
476 fsi->playback.uerr_num++;
477
478 if (istatus & ERR_OVER)
479 fsi->capture.oerr_num++;
480
481 if (istatus & ERR_UNDER)
482 fsi->capture.uerr_num++;
483
484 fsi_reg_write(fsi, DOFF_ST, 0);
485 fsi_reg_write(fsi, DIFF_ST, 0);
486 }
487
488 /*
489 * fsi_stream_xx() function
490 */
491 static inline int fsi_stream_is_play(struct fsi_priv *fsi,
492 struct fsi_stream *io)
493 {
494 return &fsi->playback == io;
495 }
496
497 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
498 struct snd_pcm_substream *substream)
499 {
500 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
501 }
502
503 static int fsi_stream_is_working(struct fsi_priv *fsi,
504 struct fsi_stream *io)
505 {
506 struct fsi_master *master = fsi_get_master(fsi);
507 unsigned long flags;
508 int ret;
509
510 spin_lock_irqsave(&master->lock, flags);
511 ret = !!(io->substream && io->substream->runtime);
512 spin_unlock_irqrestore(&master->lock, flags);
513
514 return ret;
515 }
516
517 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
518 {
519 return io->priv;
520 }
521
522 static void fsi_stream_init(struct fsi_priv *fsi,
523 struct fsi_stream *io,
524 struct snd_pcm_substream *substream)
525 {
526 struct snd_pcm_runtime *runtime = substream->runtime;
527 struct fsi_master *master = fsi_get_master(fsi);
528 unsigned long flags;
529
530 spin_lock_irqsave(&master->lock, flags);
531 io->substream = substream;
532 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
533 io->buff_sample_pos = 0;
534 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
535 io->period_pos = 0;
536 io->sample_width = samples_to_bytes(runtime, 1);
537 io->bus_option = 0;
538 io->oerr_num = -1; /* ignore 1st err */
539 io->uerr_num = -1; /* ignore 1st err */
540 fsi_stream_handler_call(io, init, fsi, io);
541 spin_unlock_irqrestore(&master->lock, flags);
542 }
543
544 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
545 {
546 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
547 struct fsi_master *master = fsi_get_master(fsi);
548 unsigned long flags;
549
550 spin_lock_irqsave(&master->lock, flags);
551
552 if (io->oerr_num > 0)
553 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
554
555 if (io->uerr_num > 0)
556 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
557
558 fsi_stream_handler_call(io, quit, fsi, io);
559 io->substream = NULL;
560 io->buff_sample_capa = 0;
561 io->buff_sample_pos = 0;
562 io->period_samples = 0;
563 io->period_pos = 0;
564 io->sample_width = 0;
565 io->bus_option = 0;
566 io->oerr_num = 0;
567 io->uerr_num = 0;
568 spin_unlock_irqrestore(&master->lock, flags);
569 }
570
571 static int fsi_stream_transfer(struct fsi_stream *io)
572 {
573 struct fsi_priv *fsi = fsi_stream_to_priv(io);
574 if (!fsi)
575 return -EIO;
576
577 return fsi_stream_handler_call(io, transfer, fsi, io);
578 }
579
580 #define fsi_stream_start(fsi, io)\
581 fsi_stream_handler_call(io, start_stop, fsi, io, 1)
582
583 #define fsi_stream_stop(fsi, io)\
584 fsi_stream_handler_call(io, start_stop, fsi, io, 0)
585
586 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
587 {
588 struct fsi_stream *io;
589 int ret1, ret2;
590
591 io = &fsi->playback;
592 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
593
594 io = &fsi->capture;
595 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
596
597 if (ret1 < 0)
598 return ret1;
599 if (ret2 < 0)
600 return ret2;
601
602 return 0;
603 }
604
605 static int fsi_stream_remove(struct fsi_priv *fsi)
606 {
607 struct fsi_stream *io;
608 int ret1, ret2;
609
610 io = &fsi->playback;
611 ret1 = fsi_stream_handler_call(io, remove, fsi, io);
612
613 io = &fsi->capture;
614 ret2 = fsi_stream_handler_call(io, remove, fsi, io);
615
616 if (ret1 < 0)
617 return ret1;
618 if (ret2 < 0)
619 return ret2;
620
621 return 0;
622 }
623
624 /*
625 * format/bus/dma setting
626 */
627 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
628 u32 bus, struct device *dev)
629 {
630 struct fsi_master *master = fsi_get_master(fsi);
631 int is_play = fsi_stream_is_play(fsi, io);
632 u32 fmt = fsi->fmt;
633
634 if (fsi_version(master) >= 2) {
635 u32 dma = 0;
636
637 /*
638 * FSI2 needs DMA/Bus setting
639 */
640 switch (bus) {
641 case PACKAGE_24BITBUS_FRONT:
642 fmt |= CR_BWS_24;
643 dma |= VDMD_FRONT;
644 dev_dbg(dev, "24bit bus / package in front\n");
645 break;
646 case PACKAGE_16BITBUS_STREAM:
647 fmt |= CR_BWS_16;
648 dma |= VDMD_STREAM;
649 dev_dbg(dev, "16bit bus / stream mode\n");
650 break;
651 case PACKAGE_24BITBUS_BACK:
652 default:
653 fmt |= CR_BWS_24;
654 dma |= VDMD_BACK;
655 dev_dbg(dev, "24bit bus / package in back\n");
656 break;
657 }
658
659 if (is_play)
660 fsi_reg_write(fsi, OUT_DMAC, dma);
661 else
662 fsi_reg_write(fsi, IN_DMAC, dma);
663 }
664
665 if (is_play)
666 fsi_reg_write(fsi, DO_FMT, fmt);
667 else
668 fsi_reg_write(fsi, DI_FMT, fmt);
669 }
670
671 /*
672 * irq function
673 */
674
675 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
676 {
677 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
678 struct fsi_master *master = fsi_get_master(fsi);
679
680 fsi_core_mask_set(master, imsk, data, data);
681 fsi_core_mask_set(master, iemsk, data, data);
682 }
683
684 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
685 {
686 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
687 struct fsi_master *master = fsi_get_master(fsi);
688
689 fsi_core_mask_set(master, imsk, data, 0);
690 fsi_core_mask_set(master, iemsk, data, 0);
691 }
692
693 static u32 fsi_irq_get_status(struct fsi_master *master)
694 {
695 return fsi_core_read(master, int_st);
696 }
697
698 static void fsi_irq_clear_status(struct fsi_priv *fsi)
699 {
700 u32 data = 0;
701 struct fsi_master *master = fsi_get_master(fsi);
702
703 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
704 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
705
706 /* clear interrupt factor */
707 fsi_core_mask_set(master, int_st, data, 0);
708 }
709
710 /*
711 * SPDIF master clock function
712 *
713 * These functions are used later FSI2
714 */
715 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
716 {
717 struct fsi_master *master = fsi_get_master(fsi);
718 u32 mask, val;
719
720 mask = BP | SE;
721 val = enable ? mask : 0;
722
723 fsi_is_port_a(fsi) ?
724 fsi_core_mask_set(master, a_mclk, mask, val) :
725 fsi_core_mask_set(master, b_mclk, mask, val);
726 }
727
728 /*
729 * clock function
730 */
731 static int fsi_clk_init(struct device *dev,
732 struct fsi_priv *fsi,
733 int xck,
734 int ick,
735 int div,
736 int (*set_rate)(struct device *dev,
737 struct fsi_priv *fsi))
738 {
739 struct fsi_clk *clock = &fsi->clock;
740 int is_porta = fsi_is_port_a(fsi);
741
742 clock->xck = NULL;
743 clock->ick = NULL;
744 clock->div = NULL;
745 clock->rate = 0;
746 clock->count = 0;
747 clock->set_rate = set_rate;
748
749 clock->own = devm_clk_get(dev, NULL);
750 if (IS_ERR(clock->own))
751 return -EINVAL;
752
753 /* external clock */
754 if (xck) {
755 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
756 if (IS_ERR(clock->xck)) {
757 dev_err(dev, "can't get xck clock\n");
758 return -EINVAL;
759 }
760 if (clock->xck == clock->own) {
761 dev_err(dev, "cpu doesn't support xck clock\n");
762 return -EINVAL;
763 }
764 }
765
766 /* FSIACLK/FSIBCLK */
767 if (ick) {
768 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
769 if (IS_ERR(clock->ick)) {
770 dev_err(dev, "can't get ick clock\n");
771 return -EINVAL;
772 }
773 if (clock->ick == clock->own) {
774 dev_err(dev, "cpu doesn't support ick clock\n");
775 return -EINVAL;
776 }
777 }
778
779 /* FSI-DIV */
780 if (div) {
781 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
782 if (IS_ERR(clock->div)) {
783 dev_err(dev, "can't get div clock\n");
784 return -EINVAL;
785 }
786 if (clock->div == clock->own) {
787 dev_err(dev, "cpu doens't support div clock\n");
788 return -EINVAL;
789 }
790 }
791
792 return 0;
793 }
794
795 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
796 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
797 {
798 fsi->clock.rate = rate;
799 }
800
801 static int fsi_clk_is_valid(struct fsi_priv *fsi)
802 {
803 return fsi->clock.set_rate &&
804 fsi->clock.rate;
805 }
806
807 static int fsi_clk_enable(struct device *dev,
808 struct fsi_priv *fsi)
809 {
810 struct fsi_clk *clock = &fsi->clock;
811 int ret = -EINVAL;
812
813 if (!fsi_clk_is_valid(fsi))
814 return ret;
815
816 if (0 == clock->count) {
817 ret = clock->set_rate(dev, fsi);
818 if (ret < 0) {
819 fsi_clk_invalid(fsi);
820 return ret;
821 }
822
823 if (clock->xck)
824 clk_enable(clock->xck);
825 if (clock->ick)
826 clk_enable(clock->ick);
827 if (clock->div)
828 clk_enable(clock->div);
829
830 clock->count++;
831 }
832
833 return ret;
834 }
835
836 static int fsi_clk_disable(struct device *dev,
837 struct fsi_priv *fsi)
838 {
839 struct fsi_clk *clock = &fsi->clock;
840
841 if (!fsi_clk_is_valid(fsi))
842 return -EINVAL;
843
844 if (1 == clock->count--) {
845 clk_disable(clock->xck);
846 clk_disable(clock->ick);
847 clk_disable(clock->div);
848 }
849
850 return 0;
851 }
852
853 static int fsi_clk_set_ackbpf(struct device *dev,
854 struct fsi_priv *fsi,
855 int ackmd, int bpfmd)
856 {
857 u32 data = 0;
858
859 /* check ackmd/bpfmd relationship */
860 if (bpfmd > ackmd) {
861 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
862 return -EINVAL;
863 }
864
865 /* ACKMD */
866 switch (ackmd) {
867 case 512:
868 data |= (0x0 << 12);
869 break;
870 case 256:
871 data |= (0x1 << 12);
872 break;
873 case 128:
874 data |= (0x2 << 12);
875 break;
876 case 64:
877 data |= (0x3 << 12);
878 break;
879 case 32:
880 data |= (0x4 << 12);
881 break;
882 default:
883 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
884 return -EINVAL;
885 }
886
887 /* BPFMD */
888 switch (bpfmd) {
889 case 32:
890 data |= (0x0 << 8);
891 break;
892 case 64:
893 data |= (0x1 << 8);
894 break;
895 case 128:
896 data |= (0x2 << 8);
897 break;
898 case 256:
899 data |= (0x3 << 8);
900 break;
901 case 512:
902 data |= (0x4 << 8);
903 break;
904 case 16:
905 data |= (0x7 << 8);
906 break;
907 default:
908 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
909 return -EINVAL;
910 }
911
912 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
913
914 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
915 udelay(10);
916
917 return 0;
918 }
919
920 static int fsi_clk_set_rate_external(struct device *dev,
921 struct fsi_priv *fsi)
922 {
923 struct clk *xck = fsi->clock.xck;
924 struct clk *ick = fsi->clock.ick;
925 unsigned long rate = fsi->clock.rate;
926 unsigned long xrate;
927 int ackmd, bpfmd;
928 int ret = 0;
929
930 /* check clock rate */
931 xrate = clk_get_rate(xck);
932 if (xrate % rate) {
933 dev_err(dev, "unsupported clock rate\n");
934 return -EINVAL;
935 }
936
937 clk_set_parent(ick, xck);
938 clk_set_rate(ick, xrate);
939
940 bpfmd = fsi->chan_num * 32;
941 ackmd = xrate / rate;
942
943 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
944
945 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
946 if (ret < 0)
947 dev_err(dev, "%s failed", __func__);
948
949 return ret;
950 }
951
952 static int fsi_clk_set_rate_cpg(struct device *dev,
953 struct fsi_priv *fsi)
954 {
955 struct clk *ick = fsi->clock.ick;
956 struct clk *div = fsi->clock.div;
957 unsigned long rate = fsi->clock.rate;
958 unsigned long target = 0; /* 12288000 or 11289600 */
959 unsigned long actual, cout;
960 unsigned long diff, min;
961 unsigned long best_cout, best_act;
962 int adj;
963 int ackmd, bpfmd;
964 int ret = -EINVAL;
965
966 if (!(12288000 % rate))
967 target = 12288000;
968 if (!(11289600 % rate))
969 target = 11289600;
970 if (!target) {
971 dev_err(dev, "unsupported rate\n");
972 return ret;
973 }
974
975 bpfmd = fsi->chan_num * 32;
976 ackmd = target / rate;
977 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
978 if (ret < 0) {
979 dev_err(dev, "%s failed", __func__);
980 return ret;
981 }
982
983 /*
984 * The clock flow is
985 *
986 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
987 *
988 * But, it needs to find best match of CPG and FSI_DIV
989 * combination, since it is difficult to generate correct
990 * frequency of audio clock from ick clock only.
991 * Because ick is created from its parent clock.
992 *
993 * target = rate x [512/256/128/64]fs
994 * cout = round(target x adjustment)
995 * actual = cout / adjustment (by FSI-DIV) ~= target
996 * audio = actual
997 */
998 min = ~0;
999 best_cout = 0;
1000 best_act = 0;
1001 for (adj = 1; adj < 0xffff; adj++) {
1002
1003 cout = target * adj;
1004 if (cout > 100000000) /* max clock = 100MHz */
1005 break;
1006
1007 /* cout/actual audio clock */
1008 cout = clk_round_rate(ick, cout);
1009 actual = cout / adj;
1010
1011 /* find best frequency */
1012 diff = abs(actual - target);
1013 if (diff < min) {
1014 min = diff;
1015 best_cout = cout;
1016 best_act = actual;
1017 }
1018 }
1019
1020 ret = clk_set_rate(ick, best_cout);
1021 if (ret < 0) {
1022 dev_err(dev, "ick clock failed\n");
1023 return -EIO;
1024 }
1025
1026 ret = clk_set_rate(div, clk_round_rate(div, best_act));
1027 if (ret < 0) {
1028 dev_err(dev, "div clock failed\n");
1029 return -EIO;
1030 }
1031
1032 dev_dbg(dev, "ick/div = %ld/%ld\n",
1033 clk_get_rate(ick), clk_get_rate(div));
1034
1035 return ret;
1036 }
1037
1038 static void fsi_pointer_update(struct fsi_stream *io, int size)
1039 {
1040 io->buff_sample_pos += size;
1041
1042 if (io->buff_sample_pos >=
1043 io->period_samples * (io->period_pos + 1)) {
1044 struct snd_pcm_substream *substream = io->substream;
1045 struct snd_pcm_runtime *runtime = substream->runtime;
1046
1047 io->period_pos++;
1048
1049 if (io->period_pos >= runtime->periods) {
1050 io->buff_sample_pos = 0;
1051 io->period_pos = 0;
1052 }
1053
1054 snd_pcm_period_elapsed(substream);
1055 }
1056 }
1057
1058 /*
1059 * pio data transfer handler
1060 */
1061 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1062 {
1063 int i;
1064
1065 if (fsi_is_enable_stream(fsi)) {
1066 /*
1067 * stream mode
1068 * see
1069 * fsi_pio_push_init()
1070 */
1071 u32 *buf = (u32 *)_buf;
1072
1073 for (i = 0; i < samples / 2; i++)
1074 fsi_reg_write(fsi, DODT, buf[i]);
1075 } else {
1076 /* normal mode */
1077 u16 *buf = (u16 *)_buf;
1078
1079 for (i = 0; i < samples; i++)
1080 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1081 }
1082 }
1083
1084 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1085 {
1086 u16 *buf = (u16 *)_buf;
1087 int i;
1088
1089 for (i = 0; i < samples; i++)
1090 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1091 }
1092
1093 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1094 {
1095 u32 *buf = (u32 *)_buf;
1096 int i;
1097
1098 for (i = 0; i < samples; i++)
1099 fsi_reg_write(fsi, DODT, *(buf + i));
1100 }
1101
1102 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1103 {
1104 u32 *buf = (u32 *)_buf;
1105 int i;
1106
1107 for (i = 0; i < samples; i++)
1108 *(buf + i) = fsi_reg_read(fsi, DIDT);
1109 }
1110
1111 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1112 {
1113 struct snd_pcm_runtime *runtime = io->substream->runtime;
1114
1115 return runtime->dma_area +
1116 samples_to_bytes(runtime, io->buff_sample_pos);
1117 }
1118
1119 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1120 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1121 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1122 int samples)
1123 {
1124 u8 *buf;
1125
1126 if (!fsi_stream_is_working(fsi, io))
1127 return -EINVAL;
1128
1129 buf = fsi_pio_get_area(fsi, io);
1130
1131 switch (io->sample_width) {
1132 case 2:
1133 run16(fsi, buf, samples);
1134 break;
1135 case 4:
1136 run32(fsi, buf, samples);
1137 break;
1138 default:
1139 return -EINVAL;
1140 }
1141
1142 fsi_pointer_update(io, samples);
1143
1144 return 0;
1145 }
1146
1147 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1148 {
1149 int sample_residues; /* samples in FSI fifo */
1150 int sample_space; /* ALSA free samples space */
1151 int samples;
1152
1153 sample_residues = fsi_get_current_fifo_samples(fsi, io);
1154 sample_space = io->buff_sample_capa - io->buff_sample_pos;
1155
1156 samples = min(sample_residues, sample_space);
1157
1158 return fsi_pio_transfer(fsi, io,
1159 fsi_pio_pop16,
1160 fsi_pio_pop32,
1161 samples);
1162 }
1163
1164 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1165 {
1166 int sample_residues; /* ALSA residue samples */
1167 int sample_space; /* FSI fifo free samples space */
1168 int samples;
1169
1170 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1171 sample_space = io->fifo_sample_capa -
1172 fsi_get_current_fifo_samples(fsi, io);
1173
1174 samples = min(sample_residues, sample_space);
1175
1176 return fsi_pio_transfer(fsi, io,
1177 fsi_pio_push16,
1178 fsi_pio_push32,
1179 samples);
1180 }
1181
1182 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1183 int enable)
1184 {
1185 struct fsi_master *master = fsi_get_master(fsi);
1186 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1187
1188 if (enable)
1189 fsi_irq_enable(fsi, io);
1190 else
1191 fsi_irq_disable(fsi, io);
1192
1193 if (fsi_is_clk_master(fsi))
1194 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1195
1196 return 0;
1197 }
1198
1199 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1200 {
1201 /*
1202 * we can use 16bit stream mode
1203 * when "playback" and "16bit data"
1204 * and platform allows "stream mode"
1205 * see
1206 * fsi_pio_push16()
1207 */
1208 if (fsi_is_enable_stream(fsi))
1209 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1210 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1211 else
1212 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1213 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1214 return 0;
1215 }
1216
1217 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1218 {
1219 /*
1220 * always 24bit bus, package back when "capture"
1221 */
1222 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1223 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1224 return 0;
1225 }
1226
1227 static struct fsi_stream_handler fsi_pio_push_handler = {
1228 .init = fsi_pio_push_init,
1229 .transfer = fsi_pio_push,
1230 .start_stop = fsi_pio_start_stop,
1231 };
1232
1233 static struct fsi_stream_handler fsi_pio_pop_handler = {
1234 .init = fsi_pio_pop_init,
1235 .transfer = fsi_pio_pop,
1236 .start_stop = fsi_pio_start_stop,
1237 };
1238
1239 static irqreturn_t fsi_interrupt(int irq, void *data)
1240 {
1241 struct fsi_master *master = data;
1242 u32 int_st = fsi_irq_get_status(master);
1243
1244 /* clear irq status */
1245 fsi_master_mask_set(master, SOFT_RST, IR, 0);
1246 fsi_master_mask_set(master, SOFT_RST, IR, IR);
1247
1248 if (int_st & AB_IO(1, AO_SHIFT))
1249 fsi_stream_transfer(&master->fsia.playback);
1250 if (int_st & AB_IO(1, BO_SHIFT))
1251 fsi_stream_transfer(&master->fsib.playback);
1252 if (int_st & AB_IO(1, AI_SHIFT))
1253 fsi_stream_transfer(&master->fsia.capture);
1254 if (int_st & AB_IO(1, BI_SHIFT))
1255 fsi_stream_transfer(&master->fsib.capture);
1256
1257 fsi_count_fifo_err(&master->fsia);
1258 fsi_count_fifo_err(&master->fsib);
1259
1260 fsi_irq_clear_status(&master->fsia);
1261 fsi_irq_clear_status(&master->fsib);
1262
1263 return IRQ_HANDLED;
1264 }
1265
1266 /*
1267 * dma data transfer handler
1268 */
1269 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1270 {
1271 /*
1272 * 24bit data : 24bit bus / package in back
1273 * 16bit data : 16bit bus / stream mode
1274 */
1275 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1276 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1277
1278 return 0;
1279 }
1280
1281 static void fsi_dma_complete(void *data)
1282 {
1283 struct fsi_stream *io = (struct fsi_stream *)data;
1284 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1285
1286 fsi_pointer_update(io, io->period_samples);
1287
1288 fsi_count_fifo_err(fsi);
1289 }
1290
1291 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1292 {
1293 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1294 struct snd_pcm_substream *substream = io->substream;
1295 struct dma_async_tx_descriptor *desc;
1296 int is_play = fsi_stream_is_play(fsi, io);
1297 enum dma_transfer_direction dir;
1298 int ret = -EIO;
1299
1300 if (is_play)
1301 dir = DMA_MEM_TO_DEV;
1302 else
1303 dir = DMA_DEV_TO_MEM;
1304
1305 desc = dmaengine_prep_dma_cyclic(io->chan,
1306 substream->runtime->dma_addr,
1307 snd_pcm_lib_buffer_bytes(substream),
1308 snd_pcm_lib_period_bytes(substream),
1309 dir,
1310 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1311 if (!desc) {
1312 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
1313 goto fsi_dma_transfer_err;
1314 }
1315
1316 desc->callback = fsi_dma_complete;
1317 desc->callback_param = io;
1318
1319 if (dmaengine_submit(desc) < 0) {
1320 dev_err(dai->dev, "tx_submit() fail\n");
1321 goto fsi_dma_transfer_err;
1322 }
1323
1324 dma_async_issue_pending(io->chan);
1325
1326 /*
1327 * FIXME
1328 *
1329 * In DMAEngine case, codec and FSI cannot be started simultaneously
1330 * since FSI is using the scheduler work queue.
1331 * Therefore, in capture case, probably FSI FIFO will have got
1332 * overflow error in this point.
1333 * in that case, DMA cannot start transfer until error was cleared.
1334 */
1335 if (!is_play) {
1336 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1337 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1338 fsi_reg_write(fsi, DIFF_ST, 0);
1339 }
1340 }
1341
1342 ret = 0;
1343
1344 fsi_dma_transfer_err:
1345 return ret;
1346 }
1347
1348 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1349 int start)
1350 {
1351 struct fsi_master *master = fsi_get_master(fsi);
1352 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1353 u32 enable = start ? DMA_ON : 0;
1354
1355 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1356
1357 dmaengine_terminate_all(io->chan);
1358
1359 if (fsi_is_clk_master(fsi))
1360 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1361
1362 return 0;
1363 }
1364
1365 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1366 {
1367 dma_cap_mask_t mask;
1368 int is_play = fsi_stream_is_play(fsi, io);
1369
1370 dma_cap_zero(mask);
1371 dma_cap_set(DMA_SLAVE, mask);
1372
1373 io->chan = dma_request_slave_channel_compat(mask,
1374 shdma_chan_filter, (void *)io->dma_id,
1375 dev, is_play ? "tx" : "rx");
1376 if (io->chan) {
1377 struct dma_slave_config cfg;
1378 int ret;
1379
1380 cfg.slave_id = io->dma_id;
1381 cfg.dst_addr = 0; /* use default addr */
1382 cfg.src_addr = 0; /* use default addr */
1383 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1384
1385 ret = dmaengine_slave_config(io->chan, &cfg);
1386 if (ret < 0) {
1387 dma_release_channel(io->chan);
1388 io->chan = NULL;
1389 }
1390 }
1391
1392 if (!io->chan) {
1393
1394 /* switch to PIO handler */
1395 if (is_play)
1396 fsi->playback.handler = &fsi_pio_push_handler;
1397 else
1398 fsi->capture.handler = &fsi_pio_pop_handler;
1399
1400 dev_info(dev, "switch handler (dma => pio)\n");
1401
1402 /* probe again */
1403 return fsi_stream_probe(fsi, dev);
1404 }
1405
1406 return 0;
1407 }
1408
1409 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1410 {
1411 fsi_stream_stop(fsi, io);
1412
1413 if (io->chan)
1414 dma_release_channel(io->chan);
1415
1416 io->chan = NULL;
1417 return 0;
1418 }
1419
1420 static struct fsi_stream_handler fsi_dma_push_handler = {
1421 .init = fsi_dma_init,
1422 .probe = fsi_dma_probe,
1423 .transfer = fsi_dma_transfer,
1424 .remove = fsi_dma_remove,
1425 .start_stop = fsi_dma_push_start_stop,
1426 };
1427
1428 /*
1429 * dai ops
1430 */
1431 static void fsi_fifo_init(struct fsi_priv *fsi,
1432 struct fsi_stream *io,
1433 struct device *dev)
1434 {
1435 struct fsi_master *master = fsi_get_master(fsi);
1436 int is_play = fsi_stream_is_play(fsi, io);
1437 u32 shift, i;
1438 int frame_capa;
1439
1440 /* get on-chip RAM capacity */
1441 shift = fsi_master_read(master, FIFO_SZ);
1442 shift >>= fsi_get_port_shift(fsi, io);
1443 shift &= FIFO_SZ_MASK;
1444 frame_capa = 256 << shift;
1445 dev_dbg(dev, "fifo = %d words\n", frame_capa);
1446
1447 /*
1448 * The maximum number of sample data varies depending
1449 * on the number of channels selected for the format.
1450 *
1451 * FIFOs are used in 4-channel units in 3-channel mode
1452 * and in 8-channel units in 5- to 7-channel mode
1453 * meaning that more FIFOs than the required size of DPRAM
1454 * are used.
1455 *
1456 * ex) if 256 words of DP-RAM is connected
1457 * 1 channel: 256 (256 x 1 = 256)
1458 * 2 channels: 128 (128 x 2 = 256)
1459 * 3 channels: 64 ( 64 x 3 = 192)
1460 * 4 channels: 64 ( 64 x 4 = 256)
1461 * 5 channels: 32 ( 32 x 5 = 160)
1462 * 6 channels: 32 ( 32 x 6 = 192)
1463 * 7 channels: 32 ( 32 x 7 = 224)
1464 * 8 channels: 32 ( 32 x 8 = 256)
1465 */
1466 for (i = 1; i < fsi->chan_num; i <<= 1)
1467 frame_capa >>= 1;
1468 dev_dbg(dev, "%d channel %d store\n",
1469 fsi->chan_num, frame_capa);
1470
1471 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1472
1473 /*
1474 * set interrupt generation factor
1475 * clear FIFO
1476 */
1477 if (is_play) {
1478 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
1479 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
1480 } else {
1481 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
1482 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1483 }
1484 }
1485
1486 static int fsi_hw_startup(struct fsi_priv *fsi,
1487 struct fsi_stream *io,
1488 struct device *dev)
1489 {
1490 u32 data = 0;
1491
1492 /* clock setting */
1493 if (fsi_is_clk_master(fsi))
1494 data = DIMD | DOMD;
1495
1496 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1497
1498 /* clock inversion (CKG2) */
1499 data = 0;
1500 if (fsi->bit_clk_inv)
1501 data |= (1 << 0);
1502 if (fsi->lr_clk_inv)
1503 data |= (1 << 4);
1504 if (fsi_is_clk_master(fsi))
1505 data <<= 8;
1506 fsi_reg_write(fsi, CKG2, data);
1507
1508 /* spdif ? */
1509 if (fsi_is_spdif(fsi)) {
1510 fsi_spdif_clk_ctrl(fsi, 1);
1511 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1512 }
1513
1514 /*
1515 * get bus settings
1516 */
1517 data = 0;
1518 switch (io->sample_width) {
1519 case 2:
1520 data = BUSOP_GET(16, io->bus_option);
1521 break;
1522 case 4:
1523 data = BUSOP_GET(24, io->bus_option);
1524 break;
1525 }
1526 fsi_format_bus_setup(fsi, io, data, dev);
1527
1528 /* irq clear */
1529 fsi_irq_disable(fsi, io);
1530 fsi_irq_clear_status(fsi);
1531
1532 /* fifo init */
1533 fsi_fifo_init(fsi, io, dev);
1534
1535 /* start master clock */
1536 if (fsi_is_clk_master(fsi))
1537 return fsi_clk_enable(dev, fsi);
1538
1539 return 0;
1540 }
1541
1542 static int fsi_hw_shutdown(struct fsi_priv *fsi,
1543 struct device *dev)
1544 {
1545 /* stop master clock */
1546 if (fsi_is_clk_master(fsi))
1547 return fsi_clk_disable(dev, fsi);
1548
1549 return 0;
1550 }
1551
1552 static int fsi_dai_startup(struct snd_pcm_substream *substream,
1553 struct snd_soc_dai *dai)
1554 {
1555 struct fsi_priv *fsi = fsi_get_priv(substream);
1556
1557 fsi_clk_invalid(fsi);
1558
1559 return 0;
1560 }
1561
1562 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1563 struct snd_soc_dai *dai)
1564 {
1565 struct fsi_priv *fsi = fsi_get_priv(substream);
1566
1567 fsi_clk_invalid(fsi);
1568 }
1569
1570 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1571 struct snd_soc_dai *dai)
1572 {
1573 struct fsi_priv *fsi = fsi_get_priv(substream);
1574 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1575 int ret = 0;
1576
1577 switch (cmd) {
1578 case SNDRV_PCM_TRIGGER_START:
1579 fsi_stream_init(fsi, io, substream);
1580 if (!ret)
1581 ret = fsi_hw_startup(fsi, io, dai->dev);
1582 if (!ret)
1583 ret = fsi_stream_start(fsi, io);
1584 if (!ret)
1585 ret = fsi_stream_transfer(io);
1586 break;
1587 case SNDRV_PCM_TRIGGER_STOP:
1588 if (!ret)
1589 ret = fsi_hw_shutdown(fsi, dai->dev);
1590 fsi_stream_stop(fsi, io);
1591 fsi_stream_quit(fsi, io);
1592 break;
1593 }
1594
1595 return ret;
1596 }
1597
1598 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1599 {
1600 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1601 case SND_SOC_DAIFMT_I2S:
1602 fsi->fmt = CR_I2S;
1603 fsi->chan_num = 2;
1604 break;
1605 case SND_SOC_DAIFMT_LEFT_J:
1606 fsi->fmt = CR_PCM;
1607 fsi->chan_num = 2;
1608 break;
1609 default:
1610 return -EINVAL;
1611 }
1612
1613 return 0;
1614 }
1615
1616 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1617 {
1618 struct fsi_master *master = fsi_get_master(fsi);
1619
1620 if (fsi_version(master) < 2)
1621 return -EINVAL;
1622
1623 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1624 fsi->chan_num = 2;
1625
1626 return 0;
1627 }
1628
1629 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1630 {
1631 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1632 int ret;
1633
1634 /* set master/slave audio interface */
1635 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1636 case SND_SOC_DAIFMT_CBM_CFM:
1637 break;
1638 case SND_SOC_DAIFMT_CBS_CFS:
1639 fsi->clk_master = 1; /* codec is slave, cpu is master */
1640 break;
1641 default:
1642 return -EINVAL;
1643 }
1644
1645 /* set clock inversion */
1646 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1647 case SND_SOC_DAIFMT_NB_IF:
1648 fsi->bit_clk_inv = 0;
1649 fsi->lr_clk_inv = 1;
1650 break;
1651 case SND_SOC_DAIFMT_IB_NF:
1652 fsi->bit_clk_inv = 1;
1653 fsi->lr_clk_inv = 0;
1654 break;
1655 case SND_SOC_DAIFMT_IB_IF:
1656 fsi->bit_clk_inv = 1;
1657 fsi->lr_clk_inv = 1;
1658 break;
1659 case SND_SOC_DAIFMT_NB_NF:
1660 default:
1661 fsi->bit_clk_inv = 0;
1662 fsi->lr_clk_inv = 0;
1663 break;
1664 }
1665
1666 if (fsi_is_clk_master(fsi)) {
1667 if (fsi->clk_cpg)
1668 fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1669 fsi_clk_set_rate_cpg);
1670 else
1671 fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1672 fsi_clk_set_rate_external);
1673 }
1674
1675 /* set format */
1676 if (fsi_is_spdif(fsi))
1677 ret = fsi_set_fmt_spdif(fsi);
1678 else
1679 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1680
1681 return ret;
1682 }
1683
1684 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1685 struct snd_pcm_hw_params *params,
1686 struct snd_soc_dai *dai)
1687 {
1688 struct fsi_priv *fsi = fsi_get_priv(substream);
1689
1690 if (fsi_is_clk_master(fsi))
1691 fsi_clk_valid(fsi, params_rate(params));
1692
1693 return 0;
1694 }
1695
1696 static const struct snd_soc_dai_ops fsi_dai_ops = {
1697 .startup = fsi_dai_startup,
1698 .shutdown = fsi_dai_shutdown,
1699 .trigger = fsi_dai_trigger,
1700 .set_fmt = fsi_dai_set_fmt,
1701 .hw_params = fsi_dai_hw_params,
1702 };
1703
1704 /*
1705 * pcm ops
1706 */
1707
1708 static struct snd_pcm_hardware fsi_pcm_hardware = {
1709 .info = SNDRV_PCM_INFO_INTERLEAVED |
1710 SNDRV_PCM_INFO_MMAP |
1711 SNDRV_PCM_INFO_MMAP_VALID,
1712 .buffer_bytes_max = 64 * 1024,
1713 .period_bytes_min = 32,
1714 .period_bytes_max = 8192,
1715 .periods_min = 1,
1716 .periods_max = 32,
1717 .fifo_size = 256,
1718 };
1719
1720 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1721 {
1722 struct snd_pcm_runtime *runtime = substream->runtime;
1723 int ret = 0;
1724
1725 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1726
1727 ret = snd_pcm_hw_constraint_integer(runtime,
1728 SNDRV_PCM_HW_PARAM_PERIODS);
1729
1730 return ret;
1731 }
1732
1733 static int fsi_hw_params(struct snd_pcm_substream *substream,
1734 struct snd_pcm_hw_params *hw_params)
1735 {
1736 return snd_pcm_lib_malloc_pages(substream,
1737 params_buffer_bytes(hw_params));
1738 }
1739
1740 static int fsi_hw_free(struct snd_pcm_substream *substream)
1741 {
1742 return snd_pcm_lib_free_pages(substream);
1743 }
1744
1745 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1746 {
1747 struct fsi_priv *fsi = fsi_get_priv(substream);
1748 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1749
1750 return fsi_sample2frame(fsi, io->buff_sample_pos);
1751 }
1752
1753 static struct snd_pcm_ops fsi_pcm_ops = {
1754 .open = fsi_pcm_open,
1755 .ioctl = snd_pcm_lib_ioctl,
1756 .hw_params = fsi_hw_params,
1757 .hw_free = fsi_hw_free,
1758 .pointer = fsi_pointer,
1759 };
1760
1761 /*
1762 * snd_soc_platform
1763 */
1764
1765 #define PREALLOC_BUFFER (32 * 1024)
1766 #define PREALLOC_BUFFER_MAX (32 * 1024)
1767
1768 static void fsi_pcm_free(struct snd_pcm *pcm)
1769 {
1770 snd_pcm_lib_preallocate_free_for_all(pcm);
1771 }
1772
1773 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1774 {
1775 return snd_pcm_lib_preallocate_pages_for_all(
1776 rtd->pcm,
1777 SNDRV_DMA_TYPE_DEV,
1778 rtd->card->snd_card->dev,
1779 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1780 }
1781
1782 /*
1783 * alsa struct
1784 */
1785
1786 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1787 {
1788 .name = "fsia-dai",
1789 .playback = {
1790 .rates = FSI_RATES,
1791 .formats = FSI_FMTS,
1792 .channels_min = 2,
1793 .channels_max = 2,
1794 },
1795 .capture = {
1796 .rates = FSI_RATES,
1797 .formats = FSI_FMTS,
1798 .channels_min = 2,
1799 .channels_max = 2,
1800 },
1801 .ops = &fsi_dai_ops,
1802 },
1803 {
1804 .name = "fsib-dai",
1805 .playback = {
1806 .rates = FSI_RATES,
1807 .formats = FSI_FMTS,
1808 .channels_min = 2,
1809 .channels_max = 2,
1810 },
1811 .capture = {
1812 .rates = FSI_RATES,
1813 .formats = FSI_FMTS,
1814 .channels_min = 2,
1815 .channels_max = 2,
1816 },
1817 .ops = &fsi_dai_ops,
1818 },
1819 };
1820
1821 static struct snd_soc_platform_driver fsi_soc_platform = {
1822 .ops = &fsi_pcm_ops,
1823 .pcm_new = fsi_pcm_new,
1824 .pcm_free = fsi_pcm_free,
1825 };
1826
1827 static const struct snd_soc_component_driver fsi_soc_component = {
1828 .name = "fsi",
1829 };
1830
1831 /*
1832 * platform function
1833 */
1834 static void fsi_of_parse(char *name,
1835 struct device_node *np,
1836 struct sh_fsi_port_info *info,
1837 struct device *dev)
1838 {
1839 int i;
1840 char prop[128];
1841 unsigned long flags = 0;
1842 struct {
1843 char *name;
1844 unsigned int val;
1845 } of_parse_property[] = {
1846 { "spdif-connection", SH_FSI_FMT_SPDIF },
1847 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
1848 { "use-internal-clock", SH_FSI_CLK_CPG },
1849 };
1850
1851 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1852 sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1853 if (of_get_property(np, prop, NULL))
1854 flags |= of_parse_property[i].val;
1855 }
1856 info->flags = flags;
1857
1858 dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1859 }
1860
1861 static void fsi_port_info_init(struct fsi_priv *fsi,
1862 struct sh_fsi_port_info *info)
1863 {
1864 if (info->flags & SH_FSI_FMT_SPDIF)
1865 fsi->spdif = 1;
1866
1867 if (info->flags & SH_FSI_CLK_CPG)
1868 fsi->clk_cpg = 1;
1869
1870 if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1871 fsi->enable_stream = 1;
1872 }
1873
1874 static void fsi_handler_init(struct fsi_priv *fsi,
1875 struct sh_fsi_port_info *info)
1876 {
1877 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
1878 fsi->playback.priv = fsi;
1879 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
1880 fsi->capture.priv = fsi;
1881
1882 if (info->tx_id) {
1883 fsi->playback.dma_id = info->tx_id;
1884 fsi->playback.handler = &fsi_dma_push_handler;
1885 }
1886 }
1887
1888 static struct of_device_id fsi_of_match[];
1889 static int fsi_probe(struct platform_device *pdev)
1890 {
1891 struct fsi_master *master;
1892 struct device_node *np = pdev->dev.of_node;
1893 struct sh_fsi_platform_info info;
1894 const struct fsi_core *core;
1895 struct fsi_priv *fsi;
1896 struct resource *res;
1897 unsigned int irq;
1898 int ret;
1899
1900 memset(&info, 0, sizeof(info));
1901
1902 core = NULL;
1903 if (np) {
1904 const struct of_device_id *of_id;
1905
1906 of_id = of_match_device(fsi_of_match, &pdev->dev);
1907 if (of_id) {
1908 core = of_id->data;
1909 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1910 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1911 }
1912 } else {
1913 const struct platform_device_id *id_entry = pdev->id_entry;
1914 if (id_entry)
1915 core = (struct fsi_core *)id_entry->driver_data;
1916
1917 if (pdev->dev.platform_data)
1918 memcpy(&info, pdev->dev.platform_data, sizeof(info));
1919 }
1920
1921 if (!core) {
1922 dev_err(&pdev->dev, "unknown fsi device\n");
1923 return -ENODEV;
1924 }
1925
1926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1927 irq = platform_get_irq(pdev, 0);
1928 if (!res || (int)irq <= 0) {
1929 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1930 return -ENODEV;
1931 }
1932
1933 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1934 if (!master) {
1935 dev_err(&pdev->dev, "Could not allocate master\n");
1936 return -ENOMEM;
1937 }
1938
1939 master->base = devm_ioremap_nocache(&pdev->dev,
1940 res->start, resource_size(res));
1941 if (!master->base) {
1942 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1943 return -ENXIO;
1944 }
1945
1946 /* master setting */
1947 master->core = core;
1948 spin_lock_init(&master->lock);
1949
1950 /* FSI A setting */
1951 fsi = &master->fsia;
1952 fsi->base = master->base;
1953 fsi->master = master;
1954 fsi_port_info_init(fsi, &info.port_a);
1955 fsi_handler_init(fsi, &info.port_a);
1956 ret = fsi_stream_probe(fsi, &pdev->dev);
1957 if (ret < 0) {
1958 dev_err(&pdev->dev, "FSIA stream probe failed\n");
1959 return ret;
1960 }
1961
1962 /* FSI B setting */
1963 fsi = &master->fsib;
1964 fsi->base = master->base + 0x40;
1965 fsi->master = master;
1966 fsi_port_info_init(fsi, &info.port_b);
1967 fsi_handler_init(fsi, &info.port_b);
1968 ret = fsi_stream_probe(fsi, &pdev->dev);
1969 if (ret < 0) {
1970 dev_err(&pdev->dev, "FSIB stream probe failed\n");
1971 goto exit_fsia;
1972 }
1973
1974 pm_runtime_enable(&pdev->dev);
1975 dev_set_drvdata(&pdev->dev, master);
1976
1977 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
1978 dev_name(&pdev->dev), master);
1979 if (ret) {
1980 dev_err(&pdev->dev, "irq request err\n");
1981 goto exit_fsib;
1982 }
1983
1984 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1985 if (ret < 0) {
1986 dev_err(&pdev->dev, "cannot snd soc register\n");
1987 goto exit_fsib;
1988 }
1989
1990 ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component,
1991 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1992 if (ret < 0) {
1993 dev_err(&pdev->dev, "cannot snd component register\n");
1994 goto exit_snd_soc;
1995 }
1996
1997 return ret;
1998
1999 exit_snd_soc:
2000 snd_soc_unregister_platform(&pdev->dev);
2001 exit_fsib:
2002 pm_runtime_disable(&pdev->dev);
2003 fsi_stream_remove(&master->fsib);
2004 exit_fsia:
2005 fsi_stream_remove(&master->fsia);
2006
2007 return ret;
2008 }
2009
2010 static int fsi_remove(struct platform_device *pdev)
2011 {
2012 struct fsi_master *master;
2013
2014 master = dev_get_drvdata(&pdev->dev);
2015
2016 pm_runtime_disable(&pdev->dev);
2017
2018 snd_soc_unregister_component(&pdev->dev);
2019 snd_soc_unregister_platform(&pdev->dev);
2020
2021 fsi_stream_remove(&master->fsia);
2022 fsi_stream_remove(&master->fsib);
2023
2024 return 0;
2025 }
2026
2027 static void __fsi_suspend(struct fsi_priv *fsi,
2028 struct fsi_stream *io,
2029 struct device *dev)
2030 {
2031 if (!fsi_stream_is_working(fsi, io))
2032 return;
2033
2034 fsi_stream_stop(fsi, io);
2035 fsi_hw_shutdown(fsi, dev);
2036 }
2037
2038 static void __fsi_resume(struct fsi_priv *fsi,
2039 struct fsi_stream *io,
2040 struct device *dev)
2041 {
2042 if (!fsi_stream_is_working(fsi, io))
2043 return;
2044
2045 fsi_hw_startup(fsi, io, dev);
2046 fsi_stream_start(fsi, io);
2047 }
2048
2049 static int fsi_suspend(struct device *dev)
2050 {
2051 struct fsi_master *master = dev_get_drvdata(dev);
2052 struct fsi_priv *fsia = &master->fsia;
2053 struct fsi_priv *fsib = &master->fsib;
2054
2055 __fsi_suspend(fsia, &fsia->playback, dev);
2056 __fsi_suspend(fsia, &fsia->capture, dev);
2057
2058 __fsi_suspend(fsib, &fsib->playback, dev);
2059 __fsi_suspend(fsib, &fsib->capture, dev);
2060
2061 return 0;
2062 }
2063
2064 static int fsi_resume(struct device *dev)
2065 {
2066 struct fsi_master *master = dev_get_drvdata(dev);
2067 struct fsi_priv *fsia = &master->fsia;
2068 struct fsi_priv *fsib = &master->fsib;
2069
2070 __fsi_resume(fsia, &fsia->playback, dev);
2071 __fsi_resume(fsia, &fsia->capture, dev);
2072
2073 __fsi_resume(fsib, &fsib->playback, dev);
2074 __fsi_resume(fsib, &fsib->capture, dev);
2075
2076 return 0;
2077 }
2078
2079 static struct dev_pm_ops fsi_pm_ops = {
2080 .suspend = fsi_suspend,
2081 .resume = fsi_resume,
2082 };
2083
2084 static struct fsi_core fsi1_core = {
2085 .ver = 1,
2086
2087 /* Interrupt */
2088 .int_st = INT_ST,
2089 .iemsk = IEMSK,
2090 .imsk = IMSK,
2091 };
2092
2093 static struct fsi_core fsi2_core = {
2094 .ver = 2,
2095
2096 /* Interrupt */
2097 .int_st = CPU_INT_ST,
2098 .iemsk = CPU_IEMSK,
2099 .imsk = CPU_IMSK,
2100 .a_mclk = A_MST_CTLR,
2101 .b_mclk = B_MST_CTLR,
2102 };
2103
2104 static struct of_device_id fsi_of_match[] = {
2105 { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
2106 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
2107 {},
2108 };
2109 MODULE_DEVICE_TABLE(of, fsi_of_match);
2110
2111 static struct platform_device_id fsi_id_table[] = {
2112 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
2113 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
2114 {},
2115 };
2116 MODULE_DEVICE_TABLE(platform, fsi_id_table);
2117
2118 static struct platform_driver fsi_driver = {
2119 .driver = {
2120 .name = "fsi-pcm-audio",
2121 .pm = &fsi_pm_ops,
2122 .of_match_table = fsi_of_match,
2123 },
2124 .probe = fsi_probe,
2125 .remove = fsi_remove,
2126 .id_table = fsi_id_table,
2127 };
2128
2129 module_platform_driver(fsi_driver);
2130
2131 MODULE_LICENSE("GPL");
2132 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2133 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2134 MODULE_ALIAS("platform:fsi-pcm-audio");
Linux kernel - Deliverables
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