2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk-provider.h>
25 #define BRRx_MASK(x) (0x3FF & x)
27 static struct rsnd_mod_ops adg_ops
= {
32 struct clk
*clk
[CLKMAX
];
33 struct clk
*clkout
[CLKOUTMAX
];
34 struct clk_onecell_data onecell
;
38 int rbga_rate_for_441khz
; /* RBGA */
39 int rbgb_rate_for_48khz
; /* RBGB */
42 #define LRCLK_ASYNC (1 << 0)
43 #define adg_mode_flags(adg) (adg->flags)
45 #define for_each_rsnd_clk(pos, adg, i) \
48 ((pos) = adg->clk[i]); \
50 #define for_each_rsnd_clkout(pos, adg, i) \
53 ((pos) = adg->clkout[i]); \
55 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
57 static u32
rsnd_adg_calculate_rbgx(unsigned long div
)
64 for (i
= 3; i
>= 0; i
--) {
66 if (0 == (div
% ratio
))
67 return (u32
)((i
<< 8) | ((div
/ ratio
) - 1));
73 static u32
rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream
*io
)
75 struct rsnd_mod
*ssi_mod
= rsnd_io_to_mod_ssi(io
);
76 int id
= rsnd_mod_id(ssi_mod
);
79 if (rsnd_ssi_is_pin_sharing(io
)) {
94 return (0x6 + ws
) << 8;
97 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv
*priv
,
98 struct rsnd_dai_stream
*io
,
99 unsigned int target_rate
,
100 unsigned int *target_val
,
101 unsigned int *target_en
)
103 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
104 struct device
*dev
= rsnd_priv_to_dev(priv
);
105 int idx
, sel
, div
, step
;
106 unsigned int val
, en
;
107 unsigned int min
, diff
;
108 unsigned int sel_rate
[] = {
109 clk_get_rate(adg
->clk
[CLKA
]), /* 0000: CLKA */
110 clk_get_rate(adg
->clk
[CLKB
]), /* 0001: CLKB */
111 clk_get_rate(adg
->clk
[CLKC
]), /* 0010: CLKC */
112 adg
->rbga_rate_for_441khz
, /* 0011: RBGA */
113 adg
->rbgb_rate_for_48khz
, /* 0100: RBGB */
119 for (sel
= 0; sel
< ARRAY_SIZE(sel_rate
); sel
++) {
126 for (div
= 2; div
<= 98304; div
+= step
) {
127 diff
= abs(target_rate
- sel_rate
[sel
] / div
);
129 val
= (sel
<< 8) | idx
;
131 en
= 1 << (sel
+ 1); /* fixme */
135 * step of 0_0000 / 0_0001 / 0_1101
138 if ((idx
> 2) && (idx
% 2))
149 dev_err(dev
, "no Input clock\n");
158 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv
*priv
,
159 struct rsnd_dai_stream
*io
,
160 unsigned int in_rate
,
161 unsigned int out_rate
,
162 u32
*in
, u32
*out
, u32
*en
)
164 struct snd_pcm_runtime
*runtime
= rsnd_io_to_runtime(io
);
165 unsigned int target_rate
;
171 /* default = SSI WS */
173 _out
= rsnd_adg_ssi_ws_timing_gen2(io
);
178 if (runtime
->rate
!= in_rate
) {
179 target_rate
= out_rate
;
181 } else if (runtime
->rate
!= out_rate
) {
182 target_rate
= in_rate
;
187 __rsnd_adg_get_timesel_ratio(priv
, io
,
199 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod
*cmd_mod
,
200 struct rsnd_dai_stream
*io
)
202 struct rsnd_priv
*priv
= rsnd_mod_to_priv(cmd_mod
);
203 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
204 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
205 int id
= rsnd_mod_id(cmd_mod
);
206 int shift
= (id
% 2) ? 16 : 0;
209 rsnd_adg_get_timesel_ratio(priv
, io
,
210 rsnd_src_get_in_rate(priv
, io
),
211 rsnd_src_get_out_rate(priv
, io
),
215 mask
= 0xffff << shift
;
217 rsnd_mod_bset(adg_mod
, CMDOUT_TIMSEL
, mask
, val
);
222 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod
*src_mod
,
223 struct rsnd_dai_stream
*io
,
224 unsigned int in_rate
,
225 unsigned int out_rate
)
227 struct rsnd_priv
*priv
= rsnd_mod_to_priv(src_mod
);
228 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
229 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
232 int id
= rsnd_mod_id(src_mod
);
233 int shift
= (id
% 2) ? 16 : 0;
235 rsnd_mod_confirm_src(src_mod
);
237 rsnd_adg_get_timesel_ratio(priv
, io
,
243 mask
= 0xffff << shift
;
247 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL0
, mask
, in
);
248 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL0
, mask
, out
);
251 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL1
, mask
, in
);
252 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL1
, mask
, out
);
255 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL2
, mask
, in
);
256 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL2
, mask
, out
);
259 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL3
, mask
, in
);
260 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL3
, mask
, out
);
263 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL4
, mask
, in
);
264 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL4
, mask
, out
);
269 rsnd_mod_bset(adg_mod
, DIV_EN
, en
, en
);
274 static void rsnd_adg_set_ssi_clk(struct rsnd_mod
*ssi_mod
, u32 val
)
276 struct rsnd_priv
*priv
= rsnd_mod_to_priv(ssi_mod
);
277 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
278 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
279 int id
= rsnd_mod_id(ssi_mod
);
280 int shift
= (id
% 4) * 8;
281 u32 mask
= 0xFF << shift
;
283 rsnd_mod_confirm_ssi(ssi_mod
);
288 * SSI 8 is not connected to ADG.
289 * it works with SSI 7
296 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL0
, mask
, val
);
299 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL1
, mask
, val
);
302 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL2
, mask
, val
);
307 int rsnd_adg_ssi_clk_stop(struct rsnd_mod
*ssi_mod
)
309 rsnd_adg_set_ssi_clk(ssi_mod
, 0);
314 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod
*ssi_mod
, unsigned int rate
)
316 struct rsnd_priv
*priv
= rsnd_mod_to_priv(ssi_mod
);
317 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
318 struct device
*dev
= rsnd_priv_to_dev(priv
);
329 dev_dbg(dev
, "request clock = %d\n", rate
);
332 * find suitable clock from
333 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
336 for_each_rsnd_clk(clk
, adg
, i
) {
337 if (rate
== clk_get_rate(clk
)) {
344 * find divided clock from BRGA/BRGB
346 if (rate
== adg
->rbga_rate_for_441khz
) {
351 if (rate
== adg
->rbgb_rate_for_48khz
) {
360 rsnd_adg_set_ssi_clk(ssi_mod
, data
);
362 if (!(adg_mode_flags(adg
) & LRCLK_ASYNC
)) {
363 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
366 if (0 == (rate
% 8000))
369 rsnd_mod_bset(adg_mod
, SSICKR
, 0x80000000, ckr
);
372 dev_dbg(dev
, "ADG: %s[%d] selects 0x%x for %d\n",
373 rsnd_mod_name(ssi_mod
), rsnd_mod_id(ssi_mod
),
379 static void rsnd_adg_get_clkin(struct rsnd_priv
*priv
,
380 struct rsnd_adg
*adg
)
382 struct device
*dev
= rsnd_priv_to_dev(priv
);
384 static const char * const clk_name
[] = {
392 for (i
= 0; i
< CLKMAX
; i
++) {
393 clk
= devm_clk_get(dev
, clk_name
[i
]);
394 adg
->clk
[i
] = IS_ERR(clk
) ? NULL
: clk
;
397 for_each_rsnd_clk(clk
, adg
, i
) {
398 ret
= clk_prepare_enable(clk
);
400 dev_warn(dev
, "can't use clk %d\n", i
);
402 dev_dbg(dev
, "clk %d : %p : %ld\n", i
, clk
, clk_get_rate(clk
));
406 static void rsnd_adg_get_clkout(struct rsnd_priv
*priv
,
407 struct rsnd_adg
*adg
)
410 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
411 struct device
*dev
= rsnd_priv_to_dev(priv
);
412 struct device_node
*np
= dev
->of_node
;
413 u32 ckr
, rbgx
, rbga
, rbgb
;
414 u32 rate
, req_rate
= 0, div
;
416 unsigned long req_48kHz_rate
, req_441kHz_rate
;
418 const char *parent_clk_name
= NULL
;
419 static const char * const clkout_name
[] = {
420 [CLKOUT
] = "audio_clkout",
421 [CLKOUT1
] = "audio_clkout1",
422 [CLKOUT2
] = "audio_clkout2",
423 [CLKOUT3
] = "audio_clkout3",
432 of_property_read_u32(np
, "#clock-cells", &count
);
435 * ADG supports BRRA/BRRB output only
436 * this means all clkout0/1/2/3 will be same rate
438 of_property_read_u32(np
, "clock-frequency", &req_rate
);
441 if (0 == (req_rate
% 44100))
442 req_441kHz_rate
= req_rate
;
443 if (0 == (req_rate
% 48000))
444 req_48kHz_rate
= req_rate
;
447 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
448 * have 44.1kHz or 48kHz base clocks for now.
450 * SSI itself can divide parent clock by 1/1 - 1/16
452 * rsnd_adg_ssi_clk_try_start()
453 * rsnd_ssi_master_clk_start()
456 rbga
= 2; /* default 1/6 */
457 rbgb
= 2; /* default 1/6 */
458 adg
->rbga_rate_for_441khz
= 0;
459 adg
->rbgb_rate_for_48khz
= 0;
460 for_each_rsnd_clk(clk
, adg
, i
) {
461 rate
= clk_get_rate(clk
);
463 if (0 == rate
) /* not used */
467 if (!adg
->rbga_rate_for_441khz
&& (0 == rate
% 44100)) {
470 div
= rate
/ req_441kHz_rate
;
471 rbgx
= rsnd_adg_calculate_rbgx(div
);
472 if (BRRx_MASK(rbgx
) == rbgx
) {
474 adg
->rbga_rate_for_441khz
= rate
/ div
;
475 ckr
|= brg_table
[i
] << 20;
477 parent_clk_name
= __clk_get_name(clk
);
482 if (!adg
->rbgb_rate_for_48khz
&& (0 == rate
% 48000)) {
485 div
= rate
/ req_48kHz_rate
;
486 rbgx
= rsnd_adg_calculate_rbgx(div
);
487 if (BRRx_MASK(rbgx
) == rbgx
) {
489 adg
->rbgb_rate_for_48khz
= rate
/ div
;
490 ckr
|= brg_table
[i
] << 16;
491 if (req_48kHz_rate
) {
492 parent_clk_name
= __clk_get_name(clk
);
500 * ADG supports BRRA/BRRB output only.
501 * this means all clkout0/1/2/3 will be * same rate
508 clk
= clk_register_fixed_rate(dev
, clkout_name
[CLKOUT
],
509 parent_clk_name
, 0, req_rate
);
511 adg
->clkout
[CLKOUT
] = clk
;
512 of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
519 for (i
= 0; i
< CLKOUTMAX
; i
++) {
520 clk
= clk_register_fixed_rate(dev
, clkout_name
[i
],
524 adg
->onecell
.clks
= adg
->clkout
;
525 adg
->onecell
.clk_num
= CLKOUTMAX
;
527 adg
->clkout
[i
] = clk
;
529 of_clk_add_provider(np
, of_clk_src_onecell_get
,
535 rsnd_mod_bset(adg_mod
, SSICKR
, 0x80FF0000, ckr
);
536 rsnd_mod_write(adg_mod
, BRRA
, rbga
);
537 rsnd_mod_write(adg_mod
, BRRB
, rbgb
);
539 for_each_rsnd_clkout(clk
, adg
, i
)
540 dev_dbg(dev
, "clkout %d : %p : %ld\n", i
, clk
, clk_get_rate(clk
));
541 dev_dbg(dev
, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
545 int rsnd_adg_probe(struct rsnd_priv
*priv
)
547 struct rsnd_adg
*adg
;
548 struct device
*dev
= rsnd_priv_to_dev(priv
);
549 struct device_node
*np
= dev
->of_node
;
551 adg
= devm_kzalloc(dev
, sizeof(*adg
), GFP_KERNEL
);
553 dev_err(dev
, "ADG allocate failed\n");
557 rsnd_mod_init(priv
, &adg
->mod
, &adg_ops
,
560 rsnd_adg_get_clkin(priv
, adg
);
561 rsnd_adg_get_clkout(priv
, adg
);
563 if (of_get_property(np
, "clkout-lr-asynchronous", NULL
))
564 adg
->flags
= LRCLK_ASYNC
;
571 void rsnd_adg_remove(struct rsnd_priv
*priv
)
573 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
577 for_each_rsnd_clk(clk
, adg
, i
) {
578 clk_disable_unprepare(clk
);
This page took 0.0596370000000001 seconds and 5 git commands to generate.