sound/soc/sh/rcar/adg.c

   1 /*
   2  * Helper routines for R-Car sound ADG.
   3  *
   4  *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/clk-provider.h>
  11 #include "rsnd.h"
  12
  13 #define CLKA    0
  14 #define CLKB    1
  15 #define CLKC    2
  16 #define CLKI    3
  17 #define CLKMAX  4
  18
  19 #define CLKOUT  0
  20 #define CLKOUT1 1
  21 #define CLKOUT2 2
  22 #define CLKOUT3 3
  23 #define CLKOUTMAX 4
  24
  25 #define BRRx_MASK(x) (0x3FF & x)
  26
  27 static struct rsnd_mod_ops adg_ops = {
  28         .name = "adg",
  29 };
  30
  31 struct rsnd_adg {
  32         struct clk *clk[CLKMAX];
  33         struct clk *clkout[CLKOUTMAX];
  34         struct clk_onecell_data onecell;
  35         struct rsnd_mod mod;
  36
  37         int rbga_rate_for_441khz; /* RBGA */
  38         int rbgb_rate_for_48khz;  /* RBGB */
  39 };
  40
  41 #define for_each_rsnd_clk(pos, adg, i)          \
  42         for (i = 0;                             \
  43              (i < CLKMAX) &&                    \
  44              ((pos) = adg->clk[i]);             \
  45              i++)
  46 #define for_each_rsnd_clkout(pos, adg, i)       \
  47         for (i = 0;                             \
  48              (i < CLKOUTMAX) &&                 \
  49              ((pos) = adg->clkout[i]);  \
  50              i++)
  51 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  52
  53 static u32 rsnd_adg_calculate_rbgx(unsigned long div)
  54 {
  55         int i, ratio;
  56
  57         if (!div)
  58                 return 0;
  59
  60         for (i = 3; i >= 0; i--) {
  61                 ratio = 2 << (i * 2);
  62                 if (0 == (div % ratio))
  63                         return (u32)((i << 8) | ((div / ratio) - 1));
  64         }
  65
  66         return ~0;
  67 }
  68
  69 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
  70 {
  71         struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
  72         int id = rsnd_mod_id(mod);
  73         int ws = id;
  74
  75         if (rsnd_ssi_is_pin_sharing(io)) {
  76                 switch (id) {
  77                 case 1:
  78                 case 2:
  79                         ws = 0;
  80                         break;
  81                 case 4:
  82                         ws = 3;
  83                         break;
  84                 case 8:
  85                         ws = 7;
  86                         break;
  87                 }
  88         }
  89
  90         return (0x6 + ws) << 8;
  91 }
  92
  93 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
  94                                  struct rsnd_dai_stream *io)
  95 {
  96         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  97         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
  98         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
  99         int id = rsnd_mod_id(mod);
 100         int shift = (id % 2) ? 16 : 0;
 101         u32 mask, val;
 102
 103         val = rsnd_adg_ssi_ws_timing_gen2(io);
 104
 105         val  = val      << shift;
 106         mask = 0xffff   << shift;
 107
 108         rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val);
 109
 110         return 0;
 111 }
 112
 113 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod,
 114                                         struct rsnd_dai_stream *io,
 115                                         u32 timsel)
 116 {
 117         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 118         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 119         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 120         int is_play = rsnd_io_is_play(io);
 121         int id = rsnd_mod_id(src_mod);
 122         int shift = (id % 2) ? 16 : 0;
 123         u32 mask, ws;
 124         u32 in, out;
 125
 126         rsnd_mod_confirm_src(src_mod);
 127
 128         ws = rsnd_adg_ssi_ws_timing_gen2(io);
 129
 130         in  = (is_play) ? timsel : ws;
 131         out = (is_play) ? ws     : timsel;
 132
 133         in   = in       << shift;
 134         out  = out      << shift;
 135         mask = 0xffff   << shift;
 136
 137         switch (id / 2) {
 138         case 0:
 139                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0,  mask, in);
 140                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
 141                 break;
 142         case 1:
 143                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1,  mask, in);
 144                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
 145                 break;
 146         case 2:
 147                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2,  mask, in);
 148                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
 149                 break;
 150         case 3:
 151                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3,  mask, in);
 152                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
 153                 break;
 154         case 4:
 155                 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4,  mask, in);
 156                 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
 157                 break;
 158         }
 159
 160         return 0;
 161 }
 162
 163 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *src_mod,
 164                                   struct rsnd_dai_stream *io,
 165                                   unsigned int src_rate,
 166                                   unsigned int dst_rate)
 167 {
 168         struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
 169         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 170         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 171         struct device *dev = rsnd_priv_to_dev(priv);
 172         int idx, sel, div, step, ret;
 173         u32 val, en;
 174         unsigned int min, diff;
 175         unsigned int sel_rate [] = {
 176                 clk_get_rate(adg->clk[CLKA]),   /* 0000: CLKA */
 177                 clk_get_rate(adg->clk[CLKB]),   /* 0001: CLKB */
 178                 clk_get_rate(adg->clk[CLKC]),   /* 0010: CLKC */
 179                 adg->rbga_rate_for_441khz,      /* 0011: RBGA */
 180                 adg->rbgb_rate_for_48khz,       /* 0100: RBGB */
 181         };
 182
 183         rsnd_mod_confirm_src(src_mod);
 184
 185         min = ~0;
 186         val = 0;
 187         en = 0;
 188         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
 189                 idx = 0;
 190                 step = 2;
 191
 192                 if (!sel_rate[sel])
 193                         continue;
 194
 195                 for (div = 2; div <= 98304; div += step) {
 196                         diff = abs(src_rate - sel_rate[sel] / div);
 197                         if (min > diff) {
 198                                 val = (sel << 8) | idx;
 199                                 min = diff;
 200                                 en = 1 << (sel + 1); /* fixme */
 201                         }
 202
 203                         /*
 204                          * step of 0_0000 / 0_0001 / 0_1101
 205                          * are out of order
 206                          */
 207                         if ((idx > 2) && (idx % 2))
 208                                 step *= 2;
 209                         if (idx == 0x1c) {
 210                                 div += step;
 211                                 step *= 2;
 212                         }
 213                         idx++;
 214                 }
 215         }
 216
 217         if (min == ~0) {
 218                 dev_err(dev, "no Input clock\n");
 219                 return -EIO;
 220         }
 221
 222         ret = rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
 223         if (ret < 0) {
 224                 dev_err(dev, "timsel error\n");
 225                 return ret;
 226         }
 227
 228         rsnd_mod_bset(adg_mod, DIV_EN, en, en);
 229
 230         dev_dbg(dev, "convert rate %d <-> %d\n", src_rate, dst_rate);
 231
 232         return 0;
 233 }
 234
 235 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *src_mod,
 236                                      struct rsnd_dai_stream *io)
 237 {
 238         u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
 239
 240         rsnd_mod_confirm_src(src_mod);
 241
 242         return rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
 243 }
 244
 245 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
 246 {
 247         struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
 248         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 249         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 250         int id = rsnd_mod_id(ssi_mod);
 251         int shift = (id % 4) * 8;
 252         u32 mask = 0xFF << shift;
 253
 254         rsnd_mod_confirm_ssi(ssi_mod);
 255
 256         val = val << shift;
 257
 258         /*
 259          * SSI 8 is not connected to ADG.
 260          * it works with SSI 7
 261          */
 262         if (id == 8)
 263                 return;
 264
 265         switch (id / 4) {
 266         case 0:
 267                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
 268                 break;
 269         case 1:
 270                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
 271                 break;
 272         case 2:
 273                 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
 274                 break;
 275         }
 276 }
 277
 278 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
 279 {
 280         /*
 281          * "mod" = "ssi" here.
 282          * we can get "ssi id" from mod
 283          */
 284         rsnd_adg_set_ssi_clk(mod, 0);
 285
 286         return 0;
 287 }
 288
 289 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
 290 {
 291         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
 292         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 293         struct device *dev = rsnd_priv_to_dev(priv);
 294         struct clk *clk;
 295         int i;
 296         u32 data;
 297         int sel_table[] = {
 298                 [CLKA] = 0x1,
 299                 [CLKB] = 0x2,
 300                 [CLKC] = 0x3,
 301                 [CLKI] = 0x0,
 302         };
 303
 304         dev_dbg(dev, "request clock = %d\n", rate);
 305
 306         /*
 307          * find suitable clock from
 308          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 309          */
 310         data = 0;
 311         for_each_rsnd_clk(clk, adg, i) {
 312                 if (rate == clk_get_rate(clk)) {
 313                         data = sel_table[i];
 314                         goto found_clock;
 315                 }
 316         }
 317
 318         /*
 319          * find divided clock from BRGA/BRGB
 320          */
 321         if (rate  == adg->rbga_rate_for_441khz) {
 322                 data = 0x10;
 323                 goto found_clock;
 324         }
 325
 326         if (rate == adg->rbgb_rate_for_48khz) {
 327                 data = 0x20;
 328                 goto found_clock;
 329         }
 330
 331         return -EIO;
 332
 333 found_clock:
 334
 335         /*
 336          * This "mod" = "ssi" here.
 337          * we can get "ssi id" from mod
 338          */
 339         rsnd_adg_set_ssi_clk(mod, data);
 340
 341         dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
 342                 rsnd_mod_name(mod), rsnd_mod_id(mod),
 343                 data, rate);
 344
 345         return 0;
 346 }
 347
 348 static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
 349                                struct rsnd_adg *adg)
 350 {
 351         struct device *dev = rsnd_priv_to_dev(priv);
 352         struct clk *clk;
 353         static const char * const clk_name[] = {
 354                 [CLKA]  = "clk_a",
 355                 [CLKB]  = "clk_b",
 356                 [CLKC]  = "clk_c",
 357                 [CLKI]  = "clk_i",
 358         };
 359         int i, ret;
 360
 361         for (i = 0; i < CLKMAX; i++) {
 362                 clk = devm_clk_get(dev, clk_name[i]);
 363                 adg->clk[i] = IS_ERR(clk) ? NULL : clk;
 364         }
 365
 366         for_each_rsnd_clk(clk, adg, i) {
 367                 ret = clk_prepare_enable(clk);
 368                 if (ret < 0)
 369                         dev_warn(dev, "can't use clk %d\n", i);
 370
 371                 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 372         }
 373 }
 374
 375 static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 376                                 struct rsnd_adg *adg)
 377 {
 378         struct clk *clk;
 379         struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
 380         struct device *dev = rsnd_priv_to_dev(priv);
 381         struct device_node *np = dev->of_node;
 382         u32 ckr, rbgx, rbga, rbgb;
 383         u32 rate, req_rate = 0, div;
 384         uint32_t count = 0;
 385         unsigned long req_48kHz_rate, req_441kHz_rate;
 386         int i;
 387         const char *parent_clk_name = NULL;
 388         static const char * const clkout_name[] = {
 389                 [CLKOUT]  = "audio_clkout",
 390                 [CLKOUT1] = "audio_clkout1",
 391                 [CLKOUT2] = "audio_clkout2",
 392                 [CLKOUT3] = "audio_clkout3",
 393         };
 394         int brg_table[] = {
 395                 [CLKA] = 0x0,
 396                 [CLKB] = 0x1,
 397                 [CLKC] = 0x4,
 398                 [CLKI] = 0x2,
 399         };
 400
 401         of_property_read_u32(np, "#clock-cells", &count);
 402
 403         /*
 404          * ADG supports BRRA/BRRB output only
 405          * this means all clkout0/1/2/3 will be same rate
 406          */
 407         of_property_read_u32(np, "clock-frequency", &req_rate);
 408         req_48kHz_rate = 0;
 409         req_441kHz_rate = 0;
 410         if (0 == (req_rate % 44100))
 411                 req_441kHz_rate = req_rate;
 412         if (0 == (req_rate % 48000))
 413                 req_48kHz_rate = req_rate;
 414
 415         /*
 416          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 417          * have 44.1kHz or 48kHz base clocks for now.
 418          *
 419          * SSI itself can divide parent clock by 1/1 - 1/16
 420          * see
 421          *      rsnd_adg_ssi_clk_try_start()
 422          *      rsnd_ssi_master_clk_start()
 423          */
 424         ckr = 0;
 425         rbga = 2; /* default 1/6 */
 426         rbgb = 2; /* default 1/6 */
 427         adg->rbga_rate_for_441khz       = 0;
 428         adg->rbgb_rate_for_48khz        = 0;
 429         for_each_rsnd_clk(clk, adg, i) {
 430                 rate = clk_get_rate(clk);
 431
 432                 if (0 == rate) /* not used */
 433                         continue;
 434
 435                 /* RBGA */
 436                 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
 437                         div = 6;
 438                         if (req_441kHz_rate)
 439                                 div = rate / req_441kHz_rate;
 440                         rbgx = rsnd_adg_calculate_rbgx(div);
 441                         if (BRRx_MASK(rbgx) == rbgx) {
 442                                 rbga = rbgx;
 443                                 adg->rbga_rate_for_441khz = rate / div;
 444                                 ckr |= brg_table[i] << 20;
 445                                 if (req_441kHz_rate)
 446                                         parent_clk_name = __clk_get_name(clk);
 447                         }
 448                 }
 449
 450                 /* RBGB */
 451                 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
 452                         div = 6;
 453                         if (req_48kHz_rate)
 454                                 div = rate / req_48kHz_rate;
 455                         rbgx = rsnd_adg_calculate_rbgx(div);
 456                         if (BRRx_MASK(rbgx) == rbgx) {
 457                                 rbgb = rbgx;
 458                                 adg->rbgb_rate_for_48khz = rate / div;
 459                                 ckr |= brg_table[i] << 16;
 460                                 if (req_48kHz_rate) {
 461                                         parent_clk_name = __clk_get_name(clk);
 462                                         ckr |= 0x80000000;
 463                                 }
 464                         }
 465                 }
 466         }
 467
 468         /*
 469          * ADG supports BRRA/BRRB output only.
 470          * this means all clkout0/1/2/3 will be * same rate
 471          */
 472
 473         /*
 474          * for clkout
 475          */
 476         if (!count) {
 477                 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT],
 478                                               parent_clk_name,
 479                                               (parent_clk_name) ?
 480                                               0 : CLK_IS_ROOT, req_rate);
 481                 if (!IS_ERR(clk)) {
 482                         adg->clkout[CLKOUT] = clk;
 483                         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 484                 }
 485         }
 486         /*
 487          * for clkout0/1/2/3
 488          */
 489         else {
 490                 for (i = 0; i < CLKOUTMAX; i++) {
 491                         clk = clk_register_fixed_rate(dev, clkout_name[i],
 492                                                       parent_clk_name,
 493                                                       (parent_clk_name) ?
 494                                                       0 : CLK_IS_ROOT,
 495                                                       req_rate);
 496                         if (!IS_ERR(clk)) {
 497                                 adg->onecell.clks       = adg->clkout;
 498                                 adg->onecell.clk_num    = CLKOUTMAX;
 499
 500                                 adg->clkout[i] = clk;
 501
 502                                 of_clk_add_provider(np, of_clk_src_onecell_get,
 503                                                     &adg->onecell);
 504                         }
 505                 }
 506         }
 507
 508         rsnd_mod_bset(adg_mod, SSICKR, 0x00FF0000, ckr);
 509         rsnd_mod_write(adg_mod, BRRA,  rbga);
 510         rsnd_mod_write(adg_mod, BRRB,  rbgb);
 511
 512         for_each_rsnd_clkout(clk, adg, i)
 513                 dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
 514         dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
 515                 ckr, rbga, rbgb);
 516 }
 517
 518 int rsnd_adg_probe(struct rsnd_priv *priv)
 519 {
 520         struct rsnd_adg *adg;
 521         struct device *dev = rsnd_priv_to_dev(priv);
 522
 523         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 524         if (!adg) {
 525                 dev_err(dev, "ADG allocate failed\n");
 526                 return -ENOMEM;
 527         }
 528
 529         /*
 530          * ADG is special module.
 531          * Use ADG mod without rsnd_mod_init() to make debug easy
 532          * for rsnd_write/rsnd_read
 533          */
 534         adg->mod.ops = &adg_ops;
 535         adg->mod.priv = priv;
 536
 537         rsnd_adg_get_clkin(priv, adg);
 538         rsnd_adg_get_clkout(priv, adg);
 539
 540         priv->adg = adg;
 541
 542         return 0;
 543 }
 544
 545 void rsnd_adg_remove(struct rsnd_priv *priv)
 546 {
 547         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 548         struct clk *clk;
 549         int i;
 550
 551         for_each_rsnd_clk(clk, adg, i) {
 552                 clk_disable_unprepare(clk);
 553         }
 554 }