2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/sh_clk.h>
20 struct clk
*clk
[CLKMAX
];
22 int rbga_rate_for_441khz_div_6
; /* RBGA */
23 int rbgb_rate_for_48khz_div_6
; /* RBGB */
27 #define for_each_rsnd_clk(pos, adg, i) \
30 ((pos) = adg->clk[i]); \
32 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
35 static u32
rsnd_adg_ssi_ws_timing_gen2(struct rsnd_mod
*mod
)
37 struct rsnd_priv
*priv
= rsnd_mod_to_priv(mod
);
38 int id
= rsnd_mod_id(mod
);
41 if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv
, id
))) {
56 return (0x6 + ws
) << 8;
59 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_dai
*rdai
,
61 struct rsnd_dai_stream
*io
,
64 int is_play
= rsnd_dai_is_play(rdai
, io
);
65 int id
= rsnd_mod_id(mod
);
66 int shift
= (id
% 2) ? 16 : 0;
70 ws
= rsnd_adg_ssi_ws_timing_gen2(mod
);
72 in
= (is_play
) ? timsel
: ws
;
73 out
= (is_play
) ? ws
: timsel
;
77 mask
= 0xffff << shift
;
81 rsnd_mod_bset(mod
, SRCIN_TIMSEL0
, mask
, in
);
82 rsnd_mod_bset(mod
, SRCOUT_TIMSEL0
, mask
, out
);
85 rsnd_mod_bset(mod
, SRCIN_TIMSEL1
, mask
, in
);
86 rsnd_mod_bset(mod
, SRCOUT_TIMSEL1
, mask
, out
);
89 rsnd_mod_bset(mod
, SRCIN_TIMSEL2
, mask
, in
);
90 rsnd_mod_bset(mod
, SRCOUT_TIMSEL2
, mask
, out
);
93 rsnd_mod_bset(mod
, SRCIN_TIMSEL3
, mask
, in
);
94 rsnd_mod_bset(mod
, SRCOUT_TIMSEL3
, mask
, out
);
97 rsnd_mod_bset(mod
, SRCIN_TIMSEL4
, mask
, in
);
98 rsnd_mod_bset(mod
, SRCOUT_TIMSEL4
, mask
, out
);
105 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod
*mod
,
106 struct rsnd_dai
*rdai
,
107 struct rsnd_dai_stream
*io
,
108 unsigned int src_rate
,
109 unsigned int dst_rate
)
111 struct rsnd_priv
*priv
= rsnd_mod_to_priv(mod
);
112 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
113 struct device
*dev
= rsnd_priv_to_dev(priv
);
114 int idx
, sel
, div
, step
, ret
;
116 unsigned int min
, diff
;
117 unsigned int sel_rate
[] = {
118 clk_get_rate(adg
->clk
[CLKA
]), /* 0000: CLKA */
119 clk_get_rate(adg
->clk
[CLKB
]), /* 0001: CLKB */
120 clk_get_rate(adg
->clk
[CLKC
]), /* 0010: CLKC */
121 adg
->rbga_rate_for_441khz_div_6
,/* 0011: RBGA */
122 adg
->rbgb_rate_for_48khz_div_6
, /* 0100: RBGB */
128 for (sel
= 0; sel
< ARRAY_SIZE(sel_rate
); sel
++) {
135 for (div
= 2; div
<= 98304; div
+= step
) {
136 diff
= abs(src_rate
- sel_rate
[sel
] / div
);
138 val
= (sel
<< 8) | idx
;
140 en
= 1 << (sel
+ 1); /* fixme */
144 * step of 0_0000 / 0_0001 / 0_1101
147 if ((idx
> 2) && (idx
% 2))
158 dev_err(dev
, "no Input clock\n");
162 ret
= rsnd_adg_set_src_timsel_gen2(rdai
, mod
, io
, val
);
164 dev_err(dev
, "timsel error\n");
168 rsnd_mod_bset(mod
, DIV_EN
, en
, en
);
173 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod
*mod
,
174 struct rsnd_dai
*rdai
,
175 struct rsnd_dai_stream
*io
)
177 u32 val
= rsnd_adg_ssi_ws_timing_gen2(mod
);
179 return rsnd_adg_set_src_timsel_gen2(rdai
, mod
, io
, val
);
182 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv
*priv
,
183 struct rsnd_mod
*mod
,
184 unsigned int src_rate
,
185 unsigned int dst_rate
)
187 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
188 struct device
*dev
= rsnd_priv_to_dev(priv
);
189 int idx
, sel
, div
, shift
;
191 int id
= rsnd_mod_id(mod
);
192 unsigned int sel_rate
[] = {
193 clk_get_rate(adg
->clk
[CLKA
]), /* 000: CLKA */
194 clk_get_rate(adg
->clk
[CLKB
]), /* 001: CLKB */
195 clk_get_rate(adg
->clk
[CLKC
]), /* 010: CLKC */
196 0, /* 011: MLBCLK (not used) */
197 adg
->rbga_rate_for_441khz_div_6
,/* 100: RBGA */
198 adg
->rbgb_rate_for_48khz_div_6
, /* 101: RBGB */
201 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
202 for (sel
= 0; sel
< ARRAY_SIZE(sel_rate
); sel
++) {
203 for (div
= 128, idx
= 0;
206 if (src_rate
== sel_rate
[sel
] / div
) {
207 val
= (idx
<< 4) | sel
;
212 dev_err(dev
, "can't find convert src clk\n");
216 shift
= (id
% 4) * 8;
217 mask
= 0xFF << shift
;
220 dev_dbg(dev
, "adg convert src clk = %02x\n", val
);
224 rsnd_mod_bset(mod
, AUDIO_CLK_SEL3
, mask
, val
);
227 rsnd_mod_bset(mod
, AUDIO_CLK_SEL4
, mask
, val
);
230 rsnd_mod_bset(mod
, AUDIO_CLK_SEL5
, mask
, val
);
235 * Gen1 doesn't need dst_rate settings,
236 * since it uses SSI WS pin.
237 * see also rsnd_src_set_route_if_gen1()
243 static void rsnd_adg_set_ssi_clk(struct rsnd_mod
*mod
, u32 val
)
245 int id
= rsnd_mod_id(mod
);
246 int shift
= (id
% 4) * 8;
247 u32 mask
= 0xFF << shift
;
252 * SSI 8 is not connected to ADG.
253 * it works with SSI 7
260 rsnd_mod_bset(mod
, AUDIO_CLK_SEL0
, mask
, val
);
263 rsnd_mod_bset(mod
, AUDIO_CLK_SEL1
, mask
, val
);
266 rsnd_mod_bset(mod
, AUDIO_CLK_SEL2
, mask
, val
);
271 int rsnd_adg_ssi_clk_stop(struct rsnd_mod
*mod
)
274 * "mod" = "ssi" here.
275 * we can get "ssi id" from mod
277 rsnd_adg_set_ssi_clk(mod
, 0);
282 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod
*mod
, unsigned int rate
)
284 struct rsnd_priv
*priv
= rsnd_mod_to_priv(mod
);
285 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
286 struct device
*dev
= rsnd_priv_to_dev(priv
);
297 dev_dbg(dev
, "request clock = %d\n", rate
);
300 * find suitable clock from
301 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
304 for_each_rsnd_clk(clk
, adg
, i
) {
305 if (rate
== clk_get_rate(clk
)) {
312 * find 1/6 clock from BRGA/BRGB
314 if (rate
== adg
->rbga_rate_for_441khz_div_6
) {
319 if (rate
== adg
->rbgb_rate_for_48khz_div_6
) {
328 /* see rsnd_adg_ssi_clk_init() */
329 rsnd_mod_bset(mod
, SSICKR
, 0x00FF0000, adg
->ckr
);
330 rsnd_mod_write(mod
, BRRA
, 0x00000002); /* 1/6 */
331 rsnd_mod_write(mod
, BRRB
, 0x00000002); /* 1/6 */
334 * This "mod" = "ssi" here.
335 * we can get "ssi id" from mod
337 rsnd_adg_set_ssi_clk(mod
, data
);
339 dev_dbg(dev
, "ADG: ssi%d selects clk%d = %d",
340 rsnd_mod_id(mod
), i
, rate
);
345 static void rsnd_adg_ssi_clk_init(struct rsnd_priv
*priv
, struct rsnd_adg
*adg
)
359 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
360 * have 44.1kHz or 48kHz base clocks for now.
362 * SSI itself can divide parent clock by 1/1 - 1/16
363 * So, BRGA outputs 44.1kHz base parent clock 1/32,
364 * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
366 * rsnd_adg_ssi_clk_try_start()
369 adg
->rbga_rate_for_441khz_div_6
= 0;
370 adg
->rbgb_rate_for_48khz_div_6
= 0;
371 for_each_rsnd_clk(clk
, adg
, i
) {
372 rate
= clk_get_rate(clk
);
374 if (0 == rate
) /* not used */
378 if (!adg
->rbga_rate_for_441khz_div_6
&& (0 == rate
% 44100)) {
379 adg
->rbga_rate_for_441khz_div_6
= rate
/ 6;
380 ckr
|= brg_table
[i
] << 20;
384 if (!adg
->rbgb_rate_for_48khz_div_6
&& (0 == rate
% 48000)) {
385 adg
->rbgb_rate_for_48khz_div_6
= rate
/ 6;
386 ckr
|= brg_table
[i
] << 16;
393 int rsnd_adg_probe(struct platform_device
*pdev
,
394 struct rcar_snd_info
*info
,
395 struct rsnd_priv
*priv
)
397 struct rsnd_adg
*adg
;
398 struct device
*dev
= rsnd_priv_to_dev(priv
);
399 struct clk
*clk
, *clk_orig
;
401 bool use_old_style
= false;
403 adg
= devm_kzalloc(dev
, sizeof(*adg
), GFP_KERNEL
);
405 dev_err(dev
, "ADG allocate failed\n");
409 clk_orig
= clk_get(dev
, NULL
);
410 adg
->clk
[CLKA
] = clk_get(dev
, "clk_a");
411 adg
->clk
[CLKB
] = clk_get(dev
, "clk_b");
412 adg
->clk
[CLKC
] = clk_get(dev
, "clk_c");
413 adg
->clk
[CLKI
] = clk_get(dev
, "clk_i");
416 * It request device dependent audio clock.
417 * But above all clks will indicate rsnd module clock
418 * if platform doesn't it
420 for_each_rsnd_clk(clk
, adg
, i
) {
421 if (clk_orig
== clk
) {
423 "doesn't have device dependent clock, use independent clock\n");
424 use_old_style
= true;
431 * these exist in order to keep compatible with
432 * platform which has device independent audio clock,
433 * but will be removed soon
436 adg
->clk
[CLKA
] = clk_get(NULL
, "audio_clk_a");
437 adg
->clk
[CLKB
] = clk_get(NULL
, "audio_clk_b");
438 adg
->clk
[CLKC
] = clk_get(NULL
, "audio_clk_c");
439 adg
->clk
[CLKI
] = clk_get(NULL
, "audio_clk_internal");
442 for_each_rsnd_clk(clk
, adg
, i
) {
444 dev_err(dev
, "Audio clock failed\n");
449 rsnd_adg_ssi_clk_init(priv
, adg
);
453 dev_dbg(dev
, "adg probed\n");
458 void rsnd_adg_remove(struct platform_device
*pdev
,
459 struct rsnd_priv
*priv
)
461 struct rsnd_adg
*adg
= priv
->adg
;
465 for_each_rsnd_clk(clk
, adg
, i
)