2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk-provider.h>
25 #define BRRx_MASK(x) (0x3FF & x)
27 static struct rsnd_mod_ops adg_ops
= {
32 struct clk
*clk
[CLKMAX
];
33 struct clk
*clkout
[CLKOUTMAX
];
34 struct clk_onecell_data onecell
;
37 int rbga_rate_for_441khz
; /* RBGA */
38 int rbgb_rate_for_48khz
; /* RBGB */
41 #define for_each_rsnd_clk(pos, adg, i) \
44 ((pos) = adg->clk[i]); \
46 #define for_each_rsnd_clkout(pos, adg, i) \
49 ((pos) = adg->clkout[i]); \
51 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
53 static u32
rsnd_adg_calculate_rbgx(unsigned long div
)
60 for (i
= 3; i
>= 0; i
--) {
62 if (0 == (div
% ratio
))
63 return (u32
)((i
<< 8) | ((div
/ ratio
) - 1));
69 static u32
rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream
*io
)
71 struct rsnd_mod
*ssi_mod
= rsnd_io_to_mod_ssi(io
);
72 int id
= rsnd_mod_id(ssi_mod
);
75 if (rsnd_ssi_is_pin_sharing(io
)) {
90 return (0x6 + ws
) << 8;
93 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv
*priv
,
94 struct rsnd_dai_stream
*io
,
95 unsigned int target_rate
,
96 unsigned int *target_val
,
97 unsigned int *target_en
)
99 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
100 struct device
*dev
= rsnd_priv_to_dev(priv
);
101 int idx
, sel
, div
, step
;
102 unsigned int val
, en
;
103 unsigned int min
, diff
;
104 unsigned int sel_rate
[] = {
105 clk_get_rate(adg
->clk
[CLKA
]), /* 0000: CLKA */
106 clk_get_rate(adg
->clk
[CLKB
]), /* 0001: CLKB */
107 clk_get_rate(adg
->clk
[CLKC
]), /* 0010: CLKC */
108 adg
->rbga_rate_for_441khz
, /* 0011: RBGA */
109 adg
->rbgb_rate_for_48khz
, /* 0100: RBGB */
115 for (sel
= 0; sel
< ARRAY_SIZE(sel_rate
); sel
++) {
122 for (div
= 2; div
<= 98304; div
+= step
) {
123 diff
= abs(target_rate
- sel_rate
[sel
] / div
);
125 val
= (sel
<< 8) | idx
;
127 en
= 1 << (sel
+ 1); /* fixme */
131 * step of 0_0000 / 0_0001 / 0_1101
134 if ((idx
> 2) && (idx
% 2))
145 dev_err(dev
, "no Input clock\n");
154 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv
*priv
,
155 struct rsnd_dai_stream
*io
,
156 unsigned int in_rate
,
157 unsigned int out_rate
,
158 u32
*in
, u32
*out
, u32
*en
)
160 struct snd_pcm_runtime
*runtime
= rsnd_io_to_runtime(io
);
161 unsigned int target_rate
;
167 /* default = SSI WS */
169 _out
= rsnd_adg_ssi_ws_timing_gen2(io
);
174 if (runtime
->rate
!= in_rate
) {
175 target_rate
= out_rate
;
177 } else if (runtime
->rate
!= out_rate
) {
178 target_rate
= in_rate
;
183 __rsnd_adg_get_timesel_ratio(priv
, io
,
195 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod
*cmd_mod
,
196 struct rsnd_dai_stream
*io
)
198 struct rsnd_priv
*priv
= rsnd_mod_to_priv(cmd_mod
);
199 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
200 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
201 int id
= rsnd_mod_id(cmd_mod
);
202 int shift
= (id
% 2) ? 16 : 0;
205 rsnd_adg_get_timesel_ratio(priv
, io
,
206 rsnd_src_get_in_rate(priv
, io
),
207 rsnd_src_get_out_rate(priv
, io
),
211 mask
= 0xffff << shift
;
213 rsnd_mod_bset(adg_mod
, CMDOUT_TIMSEL
, mask
, val
);
218 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod
*src_mod
,
219 struct rsnd_dai_stream
*io
,
220 unsigned int in_rate
,
221 unsigned int out_rate
)
223 struct rsnd_priv
*priv
= rsnd_mod_to_priv(src_mod
);
224 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
225 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
228 int id
= rsnd_mod_id(src_mod
);
229 int shift
= (id
% 2) ? 16 : 0;
231 rsnd_mod_confirm_src(src_mod
);
233 rsnd_adg_get_timesel_ratio(priv
, io
,
239 mask
= 0xffff << shift
;
243 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL0
, mask
, in
);
244 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL0
, mask
, out
);
247 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL1
, mask
, in
);
248 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL1
, mask
, out
);
251 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL2
, mask
, in
);
252 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL2
, mask
, out
);
255 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL3
, mask
, in
);
256 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL3
, mask
, out
);
259 rsnd_mod_bset(adg_mod
, SRCIN_TIMSEL4
, mask
, in
);
260 rsnd_mod_bset(adg_mod
, SRCOUT_TIMSEL4
, mask
, out
);
265 rsnd_mod_bset(adg_mod
, DIV_EN
, en
, en
);
270 static void rsnd_adg_set_ssi_clk(struct rsnd_mod
*ssi_mod
, u32 val
)
272 struct rsnd_priv
*priv
= rsnd_mod_to_priv(ssi_mod
);
273 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
274 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
275 int id
= rsnd_mod_id(ssi_mod
);
276 int shift
= (id
% 4) * 8;
277 u32 mask
= 0xFF << shift
;
279 rsnd_mod_confirm_ssi(ssi_mod
);
284 * SSI 8 is not connected to ADG.
285 * it works with SSI 7
292 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL0
, mask
, val
);
295 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL1
, mask
, val
);
298 rsnd_mod_bset(adg_mod
, AUDIO_CLK_SEL2
, mask
, val
);
303 int rsnd_adg_ssi_clk_stop(struct rsnd_mod
*ssi_mod
)
305 rsnd_adg_set_ssi_clk(ssi_mod
, 0);
310 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod
*ssi_mod
, unsigned int rate
)
312 struct rsnd_priv
*priv
= rsnd_mod_to_priv(ssi_mod
);
313 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
314 struct device
*dev
= rsnd_priv_to_dev(priv
);
325 dev_dbg(dev
, "request clock = %d\n", rate
);
328 * find suitable clock from
329 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
332 for_each_rsnd_clk(clk
, adg
, i
) {
333 if (rate
== clk_get_rate(clk
)) {
340 * find divided clock from BRGA/BRGB
342 if (rate
== adg
->rbga_rate_for_441khz
) {
347 if (rate
== adg
->rbgb_rate_for_48khz
) {
356 rsnd_adg_set_ssi_clk(ssi_mod
, data
);
358 dev_dbg(dev
, "ADG: %s[%d] selects 0x%x for %d\n",
359 rsnd_mod_name(ssi_mod
), rsnd_mod_id(ssi_mod
),
365 static void rsnd_adg_get_clkin(struct rsnd_priv
*priv
,
366 struct rsnd_adg
*adg
)
368 struct device
*dev
= rsnd_priv_to_dev(priv
);
370 static const char * const clk_name
[] = {
378 for (i
= 0; i
< CLKMAX
; i
++) {
379 clk
= devm_clk_get(dev
, clk_name
[i
]);
380 adg
->clk
[i
] = IS_ERR(clk
) ? NULL
: clk
;
383 for_each_rsnd_clk(clk
, adg
, i
) {
384 ret
= clk_prepare_enable(clk
);
386 dev_warn(dev
, "can't use clk %d\n", i
);
388 dev_dbg(dev
, "clk %d : %p : %ld\n", i
, clk
, clk_get_rate(clk
));
392 static void rsnd_adg_get_clkout(struct rsnd_priv
*priv
,
393 struct rsnd_adg
*adg
)
396 struct rsnd_mod
*adg_mod
= rsnd_mod_get(adg
);
397 struct device
*dev
= rsnd_priv_to_dev(priv
);
398 struct device_node
*np
= dev
->of_node
;
399 u32 ckr
, rbgx
, rbga
, rbgb
;
400 u32 rate
, req_rate
= 0, div
;
402 unsigned long req_48kHz_rate
, req_441kHz_rate
;
404 const char *parent_clk_name
= NULL
;
405 static const char * const clkout_name
[] = {
406 [CLKOUT
] = "audio_clkout",
407 [CLKOUT1
] = "audio_clkout1",
408 [CLKOUT2
] = "audio_clkout2",
409 [CLKOUT3
] = "audio_clkout3",
418 of_property_read_u32(np
, "#clock-cells", &count
);
421 * ADG supports BRRA/BRRB output only
422 * this means all clkout0/1/2/3 will be same rate
424 of_property_read_u32(np
, "clock-frequency", &req_rate
);
427 if (0 == (req_rate
% 44100))
428 req_441kHz_rate
= req_rate
;
429 if (0 == (req_rate
% 48000))
430 req_48kHz_rate
= req_rate
;
433 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
434 * have 44.1kHz or 48kHz base clocks for now.
436 * SSI itself can divide parent clock by 1/1 - 1/16
438 * rsnd_adg_ssi_clk_try_start()
439 * rsnd_ssi_master_clk_start()
442 rbga
= 2; /* default 1/6 */
443 rbgb
= 2; /* default 1/6 */
444 adg
->rbga_rate_for_441khz
= 0;
445 adg
->rbgb_rate_for_48khz
= 0;
446 for_each_rsnd_clk(clk
, adg
, i
) {
447 rate
= clk_get_rate(clk
);
449 if (0 == rate
) /* not used */
453 if (!adg
->rbga_rate_for_441khz
&& (0 == rate
% 44100)) {
456 div
= rate
/ req_441kHz_rate
;
457 rbgx
= rsnd_adg_calculate_rbgx(div
);
458 if (BRRx_MASK(rbgx
) == rbgx
) {
460 adg
->rbga_rate_for_441khz
= rate
/ div
;
461 ckr
|= brg_table
[i
] << 20;
463 parent_clk_name
= __clk_get_name(clk
);
468 if (!adg
->rbgb_rate_for_48khz
&& (0 == rate
% 48000)) {
471 div
= rate
/ req_48kHz_rate
;
472 rbgx
= rsnd_adg_calculate_rbgx(div
);
473 if (BRRx_MASK(rbgx
) == rbgx
) {
475 adg
->rbgb_rate_for_48khz
= rate
/ div
;
476 ckr
|= brg_table
[i
] << 16;
477 if (req_48kHz_rate
) {
478 parent_clk_name
= __clk_get_name(clk
);
486 * ADG supports BRRA/BRRB output only.
487 * this means all clkout0/1/2/3 will be * same rate
494 clk
= clk_register_fixed_rate(dev
, clkout_name
[CLKOUT
],
497 0 : CLK_IS_ROOT
, req_rate
);
499 adg
->clkout
[CLKOUT
] = clk
;
500 of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
507 for (i
= 0; i
< CLKOUTMAX
; i
++) {
508 clk
= clk_register_fixed_rate(dev
, clkout_name
[i
],
514 adg
->onecell
.clks
= adg
->clkout
;
515 adg
->onecell
.clk_num
= CLKOUTMAX
;
517 adg
->clkout
[i
] = clk
;
519 of_clk_add_provider(np
, of_clk_src_onecell_get
,
525 rsnd_mod_bset(adg_mod
, SSICKR
, 0x00FF0000, ckr
);
526 rsnd_mod_write(adg_mod
, BRRA
, rbga
);
527 rsnd_mod_write(adg_mod
, BRRB
, rbgb
);
529 for_each_rsnd_clkout(clk
, adg
, i
)
530 dev_dbg(dev
, "clkout %d : %p : %ld\n", i
, clk
, clk_get_rate(clk
));
531 dev_dbg(dev
, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
535 int rsnd_adg_probe(struct rsnd_priv
*priv
)
537 struct rsnd_adg
*adg
;
538 struct device
*dev
= rsnd_priv_to_dev(priv
);
540 adg
= devm_kzalloc(dev
, sizeof(*adg
), GFP_KERNEL
);
542 dev_err(dev
, "ADG allocate failed\n");
546 rsnd_mod_init(priv
, &adg
->mod
, &adg_ops
,
549 rsnd_adg_get_clkin(priv
, adg
);
550 rsnd_adg_get_clkout(priv
, adg
);
557 void rsnd_adg_remove(struct rsnd_priv
*priv
)
559 struct rsnd_adg
*adg
= rsnd_priv_to_adg(priv
);
563 for_each_rsnd_clk(clk
, adg
, i
) {
564 clk_disable_unprepare(clk
);
This page took 0.077102 seconds and 6 git commands to generate.