sound/soc/sirf/sirf-usp.c

   1 /*
   2  * SiRF USP in I2S/DSP mode
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8 #include <linux/module.h>
   9 #include <linux/io.h>
  10 #include <linux/of.h>
  11 #include <linux/clk.h>
  12 #include <linux/pm_runtime.h>
  13 #include <sound/soc.h>
  14 #include <sound/pcm_params.h>
  15 #include <sound/dmaengine_pcm.h>
  16
  17 #include "sirf-usp.h"
  18
  19 struct sirf_usp {
  20         struct regmap *regmap;
  21         struct clk *clk;
  22         u32 mode1_reg;
  23         u32 mode2_reg;
  24         int daifmt_format;
  25         struct snd_dmaengine_dai_dma_data playback_dma_data;
  26         struct snd_dmaengine_dai_dma_data capture_dma_data;
  27 };
  28
  29 static void sirf_usp_tx_enable(struct sirf_usp *usp)
  30 {
  31         regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
  32                 USP_TX_FIFO_RESET, USP_TX_FIFO_RESET);
  33         regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
  34
  35         regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
  36                 USP_TX_FIFO_START, USP_TX_FIFO_START);
  37
  38         regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
  39                 USP_TX_ENA, USP_TX_ENA);
  40 }
  41
  42 static void sirf_usp_tx_disable(struct sirf_usp *usp)
  43 {
  44         regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
  45                 USP_TX_ENA, ~USP_TX_ENA);
  46         /* FIFO stop */
  47         regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
  48 }
  49
  50 static void sirf_usp_rx_enable(struct sirf_usp *usp)
  51 {
  52         regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
  53                 USP_RX_FIFO_RESET, USP_RX_FIFO_RESET);
  54         regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
  55
  56         regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
  57                 USP_RX_FIFO_START, USP_RX_FIFO_START);
  58
  59         regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
  60                 USP_RX_ENA, USP_RX_ENA);
  61 }
  62
  63 static void sirf_usp_rx_disable(struct sirf_usp *usp)
  64 {
  65         regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
  66                 USP_RX_ENA, ~USP_RX_ENA);
  67         /* FIFO stop */
  68         regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
  69 }
  70
  71 static int sirf_usp_pcm_dai_probe(struct snd_soc_dai *dai)
  72 {
  73         struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
  74         snd_soc_dai_init_dma_data(dai, &usp->playback_dma_data,
  75                         &usp->capture_dma_data);
  76         return 0;
  77 }
  78
  79 static int sirf_usp_pcm_set_dai_fmt(struct snd_soc_dai *dai,
  80                 unsigned int fmt)
  81 {
  82         struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
  83
  84         /* set master/slave audio interface */
  85         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  86         case SND_SOC_DAIFMT_CBM_CFM:
  87                 break;
  88         default:
  89                 dev_err(dai->dev, "Only CBM and CFM supported\n");
  90                 return -EINVAL;
  91         }
  92
  93         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  94         case SND_SOC_DAIFMT_I2S:
  95         case SND_SOC_DAIFMT_DSP_A:
  96                 usp->daifmt_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  97                 break;
  98         default:
  99                 dev_err(dai->dev, "Only I2S and DSP_A format supported\n");
 100                 return -EINVAL;
 101         }
 102
 103         return 0;
 104 }
 105
 106 static void sirf_usp_i2s_init(struct sirf_usp *usp)
 107 {
 108         /* Configure RISC mode */
 109         regmap_update_bits(usp->regmap, USP_RISC_DSP_MODE,
 110                 USP_RISC_DSP_SEL, ~USP_RISC_DSP_SEL);
 111
 112         /*
 113          * Configure DMA IO Length register
 114          * Set no limit, USP can receive data continuously until it is diabled
 115          */
 116         regmap_write(usp->regmap, USP_TX_DMA_IO_LEN, 0);
 117         regmap_write(usp->regmap, USP_RX_DMA_IO_LEN, 0);
 118
 119         /* Configure Mode2 register */
 120         regmap_write(usp->regmap, USP_MODE2, (1 << USP_RXD_DELAY_LEN_OFFSET) |
 121                 (0 << USP_TXD_DELAY_LEN_OFFSET) |
 122                 USP_TFS_CLK_SLAVE_MODE | USP_RFS_CLK_SLAVE_MODE);
 123
 124         /* Configure Mode1 register */
 125         regmap_write(usp->regmap, USP_MODE1,
 126                 USP_SYNC_MODE | USP_EN | USP_TXD_ACT_EDGE_FALLING |
 127                 USP_RFS_ACT_LEVEL_LOGIC1 | USP_TFS_ACT_LEVEL_LOGIC1 |
 128                 USP_TX_UFLOW_REPEAT_ZERO | USP_CLOCK_MODE_SLAVE);
 129
 130         /* Configure RX DMA IO Control register */
 131         regmap_write(usp->regmap, USP_RX_DMA_IO_CTRL, 0);
 132
 133         /* Congiure RX FIFO Control register */
 134         regmap_write(usp->regmap, USP_RX_FIFO_CTRL,
 135                 (USP_RX_FIFO_THRESHOLD << USP_RX_FIFO_THD_OFFSET) |
 136                 (USP_TX_RX_FIFO_WIDTH_DWORD << USP_RX_FIFO_WIDTH_OFFSET));
 137
 138         /* Congiure RX FIFO Level Check register */
 139         regmap_write(usp->regmap, USP_RX_FIFO_LEVEL_CHK,
 140                 RX_FIFO_SC(0x04) | RX_FIFO_LC(0x0E) | RX_FIFO_HC(0x1B));
 141
 142         /* Configure TX DMA IO Control register*/
 143         regmap_write(usp->regmap, USP_TX_DMA_IO_CTRL, 0);
 144
 145         /* Configure TX FIFO Control register */
 146         regmap_write(usp->regmap, USP_TX_FIFO_CTRL,
 147                 (USP_TX_FIFO_THRESHOLD << USP_TX_FIFO_THD_OFFSET) |
 148                 (USP_TX_RX_FIFO_WIDTH_DWORD << USP_TX_FIFO_WIDTH_OFFSET));
 149         /* Congiure TX FIFO Level Check register */
 150         regmap_write(usp->regmap, USP_TX_FIFO_LEVEL_CHK,
 151                 TX_FIFO_SC(0x1B) | TX_FIFO_LC(0x0E) | TX_FIFO_HC(0x04));
 152 }
 153
 154 static int sirf_usp_pcm_hw_params(struct snd_pcm_substream *substream,
 155                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 156 {
 157         struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
 158         u32 data_len, frame_len, shifter_len;
 159
 160         switch (params_format(params)) {
 161         case SNDRV_PCM_FORMAT_S16_LE:
 162                 data_len = 16;
 163                 frame_len = 16;
 164                 break;
 165         case SNDRV_PCM_FORMAT_S24_LE:
 166                 data_len = 24;
 167                 frame_len = 32;
 168                 break;
 169         case SNDRV_PCM_FORMAT_S24_3LE:
 170                 data_len = 24;
 171                 frame_len = 24;
 172                 break;
 173         default:
 174                 dev_err(dai->dev, "Format unsupported\n");
 175                 return -EINVAL;
 176         }
 177
 178         shifter_len = data_len;
 179
 180         switch (usp->daifmt_format) {
 181         case SND_SOC_DAIFMT_I2S:
 182                 regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
 183                         USP_I2S_SYNC_CHG, USP_I2S_SYNC_CHG);
 184                 break;
 185         case SND_SOC_DAIFMT_DSP_A:
 186                 regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
 187                         USP_I2S_SYNC_CHG, 0);
 188                 frame_len = data_len * params_channels(params);
 189                 data_len = frame_len;
 190                 break;
 191         default:
 192                 dev_err(dai->dev, "Only support I2S and DSP_A mode\n");
 193                 return -EINVAL;
 194         }
 195
 196         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 197                 regmap_update_bits(usp->regmap, USP_TX_FRAME_CTRL,
 198                         USP_TXC_DATA_LEN_MASK | USP_TXC_FRAME_LEN_MASK
 199                         | USP_TXC_SHIFTER_LEN_MASK | USP_TXC_SLAVE_CLK_SAMPLE,
 200                         ((data_len - 1) << USP_TXC_DATA_LEN_OFFSET)
 201                         | ((frame_len - 1) << USP_TXC_FRAME_LEN_OFFSET)
 202                         | ((shifter_len - 1) << USP_TXC_SHIFTER_LEN_OFFSET)
 203                         | USP_TXC_SLAVE_CLK_SAMPLE);
 204         else
 205                 regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
 206                         USP_RXC_DATA_LEN_MASK | USP_RXC_FRAME_LEN_MASK
 207                         | USP_RXC_SHIFTER_LEN_MASK | USP_SINGLE_SYNC_MODE,
 208                         ((data_len - 1) << USP_RXC_DATA_LEN_OFFSET)
 209                         | ((frame_len - 1) << USP_RXC_FRAME_LEN_OFFSET)
 210                         | ((shifter_len - 1) << USP_RXC_SHIFTER_LEN_OFFSET)
 211                         | USP_SINGLE_SYNC_MODE);
 212
 213         return 0;
 214 }
 215
 216 static int sirf_usp_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 217                                 struct snd_soc_dai *dai)
 218 {
 219         struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
 220
 221         switch (cmd) {
 222         case SNDRV_PCM_TRIGGER_START:
 223         case SNDRV_PCM_TRIGGER_RESUME:
 224         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 225                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 226                         sirf_usp_tx_enable(usp);
 227                 else
 228                         sirf_usp_rx_enable(usp);
 229                 break;
 230         case SNDRV_PCM_TRIGGER_STOP:
 231         case SNDRV_PCM_TRIGGER_SUSPEND:
 232         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 233                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 234                         sirf_usp_tx_disable(usp);
 235                 else
 236                         sirf_usp_rx_disable(usp);
 237                 break;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static const struct snd_soc_dai_ops sirf_usp_pcm_dai_ops = {
 244         .trigger = sirf_usp_pcm_trigger,
 245         .set_fmt = sirf_usp_pcm_set_dai_fmt,
 246         .hw_params = sirf_usp_pcm_hw_params,
 247 };
 248
 249 static struct snd_soc_dai_driver sirf_usp_pcm_dai = {
 250         .probe = sirf_usp_pcm_dai_probe,
 251         .name = "sirf-usp-pcm",
 252         .id = 0,
 253         .playback = {
 254                 .stream_name = "SiRF USP PCM Playback",
 255                 .channels_min = 1,
 256                 .channels_max = 2,
 257                 .rates = SNDRV_PCM_RATE_8000_192000,
 258                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 259                         SNDRV_PCM_FMTBIT_S24_3LE,
 260         },
 261         .capture = {
 262                 .stream_name = "SiRF USP PCM Capture",
 263                 .channels_min = 1,
 264                 .channels_max = 2,
 265                 .rates = SNDRV_PCM_RATE_8000_192000,
 266                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 267                         SNDRV_PCM_FMTBIT_S24_3LE,
 268         },
 269         .ops = &sirf_usp_pcm_dai_ops,
 270 };
 271
 272 static int sirf_usp_pcm_runtime_suspend(struct device *dev)
 273 {
 274         struct sirf_usp *usp = dev_get_drvdata(dev);
 275         clk_disable_unprepare(usp->clk);
 276         return 0;
 277 }
 278
 279 static int sirf_usp_pcm_runtime_resume(struct device *dev)
 280 {
 281         struct sirf_usp *usp = dev_get_drvdata(dev);
 282         int ret;
 283         ret = clk_prepare_enable(usp->clk);
 284         if (ret) {
 285                 dev_err(dev, "clk_enable failed: %d\n", ret);
 286                 return ret;
 287         }
 288         sirf_usp_i2s_init(usp);
 289         return 0;
 290 }
 291
 292 #ifdef CONFIG_PM_SLEEP
 293 static int sirf_usp_pcm_suspend(struct device *dev)
 294 {
 295         struct sirf_usp *usp = dev_get_drvdata(dev);
 296
 297         if (!pm_runtime_status_suspended(dev)) {
 298                 regmap_read(usp->regmap, USP_MODE1, &usp->mode1_reg);
 299                 regmap_read(usp->regmap, USP_MODE2, &usp->mode2_reg);
 300                 sirf_usp_pcm_runtime_suspend(dev);
 301         }
 302         return 0;
 303 }
 304
 305 static int sirf_usp_pcm_resume(struct device *dev)
 306 {
 307         struct sirf_usp *usp = dev_get_drvdata(dev);
 308         int ret;
 309
 310         if (!pm_runtime_status_suspended(dev)) {
 311                 ret = sirf_usp_pcm_runtime_resume(dev);
 312                 if (ret)
 313                         return ret;
 314                 regmap_write(usp->regmap, USP_MODE1, usp->mode1_reg);
 315                 regmap_write(usp->regmap, USP_MODE2, usp->mode2_reg);
 316         }
 317         return 0;
 318 }
 319 #endif
 320
 321 static const struct snd_soc_component_driver sirf_usp_component = {
 322         .name           = "sirf-usp",
 323 };
 324
 325 static const struct regmap_config sirf_usp_regmap_config = {
 326         .reg_bits = 32,
 327         .reg_stride = 4,
 328         .val_bits = 32,
 329         .max_register = USP_RX_FIFO_DATA,
 330         .cache_type = REGCACHE_NONE,
 331 };
 332
 333 static int sirf_usp_pcm_probe(struct platform_device *pdev)
 334 {
 335         int ret;
 336         struct sirf_usp *usp;
 337         void __iomem *base;
 338         struct resource *mem_res;
 339
 340         usp = devm_kzalloc(&pdev->dev, sizeof(struct sirf_usp),
 341                         GFP_KERNEL);
 342         if (!usp)
 343                 return -ENOMEM;
 344
 345         platform_set_drvdata(pdev, usp);
 346
 347         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 348         base = devm_ioremap(&pdev->dev, mem_res->start,
 349                 resource_size(mem_res));
 350         if (base == NULL)
 351                 return -ENOMEM;
 352         usp->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 353                                             &sirf_usp_regmap_config);
 354         if (IS_ERR(usp->regmap))
 355                 return PTR_ERR(usp->regmap);
 356
 357         usp->clk = devm_clk_get(&pdev->dev, NULL);
 358         if (IS_ERR(usp->clk)) {
 359                 dev_err(&pdev->dev, "Get clock failed.\n");
 360                 return PTR_ERR(usp->clk);
 361         }
 362
 363         pm_runtime_enable(&pdev->dev);
 364         if (!pm_runtime_enabled(&pdev->dev)) {
 365                 ret = sirf_usp_pcm_runtime_resume(&pdev->dev);
 366                 if (ret)
 367                         return ret;
 368         }
 369
 370         ret = devm_snd_soc_register_component(&pdev->dev, &sirf_usp_component,
 371                 &sirf_usp_pcm_dai, 1);
 372         if (ret) {
 373                 dev_err(&pdev->dev, "Register Audio SoC dai failed.\n");
 374                 return ret;
 375         }
 376         return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 377 }
 378
 379 static int sirf_usp_pcm_remove(struct platform_device *pdev)
 380 {
 381         if (!pm_runtime_enabled(&pdev->dev))
 382                 sirf_usp_pcm_runtime_suspend(&pdev->dev);
 383         else
 384                 pm_runtime_disable(&pdev->dev);
 385         return 0;
 386 }
 387
 388 static const struct of_device_id sirf_usp_pcm_of_match[] = {
 389         { .compatible = "sirf,prima2-usp-pcm", },
 390         {}
 391 };
 392 MODULE_DEVICE_TABLE(of, sirf_usp_pcm_of_match);
 393
 394 static const struct dev_pm_ops sirf_usp_pcm_pm_ops = {
 395         SET_RUNTIME_PM_OPS(sirf_usp_pcm_runtime_suspend,
 396                 sirf_usp_pcm_runtime_resume, NULL)
 397         SET_SYSTEM_SLEEP_PM_OPS(sirf_usp_pcm_suspend, sirf_usp_pcm_resume)
 398 };
 399
 400 static struct platform_driver sirf_usp_pcm_driver = {
 401         .driver = {
 402                 .name = "sirf-usp-pcm",
 403                 .owner = THIS_MODULE,
 404                 .of_match_table = sirf_usp_pcm_of_match,
 405                 .pm = &sirf_usp_pcm_pm_ops,
 406         },
 407         .probe = sirf_usp_pcm_probe,
 408         .remove = sirf_usp_pcm_remove,
 409 };
 410
 411 module_platform_driver(sirf_usp_pcm_driver);
 412
 413 MODULE_DESCRIPTION("SiRF SoC USP PCM bus driver");
 414 MODULE_AUTHOR("RongJun Ying <Rongjun.Ying@csr.com>");
 415 MODULE_LICENSE("GPL v2");