2 * Copyright (C) 2015 Andrea Venturi
3 * Andrea Venturi <be17068@iperbole.bo.it>
5 * Copyright (C) 2016 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
14 #include <linux/clk.h>
15 #include <linux/dmaengine.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/soc-dai.h>
26 #define SUN4I_I2S_CTRL_REG 0x00
27 #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
28 #define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
29 #define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
30 #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
31 #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
32 #define SUN4I_I2S_CTRL_TX_EN BIT(2)
33 #define SUN4I_I2S_CTRL_RX_EN BIT(1)
34 #define SUN4I_I2S_CTRL_GL_EN BIT(0)
36 #define SUN4I_I2S_FMT0_REG 0x04
37 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7)
38 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7)
39 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7)
40 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6)
41 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6)
42 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6)
43 #define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)
44 #define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4)
45 #define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)
46 #define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2)
47 #define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)
48 #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
49 #define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
50 #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
52 #define SUN4I_I2S_FMT1_REG 0x08
53 #define SUN4I_I2S_FIFO_TX_REG 0x0c
54 #define SUN4I_I2S_FIFO_RX_REG 0x10
56 #define SUN4I_I2S_FIFO_CTRL_REG 0x14
57 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25)
58 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24)
59 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2)
60 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2)
61 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)
62 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode)
64 #define SUN4I_I2S_FIFO_STA_REG 0x18
66 #define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c
67 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7)
68 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3)
70 #define SUN4I_I2S_INT_STA_REG 0x20
72 #define SUN4I_I2S_CLK_DIV_REG 0x24
73 #define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7)
74 #define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)
75 #define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4)
76 #define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
77 #define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
79 #define SUN4I_I2S_RX_CNT_REG 0x28
80 #define SUN4I_I2S_TX_CNT_REG 0x2c
82 #define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
83 #define SUN4I_I2S_TX_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
85 #define SUN4I_I2S_TX_CHAN_MAP_REG 0x34
86 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2))
88 #define SUN4I_I2S_RX_CHAN_SEL_REG 0x38
89 #define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
94 struct regmap
*regmap
;
96 struct snd_dmaengine_dai_dma_data playback_dma_data
;
99 struct sun4i_i2s_clk_div
{
104 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div
[] = {
105 { .div
= 2, .val
= 0 },
106 { .div
= 4, .val
= 1 },
107 { .div
= 6, .val
= 2 },
108 { .div
= 8, .val
= 3 },
109 { .div
= 12, .val
= 4 },
110 { .div
= 16, .val
= 5 },
113 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div
[] = {
114 { .div
= 1, .val
= 0 },
115 { .div
= 2, .val
= 1 },
116 { .div
= 4, .val
= 2 },
117 { .div
= 6, .val
= 3 },
118 { .div
= 8, .val
= 4 },
119 { .div
= 12, .val
= 5 },
120 { .div
= 16, .val
= 6 },
121 { .div
= 24, .val
= 7 },
124 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s
*i2s
,
125 unsigned int oversample_rate
,
126 unsigned int word_size
)
128 int div
= oversample_rate
/ word_size
/ 2;
131 for (i
= 0; i
< ARRAY_SIZE(sun4i_i2s_bclk_div
); i
++) {
132 const struct sun4i_i2s_clk_div
*bdiv
= &sun4i_i2s_bclk_div
[i
];
134 if (bdiv
->div
== div
)
141 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s
*i2s
,
142 unsigned int oversample_rate
,
143 unsigned int module_rate
,
144 unsigned int sampling_rate
)
146 int div
= module_rate
/ sampling_rate
/ oversample_rate
;
149 for (i
= 0; i
< ARRAY_SIZE(sun4i_i2s_mclk_div
); i
++) {
150 const struct sun4i_i2s_clk_div
*mdiv
= &sun4i_i2s_mclk_div
[i
];
152 if (mdiv
->div
== div
)
159 static int sun4i_i2s_oversample_rates
[] = { 128, 192, 256, 384, 512, 768 };
161 static int sun4i_i2s_set_clk_rate(struct sun4i_i2s
*i2s
,
163 unsigned int word_size
)
165 unsigned int clk_rate
;
166 int bclk_div
, mclk_div
;
195 ret
= clk_set_rate(i2s
->mod_clk
, clk_rate
);
199 /* Always favor the highest oversampling rate */
200 for (i
= (ARRAY_SIZE(sun4i_i2s_oversample_rates
) - 1); i
>= 0; i
--) {
201 unsigned int oversample_rate
= sun4i_i2s_oversample_rates
[i
];
203 bclk_div
= sun4i_i2s_get_bclk_div(i2s
, oversample_rate
,
205 mclk_div
= sun4i_i2s_get_mclk_div(i2s
, oversample_rate
,
209 if ((bclk_div
>= 0) && (mclk_div
>= 0))
213 if ((bclk_div
< 0) || (mclk_div
< 0))
216 regmap_write(i2s
->regmap
, SUN4I_I2S_CLK_DIV_REG
,
217 SUN4I_I2S_CLK_DIV_BCLK(bclk_div
) |
218 SUN4I_I2S_CLK_DIV_MCLK(mclk_div
) |
219 SUN4I_I2S_CLK_DIV_MCLK_EN
);
224 static int sun4i_i2s_hw_params(struct snd_pcm_substream
*substream
,
225 struct snd_pcm_hw_params
*params
,
226 struct snd_soc_dai
*dai
)
228 struct sun4i_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
232 if (params_channels(params
) != 2)
235 switch (params_physical_width(params
)) {
237 width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
242 i2s
->playback_dma_data
.addr_width
= width
;
244 switch (params_width(params
)) {
254 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_FMT0_REG
,
255 SUN4I_I2S_FMT0_WSS_MASK
| SUN4I_I2S_FMT0_SR_MASK
,
256 SUN4I_I2S_FMT0_WSS(wss
) | SUN4I_I2S_FMT0_SR(sr
));
258 return sun4i_i2s_set_clk_rate(i2s
, params_rate(params
),
259 params_width(params
));
262 static int sun4i_i2s_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
264 struct sun4i_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
268 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
269 case SND_SOC_DAIFMT_I2S
:
270 val
= SUN4I_I2S_FMT0_FMT_I2S
;
272 case SND_SOC_DAIFMT_LEFT_J
:
273 val
= SUN4I_I2S_FMT0_FMT_LEFT_J
;
275 case SND_SOC_DAIFMT_RIGHT_J
:
276 val
= SUN4I_I2S_FMT0_FMT_RIGHT_J
;
282 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_FMT0_REG
,
283 SUN4I_I2S_FMT0_FMT_MASK
,
286 /* DAI clock polarity */
287 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
288 case SND_SOC_DAIFMT_IB_IF
:
289 /* Invert both clocks */
290 val
= SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED
|
291 SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED
;
293 case SND_SOC_DAIFMT_IB_NF
:
294 /* Invert bit clock */
295 val
= SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED
|
296 SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL
;
298 case SND_SOC_DAIFMT_NB_IF
:
299 /* Invert frame clock */
300 val
= SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED
|
301 SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL
;
303 case SND_SOC_DAIFMT_NB_NF
:
304 /* Nothing to do for both normal cases */
305 val
= SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL
|
306 SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL
;
312 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_FMT0_REG
,
313 SUN4I_I2S_FMT0_BCLK_POLARITY_MASK
|
314 SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK
,
317 /* DAI clock master masks */
318 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
319 case SND_SOC_DAIFMT_CBS_CFS
:
320 /* BCLK and LRCLK master */
321 val
= SUN4I_I2S_CTRL_MODE_MASTER
;
323 case SND_SOC_DAIFMT_CBM_CFM
:
324 /* BCLK and LRCLK slave */
325 val
= SUN4I_I2S_CTRL_MODE_SLAVE
;
331 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_CTRL_REG
,
332 SUN4I_I2S_CTRL_MODE_MASK
,
335 /* Set significant bits in our FIFOs */
336 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_FIFO_CTRL_REG
,
337 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK
|
338 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK
,
339 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
340 SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
344 static void sun4i_i2s_start_playback(struct sun4i_i2s
*i2s
)
347 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_FIFO_CTRL_REG
,
348 SUN4I_I2S_FIFO_CTRL_FLUSH_TX
,
349 SUN4I_I2S_FIFO_CTRL_FLUSH_TX
);
351 /* Clear TX counter */
352 regmap_write(i2s
->regmap
, SUN4I_I2S_TX_CNT_REG
, 0);
354 /* Enable TX Block */
355 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_CTRL_REG
,
356 SUN4I_I2S_CTRL_TX_EN
,
357 SUN4I_I2S_CTRL_TX_EN
);
360 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_DMA_INT_CTRL_REG
,
361 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN
,
362 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN
);
366 static void sun4i_i2s_stop_playback(struct sun4i_i2s
*i2s
)
368 /* Disable TX Block */
369 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_CTRL_REG
,
370 SUN4I_I2S_CTRL_TX_EN
,
374 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_DMA_INT_CTRL_REG
,
375 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN
,
379 static int sun4i_i2s_trigger(struct snd_pcm_substream
*substream
, int cmd
,
380 struct snd_soc_dai
*dai
)
382 struct sun4i_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
385 case SNDRV_PCM_TRIGGER_START
:
386 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
387 case SNDRV_PCM_TRIGGER_RESUME
:
388 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
389 sun4i_i2s_start_playback(i2s
);
394 case SNDRV_PCM_TRIGGER_STOP
:
395 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
396 case SNDRV_PCM_TRIGGER_SUSPEND
:
397 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
398 sun4i_i2s_stop_playback(i2s
);
410 static int sun4i_i2s_startup(struct snd_pcm_substream
*substream
,
411 struct snd_soc_dai
*dai
)
413 struct sun4i_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
415 /* Enable the whole hardware block */
416 regmap_write(i2s
->regmap
, SUN4I_I2S_CTRL_REG
,
417 SUN4I_I2S_CTRL_GL_EN
);
419 /* Enable the first output line */
420 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_CTRL_REG
,
421 SUN4I_I2S_CTRL_SDO_EN_MASK
,
422 SUN4I_I2S_CTRL_SDO_EN(0));
424 /* Enable the first two channels */
425 regmap_write(i2s
->regmap
, SUN4I_I2S_TX_CHAN_SEL_REG
,
426 SUN4I_I2S_TX_CHAN_SEL(2));
428 /* Map them to the two first samples coming in */
429 regmap_write(i2s
->regmap
, SUN4I_I2S_TX_CHAN_MAP_REG
,
430 SUN4I_I2S_TX_CHAN_MAP(0, 0) | SUN4I_I2S_TX_CHAN_MAP(1, 1));
432 return clk_prepare_enable(i2s
->mod_clk
);
435 static void sun4i_i2s_shutdown(struct snd_pcm_substream
*substream
,
436 struct snd_soc_dai
*dai
)
438 struct sun4i_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
440 clk_disable_unprepare(i2s
->mod_clk
);
442 /* Disable our output lines */
443 regmap_update_bits(i2s
->regmap
, SUN4I_I2S_CTRL_REG
,
444 SUN4I_I2S_CTRL_SDO_EN_MASK
, 0);
446 /* Disable the whole hardware block */
447 regmap_write(i2s
->regmap
, SUN4I_I2S_CTRL_REG
, 0);
450 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops
= {
451 .hw_params
= sun4i_i2s_hw_params
,
452 .set_fmt
= sun4i_i2s_set_fmt
,
453 .shutdown
= sun4i_i2s_shutdown
,
454 .startup
= sun4i_i2s_startup
,
455 .trigger
= sun4i_i2s_trigger
,
458 static int sun4i_i2s_dai_probe(struct snd_soc_dai
*dai
)
460 struct sun4i_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
462 snd_soc_dai_init_dma_data(dai
, &i2s
->playback_dma_data
, NULL
);
464 snd_soc_dai_set_drvdata(dai
, i2s
);
469 static struct snd_soc_dai_driver sun4i_i2s_dai
= {
470 .probe
= sun4i_i2s_dai_probe
,
472 .stream_name
= "Playback",
475 .rates
= SNDRV_PCM_RATE_8000_192000
,
476 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
478 .ops
= &sun4i_i2s_dai_ops
,
479 .symmetric_rates
= 1,
482 static const struct snd_soc_component_driver sun4i_i2s_component
= {
486 static bool sun4i_i2s_rd_reg(struct device
*dev
, unsigned int reg
)
489 case SUN4I_I2S_FIFO_TX_REG
:
497 static bool sun4i_i2s_wr_reg(struct device
*dev
, unsigned int reg
)
500 case SUN4I_I2S_FIFO_RX_REG
:
501 case SUN4I_I2S_FIFO_STA_REG
:
509 static bool sun4i_i2s_volatile_reg(struct device
*dev
, unsigned int reg
)
512 case SUN4I_I2S_FIFO_RX_REG
:
513 case SUN4I_I2S_INT_STA_REG
:
514 case SUN4I_I2S_RX_CNT_REG
:
515 case SUN4I_I2S_TX_CNT_REG
:
523 static const struct reg_default sun4i_i2s_reg_defaults
[] = {
524 { SUN4I_I2S_CTRL_REG
, 0x00000000 },
525 { SUN4I_I2S_FMT0_REG
, 0x0000000c },
526 { SUN4I_I2S_FMT1_REG
, 0x00004020 },
527 { SUN4I_I2S_FIFO_CTRL_REG
, 0x000400f0 },
528 { SUN4I_I2S_DMA_INT_CTRL_REG
, 0x00000000 },
529 { SUN4I_I2S_CLK_DIV_REG
, 0x00000000 },
530 { SUN4I_I2S_TX_CHAN_SEL_REG
, 0x00000001 },
531 { SUN4I_I2S_TX_CHAN_MAP_REG
, 0x76543210 },
532 { SUN4I_I2S_RX_CHAN_SEL_REG
, 0x00000001 },
533 { SUN4I_I2S_RX_CHAN_MAP_REG
, 0x00003210 },
536 static const struct regmap_config sun4i_i2s_regmap_config
= {
540 .max_register
= SUN4I_I2S_RX_CHAN_MAP_REG
,
542 .cache_type
= REGCACHE_FLAT
,
543 .reg_defaults
= sun4i_i2s_reg_defaults
,
544 .num_reg_defaults
= ARRAY_SIZE(sun4i_i2s_reg_defaults
),
545 .writeable_reg
= sun4i_i2s_wr_reg
,
546 .readable_reg
= sun4i_i2s_rd_reg
,
547 .volatile_reg
= sun4i_i2s_volatile_reg
,
550 static int sun4i_i2s_runtime_resume(struct device
*dev
)
552 struct sun4i_i2s
*i2s
= dev_get_drvdata(dev
);
555 ret
= clk_prepare_enable(i2s
->bus_clk
);
557 dev_err(dev
, "Failed to enable bus clock\n");
561 regcache_cache_only(i2s
->regmap
, false);
562 regcache_mark_dirty(i2s
->regmap
);
564 ret
= regcache_sync(i2s
->regmap
);
566 dev_err(dev
, "Failed to sync regmap cache\n");
567 goto err_disable_clk
;
573 clk_disable_unprepare(i2s
->bus_clk
);
577 static int sun4i_i2s_runtime_suspend(struct device
*dev
)
579 struct sun4i_i2s
*i2s
= dev_get_drvdata(dev
);
581 regcache_cache_only(i2s
->regmap
, true);
583 clk_disable_unprepare(i2s
->bus_clk
);
588 static int sun4i_i2s_probe(struct platform_device
*pdev
)
590 struct sun4i_i2s
*i2s
;
591 struct resource
*res
;
595 i2s
= devm_kzalloc(&pdev
->dev
, sizeof(*i2s
), GFP_KERNEL
);
598 platform_set_drvdata(pdev
, i2s
);
600 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
601 regs
= devm_ioremap_resource(&pdev
->dev
, res
);
603 return PTR_ERR(regs
);
605 irq
= platform_get_irq(pdev
, 0);
607 dev_err(&pdev
->dev
, "Can't retrieve our interrupt\n");
611 i2s
->bus_clk
= devm_clk_get(&pdev
->dev
, "apb");
612 if (IS_ERR(i2s
->bus_clk
)) {
613 dev_err(&pdev
->dev
, "Can't get our bus clock\n");
614 return PTR_ERR(i2s
->bus_clk
);
617 i2s
->regmap
= devm_regmap_init_mmio(&pdev
->dev
, regs
,
618 &sun4i_i2s_regmap_config
);
619 if (IS_ERR(i2s
->regmap
)) {
620 dev_err(&pdev
->dev
, "Regmap initialisation failed\n");
621 return PTR_ERR(i2s
->regmap
);
624 i2s
->mod_clk
= devm_clk_get(&pdev
->dev
, "mod");
625 if (IS_ERR(i2s
->mod_clk
)) {
626 dev_err(&pdev
->dev
, "Can't get our mod clock\n");
627 return PTR_ERR(i2s
->mod_clk
);
630 i2s
->playback_dma_data
.addr
= res
->start
+ SUN4I_I2S_FIFO_TX_REG
;
631 i2s
->playback_dma_data
.maxburst
= 4;
633 pm_runtime_enable(&pdev
->dev
);
634 if (!pm_runtime_enabled(&pdev
->dev
)) {
635 ret
= sun4i_i2s_runtime_resume(&pdev
->dev
);
640 ret
= devm_snd_soc_register_component(&pdev
->dev
,
641 &sun4i_i2s_component
,
644 dev_err(&pdev
->dev
, "Could not register DAI\n");
648 ret
= snd_dmaengine_pcm_register(&pdev
->dev
, NULL
, 0);
650 dev_err(&pdev
->dev
, "Could not register PCM\n");
657 if (!pm_runtime_status_suspended(&pdev
->dev
))
658 sun4i_i2s_runtime_suspend(&pdev
->dev
);
660 pm_runtime_disable(&pdev
->dev
);
665 static int sun4i_i2s_remove(struct platform_device
*pdev
)
667 snd_dmaengine_pcm_unregister(&pdev
->dev
);
669 pm_runtime_disable(&pdev
->dev
);
670 if (!pm_runtime_status_suspended(&pdev
->dev
))
671 sun4i_i2s_runtime_suspend(&pdev
->dev
);
676 static const struct of_device_id sun4i_i2s_match
[] = {
677 { .compatible
= "allwinner,sun4i-a10-i2s", },
680 MODULE_DEVICE_TABLE(of
, sun4i_i2s_match
);
682 static const struct dev_pm_ops sun4i_i2s_pm_ops
= {
683 .runtime_resume
= sun4i_i2s_runtime_resume
,
684 .runtime_suspend
= sun4i_i2s_runtime_suspend
,
687 static struct platform_driver sun4i_i2s_driver
= {
688 .probe
= sun4i_i2s_probe
,
689 .remove
= sun4i_i2s_remove
,
692 .of_match_table
= sun4i_i2s_match
,
693 .pm
= &sun4i_i2s_pm_ops
,
696 module_platform_driver(sun4i_i2s_driver
);
698 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
699 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
700 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
701 MODULE_LICENSE("GPL");