2 * tegra20_i2s.c - Tegra20 I2S driver
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2010,2012 - NVIDIA, Inc.
7 * Based on code copyright/by:
9 * Copyright (c) 2009-2010, NVIDIA Corporation.
10 * Scott Peterson <speterson@nvidia.com>
12 * Copyright (C) 2010 Google, Inc.
13 * Iliyan Malchev <malchev@google.com>
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * version 2 as published by the Free Software Foundation.
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 * General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
31 #include <linux/clk.h>
32 #include <linux/device.h>
34 #include <linux/module.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/regmap.h>
39 #include <linux/slab.h>
40 #include <sound/core.h>
41 #include <sound/pcm.h>
42 #include <sound/pcm_params.h>
43 #include <sound/soc.h>
45 #include "tegra20_i2s.h"
47 #define DRV_NAME "tegra20-i2s"
49 static inline void tegra20_i2s_write(struct tegra20_i2s
*i2s
, u32 reg
, u32 val
)
51 regmap_write(i2s
->regmap
, reg
, val
);
54 static inline u32
tegra20_i2s_read(struct tegra20_i2s
*i2s
, u32 reg
)
57 regmap_read(i2s
->regmap
, reg
, &val
);
61 static int tegra20_i2s_runtime_suspend(struct device
*dev
)
63 struct tegra20_i2s
*i2s
= dev_get_drvdata(dev
);
65 clk_disable(i2s
->clk_i2s
);
70 static int tegra20_i2s_runtime_resume(struct device
*dev
)
72 struct tegra20_i2s
*i2s
= dev_get_drvdata(dev
);
75 ret
= clk_enable(i2s
->clk_i2s
);
77 dev_err(dev
, "clk_enable failed: %d\n", ret
);
84 static int tegra20_i2s_set_fmt(struct snd_soc_dai
*dai
,
87 struct tegra20_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
89 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
90 case SND_SOC_DAIFMT_NB_NF
:
96 i2s
->reg_ctrl
&= ~TEGRA20_I2S_CTRL_MASTER_ENABLE
;
97 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
98 case SND_SOC_DAIFMT_CBS_CFS
:
99 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_MASTER_ENABLE
;
101 case SND_SOC_DAIFMT_CBM_CFM
:
107 i2s
->reg_ctrl
&= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK
|
108 TEGRA20_I2S_CTRL_LRCK_MASK
);
109 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
110 case SND_SOC_DAIFMT_DSP_A
:
111 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP
;
112 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_LRCK_L_LOW
;
114 case SND_SOC_DAIFMT_DSP_B
:
115 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP
;
116 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_LRCK_R_LOW
;
118 case SND_SOC_DAIFMT_I2S
:
119 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S
;
120 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_LRCK_L_LOW
;
122 case SND_SOC_DAIFMT_RIGHT_J
:
123 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM
;
124 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_LRCK_L_LOW
;
126 case SND_SOC_DAIFMT_LEFT_J
:
127 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM
;
128 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_LRCK_L_LOW
;
137 static int tegra20_i2s_hw_params(struct snd_pcm_substream
*substream
,
138 struct snd_pcm_hw_params
*params
,
139 struct snd_soc_dai
*dai
)
141 struct device
*dev
= dai
->dev
;
142 struct tegra20_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
144 int ret
, sample_size
, srate
, i2sclock
, bitcnt
;
146 i2s
->reg_ctrl
&= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK
;
147 switch (params_format(params
)) {
148 case SNDRV_PCM_FORMAT_S16_LE
:
149 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_BIT_SIZE_16
;
152 case SNDRV_PCM_FORMAT_S24_LE
:
153 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_BIT_SIZE_24
;
156 case SNDRV_PCM_FORMAT_S32_LE
:
157 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_BIT_SIZE_32
;
164 srate
= params_rate(params
);
166 /* Final "* 2" required by Tegra hardware */
167 i2sclock
= srate
* params_channels(params
) * sample_size
* 2;
169 ret
= clk_set_rate(i2s
->clk_i2s
, i2sclock
);
171 dev_err(dev
, "Can't set I2S clock rate: %d\n", ret
);
175 bitcnt
= (i2sclock
/ (2 * srate
)) - 1;
176 if (bitcnt
< 0 || bitcnt
> TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US
)
178 reg
= bitcnt
<< TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT
;
180 if (i2sclock
% (2 * srate
))
181 reg
|= TEGRA20_I2S_TIMING_NON_SYM_ENABLE
;
183 tegra20_i2s_write(i2s
, TEGRA20_I2S_TIMING
, reg
);
185 tegra20_i2s_write(i2s
, TEGRA20_I2S_FIFO_SCR
,
186 TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS
|
187 TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS
);
192 static void tegra20_i2s_start_playback(struct tegra20_i2s
*i2s
)
194 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_FIFO1_ENABLE
;
195 tegra20_i2s_write(i2s
, TEGRA20_I2S_CTRL
, i2s
->reg_ctrl
);
198 static void tegra20_i2s_stop_playback(struct tegra20_i2s
*i2s
)
200 i2s
->reg_ctrl
&= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE
;
201 tegra20_i2s_write(i2s
, TEGRA20_I2S_CTRL
, i2s
->reg_ctrl
);
204 static void tegra20_i2s_start_capture(struct tegra20_i2s
*i2s
)
206 i2s
->reg_ctrl
|= TEGRA20_I2S_CTRL_FIFO2_ENABLE
;
207 tegra20_i2s_write(i2s
, TEGRA20_I2S_CTRL
, i2s
->reg_ctrl
);
210 static void tegra20_i2s_stop_capture(struct tegra20_i2s
*i2s
)
212 i2s
->reg_ctrl
&= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE
;
213 tegra20_i2s_write(i2s
, TEGRA20_I2S_CTRL
, i2s
->reg_ctrl
);
216 static int tegra20_i2s_trigger(struct snd_pcm_substream
*substream
, int cmd
,
217 struct snd_soc_dai
*dai
)
219 struct tegra20_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
222 case SNDRV_PCM_TRIGGER_START
:
223 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
224 case SNDRV_PCM_TRIGGER_RESUME
:
225 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
226 tegra20_i2s_start_playback(i2s
);
228 tegra20_i2s_start_capture(i2s
);
230 case SNDRV_PCM_TRIGGER_STOP
:
231 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
232 case SNDRV_PCM_TRIGGER_SUSPEND
:
233 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
234 tegra20_i2s_stop_playback(i2s
);
236 tegra20_i2s_stop_capture(i2s
);
245 static int tegra20_i2s_probe(struct snd_soc_dai
*dai
)
247 struct tegra20_i2s
*i2s
= snd_soc_dai_get_drvdata(dai
);
249 dai
->capture_dma_data
= &i2s
->capture_dma_data
;
250 dai
->playback_dma_data
= &i2s
->playback_dma_data
;
255 static const struct snd_soc_dai_ops tegra20_i2s_dai_ops
= {
256 .set_fmt
= tegra20_i2s_set_fmt
,
257 .hw_params
= tegra20_i2s_hw_params
,
258 .trigger
= tegra20_i2s_trigger
,
261 static const struct snd_soc_dai_driver tegra20_i2s_dai_template
= {
262 .probe
= tegra20_i2s_probe
,
264 .stream_name
= "Playback",
267 .rates
= SNDRV_PCM_RATE_8000_96000
,
268 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
271 .stream_name
= "Capture",
274 .rates
= SNDRV_PCM_RATE_8000_96000
,
275 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
277 .ops
= &tegra20_i2s_dai_ops
,
278 .symmetric_rates
= 1,
281 static bool tegra20_i2s_wr_rd_reg(struct device
*dev
, unsigned int reg
)
284 case TEGRA20_I2S_CTRL
:
285 case TEGRA20_I2S_STATUS
:
286 case TEGRA20_I2S_TIMING
:
287 case TEGRA20_I2S_FIFO_SCR
:
288 case TEGRA20_I2S_PCM_CTRL
:
289 case TEGRA20_I2S_NW_CTRL
:
290 case TEGRA20_I2S_TDM_CTRL
:
291 case TEGRA20_I2S_TDM_TX_RX_CTRL
:
292 case TEGRA20_I2S_FIFO1
:
293 case TEGRA20_I2S_FIFO2
:
300 static bool tegra20_i2s_volatile_reg(struct device
*dev
, unsigned int reg
)
303 case TEGRA20_I2S_STATUS
:
304 case TEGRA20_I2S_FIFO_SCR
:
305 case TEGRA20_I2S_FIFO1
:
306 case TEGRA20_I2S_FIFO2
:
313 static bool tegra20_i2s_precious_reg(struct device
*dev
, unsigned int reg
)
316 case TEGRA20_I2S_FIFO1
:
317 case TEGRA20_I2S_FIFO2
:
324 static const struct regmap_config tegra20_i2s_regmap_config
= {
328 .max_register
= TEGRA20_I2S_FIFO2
,
329 .writeable_reg
= tegra20_i2s_wr_rd_reg
,
330 .readable_reg
= tegra20_i2s_wr_rd_reg
,
331 .volatile_reg
= tegra20_i2s_volatile_reg
,
332 .precious_reg
= tegra20_i2s_precious_reg
,
333 .cache_type
= REGCACHE_RBTREE
,
336 static __devinit
int tegra20_i2s_platform_probe(struct platform_device
*pdev
)
338 struct tegra20_i2s
*i2s
;
339 struct resource
*mem
, *memregion
, *dmareq
;
345 i2s
= devm_kzalloc(&pdev
->dev
, sizeof(struct tegra20_i2s
), GFP_KERNEL
);
347 dev_err(&pdev
->dev
, "Can't allocate tegra20_i2s\n");
351 dev_set_drvdata(&pdev
->dev
, i2s
);
353 i2s
->dai
= tegra20_i2s_dai_template
;
354 i2s
->dai
.name
= dev_name(&pdev
->dev
);
356 i2s
->clk_i2s
= clk_get(&pdev
->dev
, NULL
);
357 if (IS_ERR(i2s
->clk_i2s
)) {
358 dev_err(&pdev
->dev
, "Can't retrieve i2s clock\n");
359 ret
= PTR_ERR(i2s
->clk_i2s
);
363 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
365 dev_err(&pdev
->dev
, "No memory resource\n");
370 dmareq
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
372 if (of_property_read_u32_array(pdev
->dev
.of_node
,
373 "nvidia,dma-request-selector",
375 dev_err(&pdev
->dev
, "No DMA resource\n");
381 dma_ch
= dmareq
->start
;
384 memregion
= devm_request_mem_region(&pdev
->dev
, mem
->start
,
385 resource_size(mem
), DRV_NAME
);
387 dev_err(&pdev
->dev
, "Memory region already claimed\n");
392 regs
= devm_ioremap(&pdev
->dev
, mem
->start
, resource_size(mem
));
394 dev_err(&pdev
->dev
, "ioremap failed\n");
399 i2s
->regmap
= devm_regmap_init_mmio(&pdev
->dev
, regs
,
400 &tegra20_i2s_regmap_config
);
401 if (IS_ERR(i2s
->regmap
)) {
402 dev_err(&pdev
->dev
, "regmap init failed\n");
403 ret
= PTR_ERR(i2s
->regmap
);
407 i2s
->capture_dma_data
.addr
= mem
->start
+ TEGRA20_I2S_FIFO2
;
408 i2s
->capture_dma_data
.wrap
= 4;
409 i2s
->capture_dma_data
.width
= 32;
410 i2s
->capture_dma_data
.req_sel
= dma_ch
;
412 i2s
->playback_dma_data
.addr
= mem
->start
+ TEGRA20_I2S_FIFO1
;
413 i2s
->playback_dma_data
.wrap
= 4;
414 i2s
->playback_dma_data
.width
= 32;
415 i2s
->playback_dma_data
.req_sel
= dma_ch
;
417 i2s
->reg_ctrl
= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED
;
419 pm_runtime_enable(&pdev
->dev
);
420 if (!pm_runtime_enabled(&pdev
->dev
)) {
421 ret
= tegra20_i2s_runtime_resume(&pdev
->dev
);
426 ret
= snd_soc_register_dai(&pdev
->dev
, &i2s
->dai
);
428 dev_err(&pdev
->dev
, "Could not register DAI: %d\n", ret
);
433 ret
= tegra_pcm_platform_register(&pdev
->dev
);
435 dev_err(&pdev
->dev
, "Could not register PCM: %d\n", ret
);
436 goto err_unregister_dai
;
442 snd_soc_unregister_dai(&pdev
->dev
);
444 if (!pm_runtime_status_suspended(&pdev
->dev
))
445 tegra20_i2s_runtime_suspend(&pdev
->dev
);
447 pm_runtime_disable(&pdev
->dev
);
449 clk_put(i2s
->clk_i2s
);
454 static int __devexit
tegra20_i2s_platform_remove(struct platform_device
*pdev
)
456 struct tegra20_i2s
*i2s
= dev_get_drvdata(&pdev
->dev
);
458 pm_runtime_disable(&pdev
->dev
);
459 if (!pm_runtime_status_suspended(&pdev
->dev
))
460 tegra20_i2s_runtime_suspend(&pdev
->dev
);
462 tegra_pcm_platform_unregister(&pdev
->dev
);
463 snd_soc_unregister_dai(&pdev
->dev
);
465 clk_put(i2s
->clk_i2s
);
470 static const struct of_device_id tegra20_i2s_of_match
[] __devinitconst
= {
471 { .compatible
= "nvidia,tegra20-i2s", },
475 static const struct dev_pm_ops tegra20_i2s_pm_ops __devinitconst
= {
476 SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend
,
477 tegra20_i2s_runtime_resume
, NULL
)
480 static struct platform_driver tegra20_i2s_driver
= {
483 .owner
= THIS_MODULE
,
484 .of_match_table
= tegra20_i2s_of_match
,
485 .pm
= &tegra20_i2s_pm_ops
,
487 .probe
= tegra20_i2s_platform_probe
,
488 .remove
= __devexit_p(tegra20_i2s_platform_remove
),
490 module_platform_driver(tegra20_i2s_driver
);
492 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
493 MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
494 MODULE_LICENSE("GPL");
495 MODULE_ALIAS("platform:" DRV_NAME
);
496 MODULE_DEVICE_TABLE(of
, tegra20_i2s_of_match
);