sound/soc/tegra/tegra20_i2s.c

   1 /*
   2  * tegra20_i2s.c - Tegra20 I2S driver
   3  *
   4  * Author: Stephen Warren <swarren@nvidia.com>
   5  * Copyright (C) 2010,2012 - NVIDIA, Inc.
   6  *
   7  * Based on code copyright/by:
   8  *
   9  * Copyright (c) 2009-2010, NVIDIA Corporation.
  10  * Scott Peterson <speterson@nvidia.com>
  11  *
  12  * Copyright (C) 2010 Google, Inc.
  13  * Iliyan Malchev <malchev@google.com>
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * version 2 as published by the Free Software Foundation.
  18  *
  19  * This program is distributed in the hope that it will be useful, but
  20  * WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  22  * General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  27  * 02110-1301 USA
  28  *
  29  */
  30
  31 #include <linux/clk.h>
  32 #include <linux/device.h>
  33 #include <linux/io.h>
  34 #include <linux/module.h>
  35 #include <linux/of.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/regmap.h>
  39 #include <linux/slab.h>
  40 #include <sound/core.h>
  41 #include <sound/pcm.h>
  42 #include <sound/pcm_params.h>
  43 #include <sound/soc.h>
  44
  45 #include "tegra20_i2s.h"
  46
  47 #define DRV_NAME "tegra20-i2s"
  48
  49 static int tegra20_i2s_runtime_suspend(struct device *dev)
  50 {
  51         struct tegra20_i2s *i2s = dev_get_drvdata(dev);
  52
  53         clk_disable_unprepare(i2s->clk_i2s);
  54
  55         return 0;
  56 }
  57
  58 static int tegra20_i2s_runtime_resume(struct device *dev)
  59 {
  60         struct tegra20_i2s *i2s = dev_get_drvdata(dev);
  61         int ret;
  62
  63         ret = clk_prepare_enable(i2s->clk_i2s);
  64         if (ret) {
  65                 dev_err(dev, "clk_enable failed: %d\n", ret);
  66                 return ret;
  67         }
  68
  69         return 0;
  70 }
  71
  72 static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
  73                                 unsigned int fmt)
  74 {
  75         struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  76         unsigned int mask, val;
  77
  78         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  79         case SND_SOC_DAIFMT_NB_NF:
  80                 break;
  81         default:
  82                 return -EINVAL;
  83         }
  84
  85         mask = TEGRA20_I2S_CTRL_MASTER_ENABLE;
  86         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  87         case SND_SOC_DAIFMT_CBS_CFS:
  88                 val = TEGRA20_I2S_CTRL_MASTER_ENABLE;
  89                 break;
  90         case SND_SOC_DAIFMT_CBM_CFM:
  91                 break;
  92         default:
  93                 return -EINVAL;
  94         }
  95
  96         mask |= TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
  97                 TEGRA20_I2S_CTRL_LRCK_MASK;
  98         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  99         case SND_SOC_DAIFMT_DSP_A:
 100                 val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
 101                 val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
 102                 break;
 103         case SND_SOC_DAIFMT_DSP_B:
 104                 val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
 105                 val |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
 106                 break;
 107         case SND_SOC_DAIFMT_I2S:
 108                 val |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
 109                 val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
 110                 break;
 111         case SND_SOC_DAIFMT_RIGHT_J:
 112                 val |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
 113                 val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
 114                 break;
 115         case SND_SOC_DAIFMT_LEFT_J:
 116                 val |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
 117                 val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
 118                 break;
 119         default:
 120                 return -EINVAL;
 121         }
 122
 123         regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
 124
 125         return 0;
 126 }
 127
 128 static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
 129                                  struct snd_pcm_hw_params *params,
 130                                  struct snd_soc_dai *dai)
 131 {
 132         struct device *dev = dai->dev;
 133         struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 134         unsigned int mask, val;
 135         int ret, sample_size, srate, i2sclock, bitcnt;
 136
 137         mask = TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
 138         switch (params_format(params)) {
 139         case SNDRV_PCM_FORMAT_S16_LE:
 140                 val = TEGRA20_I2S_CTRL_BIT_SIZE_16;
 141                 sample_size = 16;
 142                 break;
 143         case SNDRV_PCM_FORMAT_S24_LE:
 144                 val = TEGRA20_I2S_CTRL_BIT_SIZE_24;
 145                 sample_size = 24;
 146                 break;
 147         case SNDRV_PCM_FORMAT_S32_LE:
 148                 val = TEGRA20_I2S_CTRL_BIT_SIZE_32;
 149                 sample_size = 32;
 150                 break;
 151         default:
 152                 return -EINVAL;
 153         }
 154
 155         mask |= TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK;
 156         val |= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
 157
 158         regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
 159
 160         srate = params_rate(params);
 161
 162         /* Final "* 2" required by Tegra hardware */
 163         i2sclock = srate * params_channels(params) * sample_size * 2;
 164
 165         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
 166         if (ret) {
 167                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
 168                 return ret;
 169         }
 170
 171         bitcnt = (i2sclock / (2 * srate)) - 1;
 172         if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
 173                 return -EINVAL;
 174         val = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
 175
 176         if (i2sclock % (2 * srate))
 177                 val |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
 178
 179         regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val);
 180
 181         regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR,
 182                      TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
 183                      TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
 184
 185         return 0;
 186 }
 187
 188 static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
 189 {
 190         regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
 191                            TEGRA20_I2S_CTRL_FIFO1_ENABLE,
 192                            TEGRA20_I2S_CTRL_FIFO1_ENABLE);
 193 }
 194
 195 static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
 196 {
 197         regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
 198                            TEGRA20_I2S_CTRL_FIFO1_ENABLE, 0);
 199 }
 200
 201 static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
 202 {
 203         regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
 204                            TEGRA20_I2S_CTRL_FIFO2_ENABLE,
 205                            TEGRA20_I2S_CTRL_FIFO2_ENABLE);
 206 }
 207
 208 static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
 209 {
 210         regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
 211                            TEGRA20_I2S_CTRL_FIFO2_ENABLE, 0);
 212 }
 213
 214 static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 215                                struct snd_soc_dai *dai)
 216 {
 217         struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 218
 219         switch (cmd) {
 220         case SNDRV_PCM_TRIGGER_START:
 221         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 222         case SNDRV_PCM_TRIGGER_RESUME:
 223                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 224                         tegra20_i2s_start_playback(i2s);
 225                 else
 226                         tegra20_i2s_start_capture(i2s);
 227                 break;
 228         case SNDRV_PCM_TRIGGER_STOP:
 229         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 230         case SNDRV_PCM_TRIGGER_SUSPEND:
 231                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 232                         tegra20_i2s_stop_playback(i2s);
 233                 else
 234                         tegra20_i2s_stop_capture(i2s);
 235                 break;
 236         default:
 237                 return -EINVAL;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int tegra20_i2s_probe(struct snd_soc_dai *dai)
 244 {
 245         struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 246
 247         dai->capture_dma_data = &i2s->capture_dma_data;
 248         dai->playback_dma_data = &i2s->playback_dma_data;
 249
 250         return 0;
 251 }
 252
 253 static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
 254         .set_fmt        = tegra20_i2s_set_fmt,
 255         .hw_params      = tegra20_i2s_hw_params,
 256         .trigger        = tegra20_i2s_trigger,
 257 };
 258
 259 static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
 260         .probe = tegra20_i2s_probe,
 261         .playback = {
 262                 .stream_name = "Playback",
 263                 .channels_min = 2,
 264                 .channels_max = 2,
 265                 .rates = SNDRV_PCM_RATE_8000_96000,
 266                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 267         },
 268         .capture = {
 269                 .stream_name = "Capture",
 270                 .channels_min = 2,
 271                 .channels_max = 2,
 272                 .rates = SNDRV_PCM_RATE_8000_96000,
 273                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 274         },
 275         .ops = &tegra20_i2s_dai_ops,
 276         .symmetric_rates = 1,
 277 };
 278
 279 static const struct snd_soc_component_driver tegra20_i2s_component = {
 280         .name           = DRV_NAME,
 281 };
 282
 283 static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
 284 {
 285         switch (reg) {
 286         case TEGRA20_I2S_CTRL:
 287         case TEGRA20_I2S_STATUS:
 288         case TEGRA20_I2S_TIMING:
 289         case TEGRA20_I2S_FIFO_SCR:
 290         case TEGRA20_I2S_PCM_CTRL:
 291         case TEGRA20_I2S_NW_CTRL:
 292         case TEGRA20_I2S_TDM_CTRL:
 293         case TEGRA20_I2S_TDM_TX_RX_CTRL:
 294         case TEGRA20_I2S_FIFO1:
 295         case TEGRA20_I2S_FIFO2:
 296                 return true;
 297         default:
 298                 return false;
 299         };
 300 }
 301
 302 static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg)
 303 {
 304         switch (reg) {
 305         case TEGRA20_I2S_STATUS:
 306         case TEGRA20_I2S_FIFO_SCR:
 307         case TEGRA20_I2S_FIFO1:
 308         case TEGRA20_I2S_FIFO2:
 309                 return true;
 310         default:
 311                 return false;
 312         };
 313 }
 314
 315 static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg)
 316 {
 317         switch (reg) {
 318         case TEGRA20_I2S_FIFO1:
 319         case TEGRA20_I2S_FIFO2:
 320                 return true;
 321         default:
 322                 return false;
 323         };
 324 }
 325
 326 static const struct regmap_config tegra20_i2s_regmap_config = {
 327         .reg_bits = 32,
 328         .reg_stride = 4,
 329         .val_bits = 32,
 330         .max_register = TEGRA20_I2S_FIFO2,
 331         .writeable_reg = tegra20_i2s_wr_rd_reg,
 332         .readable_reg = tegra20_i2s_wr_rd_reg,
 333         .volatile_reg = tegra20_i2s_volatile_reg,
 334         .precious_reg = tegra20_i2s_precious_reg,
 335         .cache_type = REGCACHE_RBTREE,
 336 };
 337
 338 static int tegra20_i2s_platform_probe(struct platform_device *pdev)
 339 {
 340         struct tegra20_i2s *i2s;
 341         struct resource *mem, *memregion, *dmareq;
 342         u32 of_dma[2];
 343         u32 dma_ch;
 344         void __iomem *regs;
 345         int ret;
 346
 347         i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
 348         if (!i2s) {
 349                 dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
 350                 ret = -ENOMEM;
 351                 goto err;
 352         }
 353         dev_set_drvdata(&pdev->dev, i2s);
 354
 355         i2s->dai = tegra20_i2s_dai_template;
 356         i2s->dai.name = dev_name(&pdev->dev);
 357
 358         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
 359         if (IS_ERR(i2s->clk_i2s)) {
 360                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
 361                 ret = PTR_ERR(i2s->clk_i2s);
 362                 goto err;
 363         }
 364
 365         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 366         if (!mem) {
 367                 dev_err(&pdev->dev, "No memory resource\n");
 368                 ret = -ENODEV;
 369                 goto err_clk_put;
 370         }
 371
 372         dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 373         if (!dmareq) {
 374                 if (of_property_read_u32_array(pdev->dev.of_node,
 375                                         "nvidia,dma-request-selector",
 376                                         of_dma, 2) < 0) {
 377                         dev_err(&pdev->dev, "No DMA resource\n");
 378                         ret = -ENODEV;
 379                         goto err_clk_put;
 380                 }
 381                 dma_ch = of_dma[1];
 382         } else {
 383                 dma_ch = dmareq->start;
 384         }
 385
 386         memregion = devm_request_mem_region(&pdev->dev, mem->start,
 387                                             resource_size(mem), DRV_NAME);
 388         if (!memregion) {
 389                 dev_err(&pdev->dev, "Memory region already claimed\n");
 390                 ret = -EBUSY;
 391                 goto err_clk_put;
 392         }
 393
 394         regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
 395         if (!regs) {
 396                 dev_err(&pdev->dev, "ioremap failed\n");
 397                 ret = -ENOMEM;
 398                 goto err_clk_put;
 399         }
 400
 401         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 402                                             &tegra20_i2s_regmap_config);
 403         if (IS_ERR(i2s->regmap)) {
 404                 dev_err(&pdev->dev, "regmap init failed\n");
 405                 ret = PTR_ERR(i2s->regmap);
 406                 goto err_clk_put;
 407         }
 408
 409         i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
 410         i2s->capture_dma_data.wrap = 4;
 411         i2s->capture_dma_data.width = 32;
 412         i2s->capture_dma_data.req_sel = dma_ch;
 413
 414         i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
 415         i2s->playback_dma_data.wrap = 4;
 416         i2s->playback_dma_data.width = 32;
 417         i2s->playback_dma_data.req_sel = dma_ch;
 418
 419         pm_runtime_enable(&pdev->dev);
 420         if (!pm_runtime_enabled(&pdev->dev)) {
 421                 ret = tegra20_i2s_runtime_resume(&pdev->dev);
 422                 if (ret)
 423                         goto err_pm_disable;
 424         }
 425
 426         ret = snd_soc_register_component(&pdev->dev, &tegra20_i2s_component,
 427                                          &i2s->dai, 1);
 428         if (ret) {
 429                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 430                 ret = -ENOMEM;
 431                 goto err_suspend;
 432         }
 433
 434         ret = tegra_pcm_platform_register(&pdev->dev);
 435         if (ret) {
 436                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 437                 goto err_unregister_component;
 438         }
 439
 440         return 0;
 441
 442 err_unregister_component:
 443         snd_soc_unregister_component(&pdev->dev);
 444 err_suspend:
 445         if (!pm_runtime_status_suspended(&pdev->dev))
 446                 tegra20_i2s_runtime_suspend(&pdev->dev);
 447 err_pm_disable:
 448         pm_runtime_disable(&pdev->dev);
 449 err_clk_put:
 450         clk_put(i2s->clk_i2s);
 451 err:
 452         return ret;
 453 }
 454
 455 static int tegra20_i2s_platform_remove(struct platform_device *pdev)
 456 {
 457         struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);
 458
 459         pm_runtime_disable(&pdev->dev);
 460         if (!pm_runtime_status_suspended(&pdev->dev))
 461                 tegra20_i2s_runtime_suspend(&pdev->dev);
 462
 463         tegra_pcm_platform_unregister(&pdev->dev);
 464         snd_soc_unregister_component(&pdev->dev);
 465
 466         clk_put(i2s->clk_i2s);
 467
 468         return 0;
 469 }
 470
 471 static const struct of_device_id tegra20_i2s_of_match[] = {
 472         { .compatible = "nvidia,tegra20-i2s", },
 473         {},
 474 };
 475
 476 static const struct dev_pm_ops tegra20_i2s_pm_ops = {
 477         SET_RUNTIME_PM_OPS(tegra20_i2s_runtime_suspend,
 478                            tegra20_i2s_runtime_resume, NULL)
 479 };
 480
 481 static struct platform_driver tegra20_i2s_driver = {
 482         .driver = {
 483                 .name = DRV_NAME,
 484                 .owner = THIS_MODULE,
 485                 .of_match_table = tegra20_i2s_of_match,
 486                 .pm = &tegra20_i2s_pm_ops,
 487         },
 488         .probe = tegra20_i2s_platform_probe,
 489         .remove = tegra20_i2s_platform_remove,
 490 };
 491 module_platform_driver(tegra20_i2s_driver);
 492
 493 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 494 MODULE_DESCRIPTION("Tegra20 I2S ASoC driver");
 495 MODULE_LICENSE("GPL");
 496 MODULE_ALIAS("platform:" DRV_NAME);
 497 MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);