2 * tegra20_spdif.c - Tegra20 SPDIF driver
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2011-2012 - NVIDIA, Inc.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 #include <linux/clk.h>
24 #include <linux/module.h>
25 #include <linux/debugfs.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include <mach/iomap.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/soc.h>
37 #include "tegra20_spdif.h"
39 #define DRV_NAME "tegra20-spdif"
41 static inline void tegra20_spdif_write(struct tegra20_spdif
*spdif
, u32 reg
,
44 __raw_writel(val
, spdif
->regs
+ reg
);
47 static inline u32
tegra20_spdif_read(struct tegra20_spdif
*spdif
, u32 reg
)
49 return __raw_readl(spdif
->regs
+ reg
);
52 #ifdef CONFIG_DEBUG_FS
53 static int tegra20_spdif_show(struct seq_file
*s
, void *unused
)
55 #define REG(r) { r, #r }
60 REG(TEGRA20_SPDIF_CTRL
),
61 REG(TEGRA20_SPDIF_STATUS
),
62 REG(TEGRA20_SPDIF_STROBE_CTRL
),
63 REG(TEGRA20_SPDIF_DATA_FIFO_CSR
),
64 REG(TEGRA20_SPDIF_CH_STA_RX_A
),
65 REG(TEGRA20_SPDIF_CH_STA_RX_B
),
66 REG(TEGRA20_SPDIF_CH_STA_RX_C
),
67 REG(TEGRA20_SPDIF_CH_STA_RX_D
),
68 REG(TEGRA20_SPDIF_CH_STA_RX_E
),
69 REG(TEGRA20_SPDIF_CH_STA_RX_F
),
70 REG(TEGRA20_SPDIF_CH_STA_TX_A
),
71 REG(TEGRA20_SPDIF_CH_STA_TX_B
),
72 REG(TEGRA20_SPDIF_CH_STA_TX_C
),
73 REG(TEGRA20_SPDIF_CH_STA_TX_D
),
74 REG(TEGRA20_SPDIF_CH_STA_TX_E
),
75 REG(TEGRA20_SPDIF_CH_STA_TX_F
),
79 struct tegra20_spdif
*spdif
= s
->private;
82 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
83 u32 val
= tegra20_spdif_read(spdif
, regs
[i
].offset
);
84 seq_printf(s
, "%s = %08x\n", regs
[i
].name
, val
);
90 static int tegra20_spdif_debug_open(struct inode
*inode
, struct file
*file
)
92 return single_open(file
, tegra20_spdif_show
, inode
->i_private
);
95 static const struct file_operations tegra20_spdif_debug_fops
= {
96 .open
= tegra20_spdif_debug_open
,
99 .release
= single_release
,
102 static void tegra20_spdif_debug_add(struct tegra20_spdif
*spdif
)
104 spdif
->debug
= debugfs_create_file(DRV_NAME
, S_IRUGO
,
105 snd_soc_debugfs_root
, spdif
,
106 &tegra20_spdif_debug_fops
);
109 static void tegra20_spdif_debug_remove(struct tegra20_spdif
*spdif
)
112 debugfs_remove(spdif
->debug
);
115 static inline void tegra20_spdif_debug_add(struct tegra20_spdif
*spdif
)
119 static inline void tegra20_spdif_debug_remove(struct tegra20_spdif
*spdif
)
124 static int tegra20_spdif_hw_params(struct snd_pcm_substream
*substream
,
125 struct snd_pcm_hw_params
*params
,
126 struct snd_soc_dai
*dai
)
128 struct device
*dev
= substream
->pcm
->card
->dev
;
129 struct tegra20_spdif
*spdif
= snd_soc_dai_get_drvdata(dai
);
132 spdif
->reg_ctrl
&= ~TEGRA20_SPDIF_CTRL_PACK
;
133 spdif
->reg_ctrl
&= ~TEGRA20_SPDIF_CTRL_BIT_MODE_MASK
;
134 switch (params_format(params
)) {
135 case SNDRV_PCM_FORMAT_S16_LE
:
136 spdif
->reg_ctrl
|= TEGRA20_SPDIF_CTRL_PACK
;
137 spdif
->reg_ctrl
|= TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT
;
143 switch (params_rate(params
)) {
145 spdifclock
= 4096000;
148 spdifclock
= 5644800;
151 spdifclock
= 6144000;
154 spdifclock
= 11289600;
157 spdifclock
= 12288000;
160 spdifclock
= 22579200;
163 spdifclock
= 24576000;
169 ret
= clk_set_rate(spdif
->clk_spdif_out
, spdifclock
);
171 dev_err(dev
, "Can't set SPDIF clock rate: %d\n", ret
);
178 static void tegra20_spdif_start_playback(struct tegra20_spdif
*spdif
)
180 spdif
->reg_ctrl
|= TEGRA20_SPDIF_CTRL_TX_EN
;
181 tegra20_spdif_write(spdif
, TEGRA20_SPDIF_CTRL
, spdif
->reg_ctrl
);
184 static void tegra20_spdif_stop_playback(struct tegra20_spdif
*spdif
)
186 spdif
->reg_ctrl
&= ~TEGRA20_SPDIF_CTRL_TX_EN
;
187 tegra20_spdif_write(spdif
, TEGRA20_SPDIF_CTRL
, spdif
->reg_ctrl
);
190 static int tegra20_spdif_trigger(struct snd_pcm_substream
*substream
, int cmd
,
191 struct snd_soc_dai
*dai
)
193 struct tegra20_spdif
*spdif
= snd_soc_dai_get_drvdata(dai
);
196 case SNDRV_PCM_TRIGGER_START
:
197 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
198 case SNDRV_PCM_TRIGGER_RESUME
:
199 clk_enable(spdif
->clk_spdif_out
);
200 tegra20_spdif_start_playback(spdif
);
202 case SNDRV_PCM_TRIGGER_STOP
:
203 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
204 case SNDRV_PCM_TRIGGER_SUSPEND
:
205 tegra20_spdif_stop_playback(spdif
);
206 clk_disable(spdif
->clk_spdif_out
);
215 static int tegra20_spdif_probe(struct snd_soc_dai
*dai
)
217 struct tegra20_spdif
*spdif
= snd_soc_dai_get_drvdata(dai
);
219 dai
->capture_dma_data
= NULL
;
220 dai
->playback_dma_data
= &spdif
->playback_dma_data
;
225 static const struct snd_soc_dai_ops tegra20_spdif_dai_ops
= {
226 .hw_params
= tegra20_spdif_hw_params
,
227 .trigger
= tegra20_spdif_trigger
,
230 static struct snd_soc_dai_driver tegra20_spdif_dai
= {
232 .probe
= tegra20_spdif_probe
,
236 .rates
= SNDRV_PCM_RATE_32000
| SNDRV_PCM_RATE_44100
|
237 SNDRV_PCM_RATE_48000
,
238 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
240 .ops
= &tegra20_spdif_dai_ops
,
243 static __devinit
int tegra20_spdif_platform_probe(struct platform_device
*pdev
)
245 struct tegra20_spdif
*spdif
;
246 struct resource
*mem
, *memregion
, *dmareq
;
249 spdif
= kzalloc(sizeof(struct tegra20_spdif
), GFP_KERNEL
);
251 dev_err(&pdev
->dev
, "Can't allocate tegra20_spdif\n");
255 dev_set_drvdata(&pdev
->dev
, spdif
);
257 spdif
->clk_spdif_out
= clk_get(&pdev
->dev
, "spdif_out");
258 if (IS_ERR(spdif
->clk_spdif_out
)) {
259 pr_err("Can't retrieve spdif clock\n");
260 ret
= PTR_ERR(spdif
->clk_spdif_out
);
264 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
266 dev_err(&pdev
->dev
, "No memory resource\n");
271 dmareq
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
273 dev_err(&pdev
->dev
, "No DMA resource\n");
278 memregion
= request_mem_region(mem
->start
, resource_size(mem
),
281 dev_err(&pdev
->dev
, "Memory region already claimed\n");
286 spdif
->regs
= ioremap(mem
->start
, resource_size(mem
));
288 dev_err(&pdev
->dev
, "ioremap failed\n");
293 spdif
->playback_dma_data
.addr
= mem
->start
+ TEGRA20_SPDIF_DATA_OUT
;
294 spdif
->playback_dma_data
.wrap
= 4;
295 spdif
->playback_dma_data
.width
= 32;
296 spdif
->playback_dma_data
.req_sel
= dmareq
->start
;
298 ret
= snd_soc_register_dai(&pdev
->dev
, &tegra20_spdif_dai
);
300 dev_err(&pdev
->dev
, "Could not register DAI: %d\n", ret
);
305 ret
= tegra_pcm_platform_register(&pdev
->dev
);
307 dev_err(&pdev
->dev
, "Could not register PCM: %d\n", ret
);
308 goto err_unregister_dai
;
311 tegra20_spdif_debug_add(spdif
);
316 snd_soc_unregister_dai(&pdev
->dev
);
318 iounmap(spdif
->regs
);
320 release_mem_region(mem
->start
, resource_size(mem
));
322 clk_put(spdif
->clk_spdif_out
);
329 static int __devexit
tegra20_spdif_platform_remove(struct platform_device
*pdev
)
331 struct tegra20_spdif
*spdif
= dev_get_drvdata(&pdev
->dev
);
332 struct resource
*res
;
334 tegra_pcm_platform_unregister(&pdev
->dev
);
335 snd_soc_unregister_dai(&pdev
->dev
);
337 tegra20_spdif_debug_remove(spdif
);
339 iounmap(spdif
->regs
);
341 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
342 release_mem_region(res
->start
, resource_size(res
));
344 clk_put(spdif
->clk_spdif_out
);
351 static struct platform_driver tegra20_spdif_driver
= {
354 .owner
= THIS_MODULE
,
356 .probe
= tegra20_spdif_platform_probe
,
357 .remove
= __devexit_p(tegra20_spdif_platform_remove
),
360 module_platform_driver(tegra20_spdif_driver
);
362 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
363 MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
364 MODULE_LICENSE("GPL");
365 MODULE_ALIAS("platform:" DRV_NAME
);