sound/soc/tegra/tegra30_ahub.c

   1 /*
   2  * tegra30_ahub.c - Tegra30 AHUB driver
   3  *
   4  * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/device.h>
  21 #include <linux/io.h>
  22 #include <linux/module.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regmap.h>
  27 #include <linux/slab.h>
  28 #include <mach/clk.h>
  29 #include <sound/soc.h>
  30 #include "tegra30_ahub.h"
  31
  32 #define DRV_NAME "tegra30-ahub"
  33
  34 static struct tegra30_ahub *ahub;
  35
  36 static inline void tegra30_apbif_write(u32 reg, u32 val)
  37 {
  38         regmap_write(ahub->regmap_apbif, reg, val);
  39 }
  40
  41 static inline u32 tegra30_apbif_read(u32 reg)
  42 {
  43         u32 val;
  44         regmap_read(ahub->regmap_apbif, reg, &val);
  45         return val;
  46 }
  47
  48 static inline void tegra30_audio_write(u32 reg, u32 val)
  49 {
  50         regmap_write(ahub->regmap_ahub, reg, val);
  51 }
  52
  53 static int tegra30_ahub_runtime_suspend(struct device *dev)
  54 {
  55         regcache_cache_only(ahub->regmap_apbif, true);
  56         regcache_cache_only(ahub->regmap_ahub, true);
  57
  58         clk_disable_unprepare(ahub->clk_apbif);
  59         clk_disable_unprepare(ahub->clk_d_audio);
  60
  61         return 0;
  62 }
  63
  64 /*
  65  * clk_apbif isn't required for an I2S<->I2S configuration where no PCM data
  66  * is read from or sent to memory. However, that's not something the rest of
  67  * the driver supports right now, so we'll just treat the two clocks as one
  68  * for now.
  69  *
  70  * These functions should not be a plain ref-count. Instead, each active stream
  71  * contributes some requirement to the minimum clock rate, so starting or
  72  * stopping streams should dynamically adjust the clock as required.  However,
  73  * this is not yet implemented.
  74  */
  75 static int tegra30_ahub_runtime_resume(struct device *dev)
  76 {
  77         int ret;
  78
  79         ret = clk_prepare_enable(ahub->clk_d_audio);
  80         if (ret) {
  81                 dev_err(dev, "clk_enable d_audio failed: %d\n", ret);
  82                 return ret;
  83         }
  84         ret = clk_prepare_enable(ahub->clk_apbif);
  85         if (ret) {
  86                 dev_err(dev, "clk_enable apbif failed: %d\n", ret);
  87                 clk_disable(ahub->clk_d_audio);
  88                 return ret;
  89         }
  90
  91         regcache_cache_only(ahub->regmap_apbif, false);
  92         regcache_cache_only(ahub->regmap_ahub, false);
  93
  94         return 0;
  95 }
  96
  97 int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
  98                                   unsigned long *fiforeg,
  99                                   unsigned long *reqsel)
 100 {
 101         int channel;
 102         u32 reg, val;
 103
 104         channel = find_first_zero_bit(ahub->rx_usage,
 105                                       TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
 106         if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
 107                 return -EBUSY;
 108
 109         __set_bit(channel, ahub->rx_usage);
 110
 111         *rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel;
 112         *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO +
 113                    (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
 114         *reqsel = ahub->dma_sel + channel;
 115
 116         reg = TEGRA30_AHUB_CHANNEL_CTRL +
 117               (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 118         val = tegra30_apbif_read(reg);
 119         val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK |
 120                  TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK);
 121         val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) |
 122                TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN |
 123                TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16;
 124         tegra30_apbif_write(reg, val);
 125
 126         reg = TEGRA30_AHUB_CIF_RX_CTRL +
 127               (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
 128         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
 129               (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
 130               (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
 131               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
 132               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 |
 133               TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
 134         tegra30_apbif_write(reg, val);
 135
 136         return 0;
 137 }
 138 EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
 139
 140 int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 141 {
 142         int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 143         int reg, val;
 144
 145         reg = TEGRA30_AHUB_CHANNEL_CTRL +
 146               (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 147         val = tegra30_apbif_read(reg);
 148         val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
 149         tegra30_apbif_write(reg, val);
 150
 151         return 0;
 152 }
 153 EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
 154
 155 int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 156 {
 157         int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 158         int reg, val;
 159
 160         reg = TEGRA30_AHUB_CHANNEL_CTRL +
 161               (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 162         val = tegra30_apbif_read(reg);
 163         val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
 164         tegra30_apbif_write(reg, val);
 165
 166         return 0;
 167 }
 168 EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
 169
 170 int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif)
 171 {
 172         int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 173
 174         __clear_bit(channel, ahub->rx_usage);
 175
 176         return 0;
 177 }
 178 EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo);
 179
 180 int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
 181                                   unsigned long *fiforeg,
 182                                   unsigned long *reqsel)
 183 {
 184         int channel;
 185         u32 reg, val;
 186
 187         channel = find_first_zero_bit(ahub->tx_usage,
 188                                       TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
 189         if (channel >= TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
 190                 return -EBUSY;
 191
 192         __set_bit(channel, ahub->tx_usage);
 193
 194         *txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel;
 195         *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO +
 196                    (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
 197         *reqsel = ahub->dma_sel + channel;
 198
 199         reg = TEGRA30_AHUB_CHANNEL_CTRL +
 200               (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 201         val = tegra30_apbif_read(reg);
 202         val &= ~(TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK |
 203                  TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK);
 204         val |= (7 << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) |
 205                TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN |
 206                TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16;
 207         tegra30_apbif_write(reg, val);
 208
 209         reg = TEGRA30_AHUB_CIF_TX_CTRL +
 210               (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
 211         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
 212               (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
 213               (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
 214               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
 215               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 |
 216               TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
 217         tegra30_apbif_write(reg, val);
 218
 219         return 0;
 220 }
 221 EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
 222
 223 int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
 224 {
 225         int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
 226         int reg, val;
 227
 228         reg = TEGRA30_AHUB_CHANNEL_CTRL +
 229               (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 230         val = tegra30_apbif_read(reg);
 231         val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
 232         tegra30_apbif_write(reg, val);
 233
 234         return 0;
 235 }
 236 EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
 237
 238 int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
 239 {
 240         int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
 241         int reg, val;
 242
 243         reg = TEGRA30_AHUB_CHANNEL_CTRL +
 244               (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
 245         val = tegra30_apbif_read(reg);
 246         val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
 247         tegra30_apbif_write(reg, val);
 248
 249         return 0;
 250 }
 251 EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
 252
 253 int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif)
 254 {
 255         int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
 256
 257         __clear_bit(channel, ahub->tx_usage);
 258
 259         return 0;
 260 }
 261 EXPORT_SYMBOL_GPL(tegra30_ahub_free_tx_fifo);
 262
 263 int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
 264                                    enum tegra30_ahub_txcif txcif)
 265 {
 266         int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 267         int reg;
 268
 269         reg = TEGRA30_AHUB_AUDIO_RX +
 270               (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
 271         tegra30_audio_write(reg, 1 << txcif);
 272
 273         return 0;
 274 }
 275 EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
 276
 277 int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
 278 {
 279         int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
 280         int reg;
 281
 282         reg = TEGRA30_AHUB_AUDIO_RX +
 283               (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
 284         tegra30_audio_write(reg, 0);
 285
 286         return 0;
 287 }
 288 EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
 289
 290 static const char * const configlink_clocks[] = {
 291         "i2s0",
 292         "i2s1",
 293         "i2s2",
 294         "i2s3",
 295         "i2s4",
 296         "dam0",
 297         "dam1",
 298         "dam2",
 299         "spdif_in",
 300 };
 301
 302 struct of_dev_auxdata ahub_auxdata[] = {
 303         OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080300, "tegra30-i2s.0", NULL),
 304         OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080400, "tegra30-i2s.1", NULL),
 305         OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080500, "tegra30-i2s.2", NULL),
 306         OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080600, "tegra30-i2s.3", NULL),
 307         OF_DEV_AUXDATA("nvidia,tegra30-i2s", 0x70080700, "tegra30-i2s.4", NULL),
 308         {}
 309 };
 310
 311 #define LAST_REG(name) \
 312         (TEGRA30_AHUB_##name + \
 313          (TEGRA30_AHUB_##name##_STRIDE * TEGRA30_AHUB_##name##_COUNT) - 4)
 314
 315 #define REG_IN_ARRAY(reg, name) \
 316         ((reg >= TEGRA30_AHUB_##name) && \
 317          (reg <= LAST_REG(name) && \
 318          (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE))))
 319
 320 static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg)
 321 {
 322         switch (reg) {
 323         case TEGRA30_AHUB_CONFIG_LINK_CTRL:
 324         case TEGRA30_AHUB_MISC_CTRL:
 325         case TEGRA30_AHUB_APBDMA_LIVE_STATUS:
 326         case TEGRA30_AHUB_I2S_LIVE_STATUS:
 327         case TEGRA30_AHUB_SPDIF_LIVE_STATUS:
 328         case TEGRA30_AHUB_I2S_INT_MASK:
 329         case TEGRA30_AHUB_DAM_INT_MASK:
 330         case TEGRA30_AHUB_SPDIF_INT_MASK:
 331         case TEGRA30_AHUB_APBIF_INT_MASK:
 332         case TEGRA30_AHUB_I2S_INT_STATUS:
 333         case TEGRA30_AHUB_DAM_INT_STATUS:
 334         case TEGRA30_AHUB_SPDIF_INT_STATUS:
 335         case TEGRA30_AHUB_APBIF_INT_STATUS:
 336         case TEGRA30_AHUB_I2S_INT_SOURCE:
 337         case TEGRA30_AHUB_DAM_INT_SOURCE:
 338         case TEGRA30_AHUB_SPDIF_INT_SOURCE:
 339         case TEGRA30_AHUB_APBIF_INT_SOURCE:
 340         case TEGRA30_AHUB_I2S_INT_SET:
 341         case TEGRA30_AHUB_DAM_INT_SET:
 342         case TEGRA30_AHUB_SPDIF_INT_SET:
 343         case TEGRA30_AHUB_APBIF_INT_SET:
 344                 return true;
 345         default:
 346                 break;
 347         };
 348
 349         if (REG_IN_ARRAY(reg, CHANNEL_CTRL) ||
 350             REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||
 351             REG_IN_ARRAY(reg, CHANNEL_STATUS) ||
 352             REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
 353             REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||
 354             REG_IN_ARRAY(reg, CIF_TX_CTRL) ||
 355             REG_IN_ARRAY(reg, CIF_RX_CTRL) ||
 356             REG_IN_ARRAY(reg, DAM_LIVE_STATUS))
 357                 return true;
 358
 359         return false;
 360 }
 361
 362 static bool tegra30_ahub_apbif_volatile_reg(struct device *dev,
 363                                             unsigned int reg)
 364 {
 365         switch (reg) {
 366         case TEGRA30_AHUB_CONFIG_LINK_CTRL:
 367         case TEGRA30_AHUB_MISC_CTRL:
 368         case TEGRA30_AHUB_APBDMA_LIVE_STATUS:
 369         case TEGRA30_AHUB_I2S_LIVE_STATUS:
 370         case TEGRA30_AHUB_SPDIF_LIVE_STATUS:
 371         case TEGRA30_AHUB_I2S_INT_STATUS:
 372         case TEGRA30_AHUB_DAM_INT_STATUS:
 373         case TEGRA30_AHUB_SPDIF_INT_STATUS:
 374         case TEGRA30_AHUB_APBIF_INT_STATUS:
 375         case TEGRA30_AHUB_I2S_INT_SET:
 376         case TEGRA30_AHUB_DAM_INT_SET:
 377         case TEGRA30_AHUB_SPDIF_INT_SET:
 378         case TEGRA30_AHUB_APBIF_INT_SET:
 379                 return true;
 380         default:
 381                 break;
 382         };
 383
 384         if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||
 385             REG_IN_ARRAY(reg, CHANNEL_STATUS) ||
 386             REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
 387             REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||
 388             REG_IN_ARRAY(reg, DAM_LIVE_STATUS))
 389                 return true;
 390
 391         return false;
 392 }
 393
 394 static bool tegra30_ahub_apbif_precious_reg(struct device *dev,
 395                                             unsigned int reg)
 396 {
 397         if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||
 398             REG_IN_ARRAY(reg, CHANNEL_RXFIFO))
 399                 return true;
 400
 401         return false;
 402 }
 403
 404 static const struct regmap_config tegra30_ahub_apbif_regmap_config = {
 405         .name = "apbif",
 406         .reg_bits = 32,
 407         .val_bits = 32,
 408         .reg_stride = 4,
 409         .max_register = TEGRA30_AHUB_APBIF_INT_SET,
 410         .writeable_reg = tegra30_ahub_apbif_wr_rd_reg,
 411         .readable_reg = tegra30_ahub_apbif_wr_rd_reg,
 412         .volatile_reg = tegra30_ahub_apbif_volatile_reg,
 413         .precious_reg = tegra30_ahub_apbif_precious_reg,
 414         .cache_type = REGCACHE_RBTREE,
 415 };
 416
 417 static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg)
 418 {
 419         if (REG_IN_ARRAY(reg, AUDIO_RX))
 420                 return true;
 421
 422         return false;
 423 }
 424
 425 static const struct regmap_config tegra30_ahub_ahub_regmap_config = {
 426         .name = "ahub",
 427         .reg_bits = 32,
 428         .val_bits = 32,
 429         .reg_stride = 4,
 430         .max_register = LAST_REG(AUDIO_RX),
 431         .writeable_reg = tegra30_ahub_ahub_wr_rd_reg,
 432         .readable_reg = tegra30_ahub_ahub_wr_rd_reg,
 433         .cache_type = REGCACHE_RBTREE,
 434 };
 435
 436 static int tegra30_ahub_probe(struct platform_device *pdev)
 437 {
 438         struct clk *clk;
 439         int i;
 440         struct resource *res0, *res1, *region;
 441         u32 of_dma[2];
 442         void __iomem *regs_apbif, *regs_ahub;
 443         int ret = 0;
 444
 445         if (ahub)
 446                 return -ENODEV;
 447
 448         /*
 449          * The AHUB hosts a register bus: the "configlink". For this to
 450          * operate correctly, all devices on this bus must be out of reset.
 451          * Ensure that here.
 452          */
 453         for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) {
 454                 clk = clk_get_sys(NULL, configlink_clocks[i]);
 455                 if (IS_ERR(clk)) {
 456                         dev_err(&pdev->dev, "Can't get clock %s\n",
 457                                 configlink_clocks[i]);
 458                         ret = PTR_ERR(clk);
 459                         goto err;
 460                 }
 461                 tegra_periph_reset_deassert(clk);
 462                 clk_put(clk);
 463         }
 464
 465         ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
 466                             GFP_KERNEL);
 467         if (!ahub) {
 468                 dev_err(&pdev->dev, "Can't allocate tegra30_ahub\n");
 469                 ret = -ENOMEM;
 470                 goto err;
 471         }
 472         dev_set_drvdata(&pdev->dev, ahub);
 473
 474         ahub->dev = &pdev->dev;
 475
 476         ahub->clk_d_audio = clk_get(&pdev->dev, "d_audio");
 477         if (IS_ERR(ahub->clk_d_audio)) {
 478                 dev_err(&pdev->dev, "Can't retrieve ahub d_audio clock\n");
 479                 ret = PTR_ERR(ahub->clk_d_audio);
 480                 goto err;
 481         }
 482
 483         ahub->clk_apbif = clk_get(&pdev->dev, "apbif");
 484         if (IS_ERR(ahub->clk_apbif)) {
 485                 dev_err(&pdev->dev, "Can't retrieve ahub apbif clock\n");
 486                 ret = PTR_ERR(ahub->clk_apbif);
 487                 goto err_clk_put_d_audio;
 488         }
 489
 490         if (of_property_read_u32_array(pdev->dev.of_node,
 491                                 "nvidia,dma-request-selector",
 492                                 of_dma, 2) < 0) {
 493                 dev_err(&pdev->dev,
 494                         "Missing property nvidia,dma-request-selector\n");
 495                 ret = -ENODEV;
 496                 goto err_clk_put_d_audio;
 497         }
 498         ahub->dma_sel = of_dma[1];
 499
 500         res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 501         if (!res0) {
 502                 dev_err(&pdev->dev, "No apbif memory resource\n");
 503                 ret = -ENODEV;
 504                 goto err_clk_put_apbif;
 505         }
 506
 507         region = devm_request_mem_region(&pdev->dev, res0->start,
 508                                          resource_size(res0), DRV_NAME);
 509         if (!region) {
 510                 dev_err(&pdev->dev, "request region apbif failed\n");
 511                 ret = -EBUSY;
 512                 goto err_clk_put_apbif;
 513         }
 514         ahub->apbif_addr = res0->start;
 515
 516         regs_apbif = devm_ioremap(&pdev->dev, res0->start,
 517                                   resource_size(res0));
 518         if (!regs_apbif) {
 519                 dev_err(&pdev->dev, "ioremap apbif failed\n");
 520                 ret = -ENOMEM;
 521                 goto err_clk_put_apbif;
 522         }
 523
 524         ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif,
 525                                         &tegra30_ahub_apbif_regmap_config);
 526         if (IS_ERR(ahub->regmap_apbif)) {
 527                 dev_err(&pdev->dev, "apbif regmap init failed\n");
 528                 ret = PTR_ERR(ahub->regmap_apbif);
 529                 goto err_clk_put_apbif;
 530         }
 531         regcache_cache_only(ahub->regmap_apbif, true);
 532
 533         res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 534         if (!res1) {
 535                 dev_err(&pdev->dev, "No ahub memory resource\n");
 536                 ret = -ENODEV;
 537                 goto err_clk_put_apbif;
 538         }
 539
 540         region = devm_request_mem_region(&pdev->dev, res1->start,
 541                                          resource_size(res1), DRV_NAME);
 542         if (!region) {
 543                 dev_err(&pdev->dev, "request region ahub failed\n");
 544                 ret = -EBUSY;
 545                 goto err_clk_put_apbif;
 546         }
 547
 548         regs_ahub = devm_ioremap(&pdev->dev, res1->start,
 549                                  resource_size(res1));
 550         if (!regs_ahub) {
 551                 dev_err(&pdev->dev, "ioremap ahub failed\n");
 552                 ret = -ENOMEM;
 553                 goto err_clk_put_apbif;
 554         }
 555
 556         ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub,
 557                                         &tegra30_ahub_ahub_regmap_config);
 558         if (IS_ERR(ahub->regmap_ahub)) {
 559                 dev_err(&pdev->dev, "ahub regmap init failed\n");
 560                 ret = PTR_ERR(ahub->regmap_ahub);
 561                 goto err_clk_put_apbif;
 562         }
 563         regcache_cache_only(ahub->regmap_ahub, true);
 564
 565         pm_runtime_enable(&pdev->dev);
 566         if (!pm_runtime_enabled(&pdev->dev)) {
 567                 ret = tegra30_ahub_runtime_resume(&pdev->dev);
 568                 if (ret)
 569                         goto err_pm_disable;
 570         }
 571
 572         of_platform_populate(pdev->dev.of_node, NULL, ahub_auxdata,
 573                              &pdev->dev);
 574
 575         return 0;
 576
 577 err_pm_disable:
 578         pm_runtime_disable(&pdev->dev);
 579 err_clk_put_apbif:
 580         clk_put(ahub->clk_apbif);
 581 err_clk_put_d_audio:
 582         clk_put(ahub->clk_d_audio);
 583         ahub = NULL;
 584 err:
 585         return ret;
 586 }
 587
 588 static int tegra30_ahub_remove(struct platform_device *pdev)
 589 {
 590         if (!ahub)
 591                 return -ENODEV;
 592
 593         pm_runtime_disable(&pdev->dev);
 594         if (!pm_runtime_status_suspended(&pdev->dev))
 595                 tegra30_ahub_runtime_suspend(&pdev->dev);
 596
 597         clk_put(ahub->clk_apbif);
 598         clk_put(ahub->clk_d_audio);
 599
 600         ahub = NULL;
 601
 602         return 0;
 603 }
 604
 605 static const struct of_device_id tegra30_ahub_of_match[] = {
 606         { .compatible = "nvidia,tegra30-ahub", },
 607         {},
 608 };
 609
 610 static const struct dev_pm_ops tegra30_ahub_pm_ops = {
 611         SET_RUNTIME_PM_OPS(tegra30_ahub_runtime_suspend,
 612                            tegra30_ahub_runtime_resume, NULL)
 613 };
 614
 615 static struct platform_driver tegra30_ahub_driver = {
 616         .probe = tegra30_ahub_probe,
 617         .remove = tegra30_ahub_remove,
 618         .driver = {
 619                 .name = DRV_NAME,
 620                 .owner = THIS_MODULE,
 621                 .of_match_table = tegra30_ahub_of_match,
 622                 .pm = &tegra30_ahub_pm_ops,
 623         },
 624 };
 625 module_platform_driver(tegra30_ahub_driver);
 626
 627 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 628 MODULE_DESCRIPTION("Tegra30 AHUB driver");
 629 MODULE_LICENSE("GPL v2");
 630 MODULE_ALIAS("platform:" DRV_NAME);
 631 MODULE_DEVICE_TABLE(of, tegra30_ahub_of_match);