sound/soc/tegra/tegra30_i2s.c

   1 /*
   2  * tegra30_i2s.c - Tegra30 I2S driver
   3  *
   4  * Author: Stephen Warren <swarren@nvidia.com>
   5  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Based on code copyright/by:
   8  *
   9  * Copyright (c) 2009-2010, NVIDIA Corporation.
  10  * Scott Peterson <speterson@nvidia.com>
  11  *
  12  * Copyright (C) 2010 Google, Inc.
  13  * Iliyan Malchev <malchev@google.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms and conditions of the GNU General Public License,
  17  * version 2, as published by the Free Software Foundation.
  18  *
  19  * This program is distributed in the hope it will be useful, but WITHOUT
  20  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  22  * more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  26  */
  27
  28 #include <linux/clk.h>
  29 #include <linux/device.h>
  30 #include <linux/io.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/regmap.h>
  36 #include <linux/slab.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/pcm_params.h>
  40 #include <sound/soc.h>
  41
  42 #include "tegra30_ahub.h"
  43 #include "tegra30_i2s.h"
  44
  45 #define DRV_NAME "tegra30-i2s"
  46
  47 static inline void tegra30_i2s_write(struct tegra30_i2s *i2s, u32 reg, u32 val)
  48 {
  49         regmap_write(i2s->regmap, reg, val);
  50 }
  51
  52 static inline u32 tegra30_i2s_read(struct tegra30_i2s *i2s, u32 reg)
  53 {
  54         u32 val;
  55         regmap_read(i2s->regmap, reg, &val);
  56         return val;
  57 }
  58
  59 static int tegra30_i2s_runtime_suspend(struct device *dev)
  60 {
  61         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
  62
  63         regcache_cache_only(i2s->regmap, true);
  64
  65         clk_disable(i2s->clk_i2s);
  66
  67         return 0;
  68 }
  69
  70 static int tegra30_i2s_runtime_resume(struct device *dev)
  71 {
  72         struct tegra30_i2s *i2s = dev_get_drvdata(dev);
  73         int ret;
  74
  75         ret = clk_enable(i2s->clk_i2s);
  76         if (ret) {
  77                 dev_err(dev, "clk_enable failed: %d\n", ret);
  78                 return ret;
  79         }
  80
  81         regcache_cache_only(i2s->regmap, false);
  82
  83         return 0;
  84 }
  85
  86 int tegra30_i2s_startup(struct snd_pcm_substream *substream,
  87                         struct snd_soc_dai *dai)
  88 {
  89         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  90         int ret;
  91
  92         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  93                 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
  94                                         &i2s->playback_dma_data.addr,
  95                                         &i2s->playback_dma_data.req_sel);
  96                 i2s->playback_dma_data.wrap = 4;
  97                 i2s->playback_dma_data.width = 32;
  98                 tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
  99                                                i2s->playback_fifo_cif);
 100         } else {
 101                 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
 102                                         &i2s->capture_dma_data.addr,
 103                                         &i2s->capture_dma_data.req_sel);
 104                 i2s->capture_dma_data.wrap = 4;
 105                 i2s->capture_dma_data.width = 32;
 106                 tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
 107                                                i2s->capture_i2s_cif);
 108         }
 109
 110         return ret;
 111 }
 112
 113 void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
 114                         struct snd_soc_dai *dai)
 115 {
 116         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 117
 118         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 119                 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
 120                 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
 121         } else {
 122                 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
 123                 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
 124         }
 125 }
 126
 127 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
 128                                 unsigned int fmt)
 129 {
 130         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 131
 132         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 133         case SND_SOC_DAIFMT_NB_NF:
 134                 break;
 135         default:
 136                 return -EINVAL;
 137         }
 138
 139         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_MASTER_ENABLE;
 140         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 141         case SND_SOC_DAIFMT_CBS_CFS:
 142                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
 143                 break;
 144         case SND_SOC_DAIFMT_CBM_CFM:
 145                 break;
 146         default:
 147                 return -EINVAL;
 148         }
 149
 150         i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
 151                            TEGRA30_I2S_CTRL_LRCK_MASK);
 152         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 153         case SND_SOC_DAIFMT_DSP_A:
 154                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
 155                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 156                 break;
 157         case SND_SOC_DAIFMT_DSP_B:
 158                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
 159                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
 160                 break;
 161         case SND_SOC_DAIFMT_I2S:
 162                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
 163                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 164                 break;
 165         case SND_SOC_DAIFMT_RIGHT_J:
 166                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
 167                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 168                 break;
 169         case SND_SOC_DAIFMT_LEFT_J:
 170                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
 171                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
 172                 break;
 173         default:
 174                 return -EINVAL;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
 181                                  struct snd_pcm_hw_params *params,
 182                                  struct snd_soc_dai *dai)
 183 {
 184         struct device *dev = dai->dev;
 185         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 186         u32 val;
 187         int ret, sample_size, srate, i2sclock, bitcnt;
 188
 189         if (params_channels(params) != 2)
 190                 return -EINVAL;
 191
 192         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
 193         switch (params_format(params)) {
 194         case SNDRV_PCM_FORMAT_S16_LE:
 195                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
 196                 sample_size = 16;
 197                 break;
 198         default:
 199                 return -EINVAL;
 200         }
 201
 202         srate = params_rate(params);
 203
 204         /* Final "* 2" required by Tegra hardware */
 205         i2sclock = srate * params_channels(params) * sample_size * 2;
 206
 207         bitcnt = (i2sclock / (2 * srate)) - 1;
 208         if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
 209                 return -EINVAL;
 210
 211         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
 212         if (ret) {
 213                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
 214                 return ret;
 215         }
 216
 217         val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
 218
 219         if (i2sclock % (2 * srate))
 220                 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
 221
 222         tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
 223
 224         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
 225               (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
 226               (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
 227               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
 228               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
 229
 230         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 231                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
 232                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
 233         } else {
 234                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
 235                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
 236         }
 237
 238         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
 239               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
 240         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
 241
 242         return 0;
 243 }
 244
 245 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
 246 {
 247         tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
 248         i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
 249         tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
 250 }
 251
 252 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
 253 {
 254         tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
 255         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
 256         tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
 257 }
 258
 259 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
 260 {
 261         tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
 262         i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
 263         tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
 264 }
 265
 266 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
 267 {
 268         tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
 269         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
 270         tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
 271 }
 272
 273 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 274                                 struct snd_soc_dai *dai)
 275 {
 276         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 277
 278         switch (cmd) {
 279         case SNDRV_PCM_TRIGGER_START:
 280         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 281         case SNDRV_PCM_TRIGGER_RESUME:
 282                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 283                         tegra30_i2s_start_playback(i2s);
 284                 else
 285                         tegra30_i2s_start_capture(i2s);
 286                 break;
 287         case SNDRV_PCM_TRIGGER_STOP:
 288         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 289         case SNDRV_PCM_TRIGGER_SUSPEND:
 290                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 291                         tegra30_i2s_stop_playback(i2s);
 292                 else
 293                         tegra30_i2s_stop_capture(i2s);
 294                 break;
 295         default:
 296                 return -EINVAL;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
 303 {
 304         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 305
 306         dai->capture_dma_data = &i2s->capture_dma_data;
 307         dai->playback_dma_data = &i2s->playback_dma_data;
 308
 309         return 0;
 310 }
 311
 312 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
 313         .startup        = tegra30_i2s_startup,
 314         .shutdown       = tegra30_i2s_shutdown,
 315         .set_fmt        = tegra30_i2s_set_fmt,
 316         .hw_params      = tegra30_i2s_hw_params,
 317         .trigger        = tegra30_i2s_trigger,
 318 };
 319
 320 static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
 321         .probe = tegra30_i2s_probe,
 322         .playback = {
 323                 .stream_name = "Playback",
 324                 .channels_min = 2,
 325                 .channels_max = 2,
 326                 .rates = SNDRV_PCM_RATE_8000_96000,
 327                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 328         },
 329         .capture = {
 330                 .stream_name = "Capture",
 331                 .channels_min = 2,
 332                 .channels_max = 2,
 333                 .rates = SNDRV_PCM_RATE_8000_96000,
 334                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 335         },
 336         .ops = &tegra30_i2s_dai_ops,
 337         .symmetric_rates = 1,
 338 };
 339
 340 static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
 341 {
 342         switch (reg) {
 343         case TEGRA30_I2S_CTRL:
 344         case TEGRA30_I2S_TIMING:
 345         case TEGRA30_I2S_OFFSET:
 346         case TEGRA30_I2S_CH_CTRL:
 347         case TEGRA30_I2S_SLOT_CTRL:
 348         case TEGRA30_I2S_CIF_RX_CTRL:
 349         case TEGRA30_I2S_CIF_TX_CTRL:
 350         case TEGRA30_I2S_FLOWCTL:
 351         case TEGRA30_I2S_TX_STEP:
 352         case TEGRA30_I2S_FLOW_STATUS:
 353         case TEGRA30_I2S_FLOW_TOTAL:
 354         case TEGRA30_I2S_FLOW_OVER:
 355         case TEGRA30_I2S_FLOW_UNDER:
 356         case TEGRA30_I2S_LCOEF_1_4_0:
 357         case TEGRA30_I2S_LCOEF_1_4_1:
 358         case TEGRA30_I2S_LCOEF_1_4_2:
 359         case TEGRA30_I2S_LCOEF_1_4_3:
 360         case TEGRA30_I2S_LCOEF_1_4_4:
 361         case TEGRA30_I2S_LCOEF_1_4_5:
 362         case TEGRA30_I2S_LCOEF_2_4_0:
 363         case TEGRA30_I2S_LCOEF_2_4_1:
 364         case TEGRA30_I2S_LCOEF_2_4_2:
 365                 return true;
 366         default:
 367                 return false;
 368         };
 369 }
 370
 371 static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
 372 {
 373         switch (reg) {
 374         case TEGRA30_I2S_FLOW_STATUS:
 375         case TEGRA30_I2S_FLOW_TOTAL:
 376         case TEGRA30_I2S_FLOW_OVER:
 377         case TEGRA30_I2S_FLOW_UNDER:
 378                 return true;
 379         default:
 380                 return false;
 381         };
 382 }
 383
 384 static const struct regmap_config tegra30_i2s_regmap_config = {
 385         .reg_bits = 32,
 386         .reg_stride = 4,
 387         .val_bits = 32,
 388         .max_register = TEGRA30_I2S_LCOEF_2_4_2,
 389         .writeable_reg = tegra30_i2s_wr_rd_reg,
 390         .readable_reg = tegra30_i2s_wr_rd_reg,
 391         .volatile_reg = tegra30_i2s_volatile_reg,
 392         .cache_type = REGCACHE_RBTREE,
 393 };
 394
 395 static __devinit int tegra30_i2s_platform_probe(struct platform_device *pdev)
 396 {
 397         struct tegra30_i2s *i2s;
 398         u32 cif_ids[2];
 399         struct resource *mem, *memregion;
 400         void __iomem *regs;
 401         int ret;
 402
 403         i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
 404         if (!i2s) {
 405                 dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
 406                 ret = -ENOMEM;
 407                 goto err;
 408         }
 409         dev_set_drvdata(&pdev->dev, i2s);
 410
 411         i2s->dai = tegra30_i2s_dai_template;
 412         i2s->dai.name = dev_name(&pdev->dev);
 413
 414         ret = of_property_read_u32_array(pdev->dev.of_node,
 415                                          "nvidia,ahub-cif-ids", cif_ids,
 416                                          ARRAY_SIZE(cif_ids));
 417         if (ret < 0)
 418                 goto err;
 419
 420         i2s->playback_i2s_cif = cif_ids[0];
 421         i2s->capture_i2s_cif = cif_ids[1];
 422
 423         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
 424         if (IS_ERR(i2s->clk_i2s)) {
 425                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
 426                 ret = PTR_ERR(i2s->clk_i2s);
 427                 goto err;
 428         }
 429
 430         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 431         if (!mem) {
 432                 dev_err(&pdev->dev, "No memory resource\n");
 433                 ret = -ENODEV;
 434                 goto err_clk_put;
 435         }
 436
 437         memregion = devm_request_mem_region(&pdev->dev, mem->start,
 438                                             resource_size(mem), DRV_NAME);
 439         if (!memregion) {
 440                 dev_err(&pdev->dev, "Memory region already claimed\n");
 441                 ret = -EBUSY;
 442                 goto err_clk_put;
 443         }
 444
 445         regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
 446         if (!regs) {
 447                 dev_err(&pdev->dev, "ioremap failed\n");
 448                 ret = -ENOMEM;
 449                 goto err_clk_put;
 450         }
 451
 452         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 453                                             &tegra30_i2s_regmap_config);
 454         if (IS_ERR(i2s->regmap)) {
 455                 dev_err(&pdev->dev, "regmap init failed\n");
 456                 ret = PTR_ERR(i2s->regmap);
 457                 goto err_clk_put;
 458         }
 459         regcache_cache_only(i2s->regmap, true);
 460
 461         pm_runtime_enable(&pdev->dev);
 462         if (!pm_runtime_enabled(&pdev->dev)) {
 463                 ret = tegra30_i2s_runtime_resume(&pdev->dev);
 464                 if (ret)
 465                         goto err_pm_disable;
 466         }
 467
 468         ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
 469         if (ret) {
 470                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 471                 ret = -ENOMEM;
 472                 goto err_suspend;
 473         }
 474
 475         ret = tegra_pcm_platform_register(&pdev->dev);
 476         if (ret) {
 477                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 478                 goto err_unregister_dai;
 479         }
 480
 481         return 0;
 482
 483 err_unregister_dai:
 484         snd_soc_unregister_dai(&pdev->dev);
 485 err_suspend:
 486         if (!pm_runtime_status_suspended(&pdev->dev))
 487                 tegra30_i2s_runtime_suspend(&pdev->dev);
 488 err_pm_disable:
 489         pm_runtime_disable(&pdev->dev);
 490 err_clk_put:
 491         clk_put(i2s->clk_i2s);
 492 err:
 493         return ret;
 494 }
 495
 496 static int __devexit tegra30_i2s_platform_remove(struct platform_device *pdev)
 497 {
 498         struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
 499
 500         pm_runtime_disable(&pdev->dev);
 501         if (!pm_runtime_status_suspended(&pdev->dev))
 502                 tegra30_i2s_runtime_suspend(&pdev->dev);
 503
 504         tegra_pcm_platform_unregister(&pdev->dev);
 505         snd_soc_unregister_dai(&pdev->dev);
 506
 507         clk_put(i2s->clk_i2s);
 508
 509         return 0;
 510 }
 511
 512 static const struct of_device_id tegra30_i2s_of_match[] __devinitconst = {
 513         { .compatible = "nvidia,tegra30-i2s", },
 514         {},
 515 };
 516
 517 static const struct dev_pm_ops tegra30_i2s_pm_ops __devinitconst = {
 518         SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
 519                            tegra30_i2s_runtime_resume, NULL)
 520 };
 521
 522 static struct platform_driver tegra30_i2s_driver = {
 523         .driver = {
 524                 .name = DRV_NAME,
 525                 .owner = THIS_MODULE,
 526                 .of_match_table = tegra30_i2s_of_match,
 527                 .pm = &tegra30_i2s_pm_ops,
 528         },
 529         .probe = tegra30_i2s_platform_probe,
 530         .remove = __devexit_p(tegra30_i2s_platform_remove),
 531 };
 532 module_platform_driver(tegra30_i2s_driver);
 533
 534 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 535 MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
 536 MODULE_LICENSE("GPL");
 537 MODULE_ALIAS("platform:" DRV_NAME);
 538 MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);