sound/soc/tegra/tegra_asoc_utils.c

   1 /*
   2  * tegra_asoc_utils.c - Harmony machine ASoC driver
   3  *
   4  * Author: Stephen Warren <swarren@nvidia.com>
   5  * Copyright (C) 2010,2012 - NVIDIA, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19  * 02110-1301 USA
  20  *
  21  */
  22
  23 #include <linux/clk.h>
  24 #include <linux/device.h>
  25 #include <linux/err.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/of.h>
  29
  30 #include "tegra_asoc_utils.h"
  31
  32 int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
  33                               int mclk)
  34 {
  35         int new_baseclock;
  36         bool clk_change;
  37         int err;
  38
  39         switch (srate) {
  40         case 11025:
  41         case 22050:
  42         case 44100:
  43         case 88200:
  44                 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
  45                         new_baseclock = 56448000;
  46                 else
  47                         new_baseclock = 564480000;
  48                 break;
  49         case 8000:
  50         case 16000:
  51         case 32000:
  52         case 48000:
  53         case 64000:
  54         case 96000:
  55                 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
  56                         new_baseclock = 73728000;
  57                 else
  58                         new_baseclock = 552960000;
  59                 break;
  60         default:
  61                 return -EINVAL;
  62         }
  63
  64         clk_change = ((new_baseclock != data->set_baseclock) ||
  65                         (mclk != data->set_mclk));
  66         if (!clk_change)
  67                 return 0;
  68
  69         data->set_baseclock = 0;
  70         data->set_mclk = 0;
  71
  72         clk_disable_unprepare(data->clk_cdev1);
  73         clk_disable_unprepare(data->clk_pll_a_out0);
  74         clk_disable_unprepare(data->clk_pll_a);
  75
  76         err = clk_set_rate(data->clk_pll_a, new_baseclock);
  77         if (err) {
  78                 dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
  79                 return err;
  80         }
  81
  82         err = clk_set_rate(data->clk_pll_a_out0, mclk);
  83         if (err) {
  84                 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
  85                 return err;
  86         }
  87
  88         /* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
  89
  90         err = clk_prepare_enable(data->clk_pll_a);
  91         if (err) {
  92                 dev_err(data->dev, "Can't enable pll_a: %d\n", err);
  93                 return err;
  94         }
  95
  96         err = clk_prepare_enable(data->clk_pll_a_out0);
  97         if (err) {
  98                 dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
  99                 return err;
 100         }
 101
 102         err = clk_prepare_enable(data->clk_cdev1);
 103         if (err) {
 104                 dev_err(data->dev, "Can't enable cdev1: %d\n", err);
 105                 return err;
 106         }
 107
 108         data->set_baseclock = new_baseclock;
 109         data->set_mclk = mclk;
 110
 111         return 0;
 112 }
 113 EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
 114
 115 int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
 116                           struct device *dev)
 117 {
 118         int ret;
 119
 120         data->dev = dev;
 121
 122         if (of_machine_is_compatible("nvidia,tegra20"))
 123                 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
 124         else if (of_machine_is_compatible("nvidia,tegra30"))
 125                 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30;
 126         else if (!dev->of_node)
 127                 /* non-DT is always Tegra20 */
 128                 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
 129         else
 130                 /* DT boot, but unknown SoC */
 131                 return -EINVAL;
 132
 133         data->clk_pll_a = clk_get_sys(NULL, "pll_a");
 134         if (IS_ERR(data->clk_pll_a)) {
 135                 dev_err(data->dev, "Can't retrieve clk pll_a\n");
 136                 ret = PTR_ERR(data->clk_pll_a);
 137                 goto err;
 138         }
 139
 140         data->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
 141         if (IS_ERR(data->clk_pll_a_out0)) {
 142                 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
 143                 ret = PTR_ERR(data->clk_pll_a_out0);
 144                 goto err_put_pll_a;
 145         }
 146
 147         if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
 148                 data->clk_cdev1 = clk_get_sys(NULL, "cdev1");
 149         else
 150                 data->clk_cdev1 = clk_get_sys("extern1", NULL);
 151         if (IS_ERR(data->clk_cdev1)) {
 152                 dev_err(data->dev, "Can't retrieve clk cdev1\n");
 153                 ret = PTR_ERR(data->clk_cdev1);
 154                 goto err_put_pll_a_out0;
 155         }
 156
 157         ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
 158         if (ret)
 159                 goto err_put_cdev1;
 160
 161         return 0;
 162
 163 err_put_cdev1:
 164         clk_put(data->clk_cdev1);
 165 err_put_pll_a_out0:
 166         clk_put(data->clk_pll_a_out0);
 167 err_put_pll_a:
 168         clk_put(data->clk_pll_a);
 169 err:
 170         return ret;
 171 }
 172 EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
 173
 174 void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
 175 {
 176         clk_put(data->clk_cdev1);
 177         clk_put(data->clk_pll_a_out0);
 178         clk_put(data->clk_pll_a);
 179 }
 180 EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
 181
 182 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 183 MODULE_DESCRIPTION("Tegra ASoC utility code");
 184 MODULE_LICENSE("GPL");