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[deliverable/linux.git] / sound / sparc / dbri.c
1 /*
2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
4 *
5 * Based entirely upon drivers/sbus/audio/dbri.c which is:
6 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
7 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
8 *
9 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
10 * on Sun SPARCstation 10, 20, LX and Voyager models.
11 *
12 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
13 * data time multiplexer with ISDN support (aka T7259)
14 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
15 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
16 * Documentation:
17 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
18 * Sparc Technology Business (courtesy of Sun Support)
19 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
20 * available from the Lucent (formarly AT&T microelectronics) home
21 * page.
22 * - http://www.freesoft.org/Linux/DBRI/
23 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
24 * Interfaces: CHI, Audio In & Out, 2 bits parallel
25 * Documentation: from the Crystal Semiconductor home page.
26 *
27 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
28 * memory and a serial device (long pipes, nr 0-15) or between two serial
29 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
30 * device (short pipes).
31 * A timeslot defines the bit-offset and nr of bits read from a serial device.
32 * The timeslots are linked to 6 circular lists, one for each direction for
33 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
34 * (the second one is a monitor/tee pipe, valid only for serial input).
35 *
36 * The mmcodec is connected via the CHI bus and needs the data & some
37 * parameters (volume, output selection) timemultiplexed in 8 byte
38 * chunks. It also has a control mode, which serves for audio format setting.
39 *
40 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
41 * the same CHI bus, so I thought perhaps it is possible to use the onboard
42 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
43 * audio devices. But the SUN HW group decided against it, at least on my
44 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
45 * connected.
46 *
47 * I've tried to stick to the following function naming conventions:
48 * snd_* ALSA stuff
49 * cs4215_* CS4215 codec specific stuff
50 * dbri_* DBRI high-level stuff
51 * other DBRI low-level stuff
52 */
53
54 #include <sound/driver.h>
55 #include <linux/interrupt.h>
56 #include <linux/delay.h>
57
58 #include <sound/core.h>
59 #include <sound/pcm.h>
60 #include <sound/pcm_params.h>
61 #include <sound/info.h>
62 #include <sound/control.h>
63 #include <sound/initval.h>
64
65 #include <asm/irq.h>
66 #include <asm/io.h>
67 #include <asm/sbus.h>
68 #include <asm/atomic.h>
69
70 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
71 MODULE_DESCRIPTION("Sun DBRI");
72 MODULE_LICENSE("GPL");
73 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
74
75 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
78
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
85
86 #define DBRI_DEBUG
87
88 #define D_INT (1<<0)
89 #define D_GEN (1<<1)
90 #define D_CMD (1<<2)
91 #define D_MM (1<<3)
92 #define D_USR (1<<4)
93 #define D_DESC (1<<5)
94
95 static int dbri_debug;
96 module_param(dbri_debug, int, 0644);
97 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
98
99 #ifdef DBRI_DEBUG
100 static char *cmds[] = {
101 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
102 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
103 };
104
105 #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
106
107 #else
108 #define dprintk(a, x...)
109
110 #endif /* DBRI_DEBUG */
111
112 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
113 (intr << 27) | \
114 value)
115
116 /***************************************************************************
117 CS4215 specific definitions and structures
118 ****************************************************************************/
119
120 struct cs4215 {
121 __u8 data[4]; /* Data mode: Time slots 5-8 */
122 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
123 __u8 onboard;
124 __u8 offset; /* Bit offset from frame sync to time slot 1 */
125 volatile __u32 status;
126 volatile __u32 version;
127 __u8 precision; /* In bits, either 8 or 16 */
128 __u8 channels; /* 1 or 2 */
129 };
130
131 /*
132 * Control mode first
133 */
134
135 /* Time Slot 1, Status register */
136 #define CS4215_CLB (1<<2) /* Control Latch Bit */
137 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
138 /* 0: line: 2.8V, speaker 8V */
139 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
140 #define CS4215_RSRVD_1 (1<<5)
141
142 /* Time Slot 2, Data Format Register */
143 #define CS4215_DFR_LINEAR16 0
144 #define CS4215_DFR_ULAW 1
145 #define CS4215_DFR_ALAW 2
146 #define CS4215_DFR_LINEAR8 3
147 #define CS4215_DFR_STEREO (1<<2)
148 static struct {
149 unsigned short freq;
150 unsigned char xtal;
151 unsigned char csval;
152 } CS4215_FREQ[] = {
153 { 8000, (1 << 4), (0 << 3) },
154 { 16000, (1 << 4), (1 << 3) },
155 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
156 { 32000, (1 << 4), (3 << 3) },
157 /* { NA, (1 << 4), (4 << 3) }, */
158 /* { NA, (1 << 4), (5 << 3) }, */
159 { 48000, (1 << 4), (6 << 3) },
160 { 9600, (1 << 4), (7 << 3) },
161 { 5513, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
162 { 11025, (2 << 4), (1 << 3) },
163 { 18900, (2 << 4), (2 << 3) },
164 { 22050, (2 << 4), (3 << 3) },
165 { 37800, (2 << 4), (4 << 3) },
166 { 44100, (2 << 4), (5 << 3) },
167 { 33075, (2 << 4), (6 << 3) },
168 { 6615, (2 << 4), (7 << 3) },
169 { 0, 0, 0}
170 };
171
172 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
173
174 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
175
176 /* Time Slot 3, Serial Port Control register */
177 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
178 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
179 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
180 #define CS4215_BSEL_128 (1<<2)
181 #define CS4215_BSEL_256 (2<<2)
182 #define CS4215_MCK_MAST (0<<4) /* Master clock */
183 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
184 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
185 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
186 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
187
188 /* Time Slot 4, Test Register */
189 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
190 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
191
192 /* Time Slot 5, Parallel Port Register */
193 /* Read only here and the same as the in data mode */
194
195 /* Time Slot 6, Reserved */
196
197 /* Time Slot 7, Version Register */
198 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
199
200 /* Time Slot 8, Reserved */
201
202 /*
203 * Data mode
204 */
205 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
206
207 /* Time Slot 5, Output Setting */
208 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
209 #define CS4215_LE (1<<6) /* Line Out Enable */
210 #define CS4215_HE (1<<7) /* Headphone Enable */
211
212 /* Time Slot 6, Output Setting */
213 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
214 #define CS4215_SE (1<<6) /* Speaker Enable */
215 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
216
217 /* Time Slot 7, Input Setting */
218 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
219 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
220 #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
221 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
222 #define CS4215_PIO1 (1<<7)
223
224 /* Time Slot 8, Input Setting */
225 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
226 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
227
228 /***************************************************************************
229 DBRI specific definitions and structures
230 ****************************************************************************/
231
232 /* DBRI main registers */
233 #define REG0 0x00UL /* Status and Control */
234 #define REG1 0x04UL /* Mode and Interrupt */
235 #define REG2 0x08UL /* Parallel IO */
236 #define REG3 0x0cUL /* Test */
237 #define REG8 0x20UL /* Command Queue Pointer */
238 #define REG9 0x24UL /* Interrupt Queue Pointer */
239
240 #define DBRI_NO_CMDS 64
241 #define DBRI_INT_BLK 64
242 #define DBRI_NO_DESCS 64
243 #define DBRI_NO_PIPES 32
244 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
245
246 #define DBRI_REC 0
247 #define DBRI_PLAY 1
248 #define DBRI_NO_STREAMS 2
249
250 /* One transmit/receive descriptor */
251 /* When ba != 0 descriptor is used */
252 struct dbri_mem {
253 volatile __u32 word1;
254 __u32 ba; /* Transmit/Receive Buffer Address */
255 __u32 nda; /* Next Descriptor Address */
256 volatile __u32 word4;
257 };
258
259 /* This structure is in a DMA region where it can accessed by both
260 * the CPU and the DBRI
261 */
262 struct dbri_dma {
263 volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
264 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
265 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
266 };
267
268 #define dbri_dma_off(member, elem) \
269 ((u32)(unsigned long) \
270 (&(((struct dbri_dma *)0)->member[elem])))
271
272 enum in_or_out { PIPEinput, PIPEoutput };
273
274 struct dbri_pipe {
275 u32 sdp; /* SDP command word */
276 int nextpipe; /* Next pipe in linked list */
277 int cycle; /* Offset of timeslot (bits) */
278 int length; /* Length of timeslot (bits) */
279 int first_desc; /* Index of first descriptor */
280 int desc; /* Index of active descriptor */
281 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
282 };
283
284 /* Per stream (playback or record) information */
285 struct dbri_streaminfo {
286 struct snd_pcm_substream *substream;
287 u32 dvma_buffer; /* Device view of Alsa DMA buffer */
288 int left; /* # of bytes left in DMA buffer */
289 int size; /* Size of DMA buffer */
290 size_t offset; /* offset in user buffer */
291 int pipe; /* Data pipe used */
292 int left_gain; /* mixer elements */
293 int right_gain;
294 };
295
296 /* This structure holds the information for both chips (DBRI & CS4215) */
297 struct snd_dbri {
298 struct snd_card *card; /* ALSA card */
299
300 int regs_size, irq; /* Needed for unload */
301 struct sbus_dev *sdev; /* SBUS device info */
302 spinlock_t lock;
303
304 struct dbri_dma *dma; /* Pointer to our DMA block */
305 u32 dma_dvma; /* DBRI visible DMA address */
306
307 void __iomem *regs; /* dbri HW regs */
308 int dbri_irqp; /* intr queue pointer */
309 int wait_send; /* sequence of command buffers send */
310 int wait_ackd; /* sequence of command buffers acknowledged */
311
312 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
313 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
314
315 int chi_in_pipe;
316 int chi_out_pipe;
317 int chi_bpf;
318
319 struct cs4215 mm; /* mmcodec special info */
320 /* per stream (playback/record) info */
321 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
322
323 struct snd_dbri *next;
324 };
325
326 #define DBRI_MAX_VOLUME 63 /* Output volume */
327 #define DBRI_MAX_GAIN 15 /* Input gain */
328
329 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
330 #define D_P (1<<15) /* Program command & queue pointer valid */
331 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
332 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
333 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
334 #define D_X (1<<7) /* Sanity Timer Disable */
335 #define D_T (1<<6) /* Permit activation of the TE interface */
336 #define D_N (1<<5) /* Permit activation of the NT interface */
337 #define D_C (1<<4) /* Permit activation of the CHI interface */
338 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
339 #define D_D (1<<2) /* Disable Master Mode */
340 #define D_H (1<<1) /* Halt for Analysis */
341 #define D_R (1<<0) /* Soft Reset */
342
343 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
344 #define D_LITTLE_END (1<<8) /* Byte Order */
345 #define D_BIG_END (0<<8) /* Byte Order */
346 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */
347 #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */
348 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */
349 #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */
350 #define D_IR (1<<0) /* Interrupt Indicator (readonly) */
351
352 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
353 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
354 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
355 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
356 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
357 #define D_ENPIO (0xf0) /* Enable all the pins */
358 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
359 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
360 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
361 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
362
363 /* DBRI Commands (Page 20) */
364 #define D_WAIT 0x0 /* Stop execution */
365 #define D_PAUSE 0x1 /* Flush long pipes */
366 #define D_JUMP 0x2 /* New command queue */
367 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
368 #define D_REX 0x4 /* Report command execution via interrupt */
369 #define D_SDP 0x5 /* Setup Data Pipe */
370 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
371 #define D_DTS 0x7 /* Define Time Slot */
372 #define D_SSP 0x8 /* Set short Data Pipe */
373 #define D_CHI 0x9 /* Set CHI Global Mode */
374 #define D_NT 0xa /* NT Command */
375 #define D_TE 0xb /* TE Command */
376 #define D_CDEC 0xc /* Codec setup */
377 #define D_TEST 0xd /* No comment */
378 #define D_CDM 0xe /* CHI Data mode command */
379
380 /* Special bits for some commands */
381 #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
382
383 /* Setup Data Pipe */
384 /* IRM */
385 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */
386 #define D_SDP_CHANGE (2<<18) /* Report any changes */
387 #define D_SDP_EVERY (3<<18) /* Report any changes */
388 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
389 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
390
391 /* Pipe data MODE */
392 #define D_SDP_MEM (0<<13) /* To/from memory */
393 #define D_SDP_HDLC (2<<13)
394 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
395 #define D_SDP_SER (4<<13) /* Serial to serial */
396 #define D_SDP_FIXED (6<<13) /* Short only */
397 #define D_SDP_MODE(v) ((v)&(7<<13))
398
399 #define D_SDP_TO_SER (1<<12) /* Direction */
400 #define D_SDP_FROM_SER (0<<12) /* Direction */
401 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
402 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
403 #define D_SDP_P (1<<10) /* Pointer Valid */
404 #define D_SDP_A (1<<8) /* Abort */
405 #define D_SDP_C (1<<7) /* Clear */
406
407 /* Define Time Slot */
408 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
409 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
410 #define D_DTS_INS (1<<15) /* Insert Time Slot */
411 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
412 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
413 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
414
415 /* Time Slot defines */
416 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
417 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
418 #define D_TS_DI (1<<13) /* Data Invert */
419 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
420 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
421 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
422 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
423 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
424 #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
425
426 /* Concentration Highway Interface Modes */
427 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
428 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
429 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
430 #define D_CHI_OD (1<<13) /* Open Drain Enable */
431 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
432 #define D_CHI_FD (1<<11) /* Frame Drive */
433 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
434
435 /* NT: These are here for completeness */
436 #define D_NT_FBIT (1<<17) /* Frame Bit */
437 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
438 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
439 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
440 #define D_NT_ISNT (1<<13) /* Configfure interface as NT */
441 #define D_NT_FT (1<<12) /* Fixed Timing */
442 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
443 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
444 #define D_NT_ACT (1<<9) /* Activate Interface */
445 #define D_NT_MFE (1<<8) /* Multiframe Enable */
446 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
447 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
448 #define D_NT_FACT (1<<1) /* Force Activation */
449 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
450
451 /* Codec Setup */
452 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
453 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
454 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
455
456 /* Test */
457 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
458 #define D_TEST_SIZE(v) ((v)<<11) /* */
459 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
460 #define D_TEST_PROC 0x6 /* MicroProcessor test */
461 #define D_TEST_SER 0x7 /* Serial-Controller test */
462 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
463 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
464 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
465 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
466 #define D_TEST_DUMP 0xe /* ROM Dump */
467
468 /* CHI Data Mode */
469 #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */
470 #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */
471 #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */
472 #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */
473 #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */
474 #define D_CDM_REN (1<<0) /* Receive Highway Enable */
475
476 /* The Interrupts */
477 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
478 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
479 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
480 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
481 #define D_INTR_EOL 5 /* End of List */
482 #define D_INTR_CMDI 6 /* Command has bean read */
483 #define D_INTR_XCMP 8 /* Transmission of frame complete */
484 #define D_INTR_SBRI 9 /* BRI status change info */
485 #define D_INTR_FXDT 10 /* Fixed data change */
486 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
487 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
488 #define D_INTR_DBYT 12 /* Dropped by frame slip */
489 #define D_INTR_RBYT 13 /* Repeated by frame slip */
490 #define D_INTR_LINT 14 /* Lost Interrupt */
491 #define D_INTR_UNDR 15 /* DMA underrun */
492
493 #define D_INTR_TE 32
494 #define D_INTR_NT 34
495 #define D_INTR_CHI 36
496 #define D_INTR_CMD 38
497
498 #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f)
499 #define D_INTR_GETCODE(v) (((v)>>20) & 0xf)
500 #define D_INTR_GETCMD(v) (((v)>>16) & 0xf)
501 #define D_INTR_GETVAL(v) ((v) & 0xffff)
502 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
503
504 #define D_P_0 0 /* TE receive anchor */
505 #define D_P_1 1 /* TE transmit anchor */
506 #define D_P_2 2 /* NT transmit anchor */
507 #define D_P_3 3 /* NT receive anchor */
508 #define D_P_4 4 /* CHI send data */
509 #define D_P_5 5 /* CHI receive data */
510 #define D_P_6 6 /* */
511 #define D_P_7 7 /* */
512 #define D_P_8 8 /* */
513 #define D_P_9 9 /* */
514 #define D_P_10 10 /* */
515 #define D_P_11 11 /* */
516 #define D_P_12 12 /* */
517 #define D_P_13 13 /* */
518 #define D_P_14 14 /* */
519 #define D_P_15 15 /* */
520 #define D_P_16 16 /* CHI anchor pipe */
521 #define D_P_17 17 /* CHI send */
522 #define D_P_18 18 /* CHI receive */
523 #define D_P_19 19 /* CHI receive */
524 #define D_P_20 20 /* CHI receive */
525 #define D_P_21 21 /* */
526 #define D_P_22 22 /* */
527 #define D_P_23 23 /* */
528 #define D_P_24 24 /* */
529 #define D_P_25 25 /* */
530 #define D_P_26 26 /* */
531 #define D_P_27 27 /* */
532 #define D_P_28 28 /* */
533 #define D_P_29 29 /* */
534 #define D_P_30 30 /* */
535 #define D_P_31 31 /* */
536
537 /* Transmit descriptor defines */
538 #define DBRI_TD_F (1<<31) /* End of Frame */
539 #define DBRI_TD_D (1<<30) /* Do not append CRC */
540 #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */
541 #define DBRI_TD_B (1<<15) /* Final interrupt */
542 #define DBRI_TD_M (1<<14) /* Marker interrupt */
543 #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */
544 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
545 #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */
546 #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */
547 #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */
548 #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */
549 /* Maximum buffer size per TD: almost 8Kb */
550 #define DBRI_TD_MAXCNT ((1 << 13) - 1)
551
552 /* Receive descriptor defines */
553 #define DBRI_RD_F (1<<31) /* End of Frame */
554 #define DBRI_RD_C (1<<30) /* Completed buffer */
555 #define DBRI_RD_B (1<<15) /* Final interrupt */
556 #define DBRI_RD_M (1<<14) /* Marker interrupt */
557 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
558 #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */
559 #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */
560 #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */
561 #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */
562 #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */
563 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */
564
565 /* stream_info[] access */
566 /* Translate the ALSA direction into the array index */
567 #define DBRI_STREAMNO(substream) \
568 (substream->stream == \
569 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
570
571 /* Return a pointer to dbri_streaminfo */
572 #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]
573
574 static struct snd_dbri *dbri_list; /* All DBRI devices */
575
576 /*
577 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
578 * So we have to reverse the bits. Note: not all bit lengths are supported
579 */
580 static __u32 reverse_bytes(__u32 b, int len)
581 {
582 switch (len) {
583 case 32:
584 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
585 case 16:
586 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
587 case 8:
588 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
589 case 4:
590 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
591 case 2:
592 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
593 case 1:
594 case 0:
595 break;
596 default:
597 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
598 };
599
600 return b;
601 }
602
603 /*
604 ****************************************************************************
605 ************** DBRI initialization and command synchronization *************
606 ****************************************************************************
607
608 Commands are sent to the DBRI by building a list of them in memory,
609 then writing the address of the first list item to DBRI register 8.
610 The list is terminated with a WAIT command, which generates a
611 CPU interrupt to signal completion.
612
613 Since the DBRI can run in parallel with the CPU, several means of
614 synchronization present themselves. The method implemented here is close
615 to the original scheme (Rudolf's), and uses 2 counters (wait_send and
616 wait_ackd) to synchronize the command buffer between the CPU and the DBRI.
617
618 A more sophisticated scheme might involve a circular command buffer
619 or an array of command buffers. A routine could fill one with
620 commands and link it onto a list. When a interrupt signaled
621 completion of the current command buffer, look on the list for
622 the next one.
623
624 Every time a routine wants to write commands to the DBRI, it must
625 first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
626 in return. dbri_cmdlock() will block if the previous commands have not
627 been completed yet. After this the commands can be written to the buffer,
628 and dbri_cmdsend() is called with the final pointer value to send them
629 to the DBRI.
630
631 */
632
633 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri);
634
635 enum dbri_lock { NoGetLock, GetLock };
636 #define MAXLOOPS 10
637
638 static volatile s32 *dbri_cmdlock(struct snd_dbri * dbri, enum dbri_lock get)
639 {
640 int maxloops = MAXLOOPS;
641
642 #ifndef SMP
643 if ((get == GetLock) && spin_is_locked(&dbri->lock)) {
644 printk(KERN_ERR "DBRI: cmdlock called while in spinlock.");
645 }
646 #endif
647
648 /* Delay if previous commands are still being processed */
649 while ((--maxloops) > 0 && (dbri->wait_send != dbri->wait_ackd)) {
650 msleep_interruptible(1);
651 }
652 if (maxloops == 0) {
653 printk(KERN_ERR "DBRI: Chip never completed command buffer %d\n",
654 dbri->wait_send);
655 } else {
656 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
657 MAXLOOPS - maxloops - 1);
658 }
659
660 /*if (get == GetLock) spin_lock(&dbri->lock); */
661 return &dbri->dma->cmd[0];
662 }
663
664 static void dbri_cmdsend(struct snd_dbri * dbri, volatile s32 * cmd)
665 {
666 volatile s32 *ptr;
667
668 for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
669 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
670 }
671
672 if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) {
673 printk(KERN_ERR "DBRI: Command buffer overflow! (bug in driver)\n");
674 /* Ignore the last part. */
675 cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3];
676 }
677
678 dbri->wait_send++;
679 dbri->wait_send &= 0xffff; /* restrict it to a 16 bit counter. */
680 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
681 *(cmd++) = DBRI_CMD(D_WAIT, 1, dbri->wait_send);
682
683 /* Set command pointer and signal it is valid. */
684 sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
685
686 /*spin_unlock(&dbri->lock); */
687 }
688
689 /* Lock must be held when calling this */
690 static void dbri_reset(struct snd_dbri * dbri)
691 {
692 int i;
693 u32 tmp;
694
695 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
696 sbus_readl(dbri->regs + REG0),
697 sbus_readl(dbri->regs + REG2),
698 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
699
700 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
701 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
702 udelay(10);
703
704 /* A brute approach - DBRI falls back to working burst size by itself
705 * On SS20 D_S does not work, so do not try so high. */
706 tmp = sbus_readl(dbri->regs + REG0);
707 tmp |= D_G | D_E;
708 tmp &= ~D_S;
709 sbus_writel(tmp, dbri->regs + REG0);
710 }
711
712 /* Lock must not be held before calling this */
713 static void dbri_initialize(struct snd_dbri * dbri)
714 {
715 volatile s32 *cmd;
716 u32 dma_addr;
717 unsigned long flags;
718 int n;
719
720 spin_lock_irqsave(&dbri->lock, flags);
721
722 dbri_reset(dbri);
723
724 cmd = dbri_cmdlock(dbri, NoGetLock);
725 dprintk(D_GEN, "init: cmd: %p, int: %p\n",
726 &dbri->dma->cmd[0], &dbri->dma->intr[0]);
727
728 /* Initialize pipes */
729 for (n = 0; n < DBRI_NO_PIPES; n++)
730 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
731
732 /*
733 * Initialize the interrupt ringbuffer.
734 */
735 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
736 dbri->dma->intr[0] = dma_addr;
737 dbri->dbri_irqp = 1;
738 /*
739 * Set up the interrupt queue
740 */
741 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
742 *(cmd++) = dma_addr;
743
744 dbri_cmdsend(dbri, cmd);
745 spin_unlock_irqrestore(&dbri->lock, flags);
746 }
747
748 /*
749 ****************************************************************************
750 ************************** DBRI data pipe management ***********************
751 ****************************************************************************
752
753 While DBRI control functions use the command and interrupt buffers, the
754 main data path takes the form of data pipes, which can be short (command
755 and interrupt driven), or long (attached to DMA buffers). These functions
756 provide a rudimentary means of setting up and managing the DBRI's pipes,
757 but the calling functions have to make sure they respect the pipes' linked
758 list ordering, among other things. The transmit and receive functions
759 here interface closely with the transmit and receive interrupt code.
760
761 */
762 static int pipe_active(struct snd_dbri * dbri, int pipe)
763 {
764 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
765 }
766
767 /* reset_pipe(dbri, pipe)
768 *
769 * Called on an in-use pipe to clear anything being transmitted or received
770 * Lock must be held before calling this.
771 */
772 static void reset_pipe(struct snd_dbri * dbri, int pipe)
773 {
774 int sdp;
775 int desc;
776 volatile int *cmd;
777
778 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
779 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n");
780 return;
781 }
782
783 sdp = dbri->pipes[pipe].sdp;
784 if (sdp == 0) {
785 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n");
786 return;
787 }
788
789 cmd = dbri_cmdlock(dbri, NoGetLock);
790 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
791 *(cmd++) = 0;
792 dbri_cmdsend(dbri, cmd);
793
794 desc = dbri->pipes[pipe].first_desc;
795 while (desc != -1) {
796 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0;
797 desc = dbri->next_desc[desc];
798 }
799
800 dbri->pipes[pipe].desc = -1;
801 dbri->pipes[pipe].first_desc = -1;
802 }
803
804 static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
805 {
806 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
807 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n");
808 return;
809 }
810
811 if ((sdp & 0xf800) != sdp) {
812 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n");
813 /* sdp &= 0xf800; */
814 }
815
816 /* If this is a fixed receive pipe, arrange for an interrupt
817 * every time its data changes
818 */
819 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
820 sdp |= D_SDP_CHANGE;
821
822 sdp |= D_PIPE(pipe);
823 dbri->pipes[pipe].sdp = sdp;
824 dbri->pipes[pipe].desc = -1;
825 dbri->pipes[pipe].first_desc = -1;
826
827 reset_pipe(dbri, pipe);
828 }
829
830 /* FIXME: direction not needed */
831 static void link_time_slot(struct snd_dbri * dbri, int pipe,
832 enum in_or_out direction, int basepipe,
833 int length, int cycle)
834 {
835 volatile s32 *cmd;
836 int val;
837 int prevpipe;
838 int nextpipe;
839
840 if (pipe < 0 || pipe > DBRI_MAX_PIPE || basepipe < 0 || basepipe > DBRI_MAX_PIPE) {
841 printk(KERN_ERR
842 "DBRI: link_time_slot called with illegal pipe number\n");
843 return;
844 }
845
846 if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
847 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
848 return;
849 }
850
851 /* Deal with CHI special case:
852 * "If transmission on edges 0 or 1 is desired, then cycle n
853 * (where n = # of bit times per frame...) must be used."
854 * - DBRI data sheet, page 11
855 */
856 if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
857 cycle = dbri->chi_bpf;
858
859 if (basepipe == pipe) {
860 prevpipe = pipe;
861 nextpipe = pipe;
862 } else {
863 /* We're not initializing a new linked list (basepipe != pipe),
864 * so run through the linked list and find where this pipe
865 * should be sloted in, based on its cycle. CHI confuses
866 * things a bit, since it has a single anchor for both its
867 * transmit and receive lists.
868 */
869 if (basepipe == 16) {
870 if (direction == PIPEinput) {
871 prevpipe = dbri->chi_in_pipe;
872 } else {
873 prevpipe = dbri->chi_out_pipe;
874 }
875 } else {
876 prevpipe = basepipe;
877 }
878
879 nextpipe = dbri->pipes[prevpipe].nextpipe;
880
881 while (dbri->pipes[nextpipe].cycle < cycle
882 && dbri->pipes[nextpipe].nextpipe != basepipe) {
883 prevpipe = nextpipe;
884 nextpipe = dbri->pipes[nextpipe].nextpipe;
885 }
886 }
887
888 if (prevpipe == 16) {
889 if (direction == PIPEinput) {
890 dbri->chi_in_pipe = pipe;
891 } else {
892 dbri->chi_out_pipe = pipe;
893 }
894 } else {
895 dbri->pipes[prevpipe].nextpipe = pipe;
896 }
897
898 dbri->pipes[pipe].nextpipe = nextpipe;
899 dbri->pipes[pipe].cycle = cycle;
900 dbri->pipes[pipe].length = length;
901
902 cmd = dbri_cmdlock(dbri, NoGetLock);
903
904 if (direction == PIPEinput) {
905 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
906 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
907 *(cmd++) =
908 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
909 *(cmd++) = 0;
910 } else {
911 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
912 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
913 *(cmd++) = 0;
914 *(cmd++) =
915 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
916 }
917
918 dbri_cmdsend(dbri, cmd);
919 }
920
921 static void unlink_time_slot(struct snd_dbri * dbri, int pipe,
922 enum in_or_out direction, int prevpipe,
923 int nextpipe)
924 {
925 volatile s32 *cmd;
926 int val;
927
928 if (pipe < 0 || pipe > DBRI_MAX_PIPE
929 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE) {
930 printk(KERN_ERR
931 "DBRI: unlink_time_slot called with illegal pipe number\n");
932 return;
933 }
934
935 cmd = dbri_cmdlock(dbri, NoGetLock);
936
937 if (direction == PIPEinput) {
938 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
939 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
940 *(cmd++) = D_TS_NEXT(nextpipe);
941 *(cmd++) = 0;
942 } else {
943 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
944 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
945 *(cmd++) = 0;
946 *(cmd++) = D_TS_NEXT(nextpipe);
947 }
948
949 dbri_cmdsend(dbri, cmd);
950 }
951
952 /* xmit_fixed() / recv_fixed()
953 *
954 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
955 * expected to change much, and which we don't need to buffer.
956 * The DBRI only interrupts us when the data changes (receive pipes),
957 * or only changes the data when this function is called (transmit pipes).
958 * Only short pipes (numbers 16-31) can be used in fixed data mode.
959 *
960 * These function operate on a 32-bit field, no matter how large
961 * the actual time slot is. The interrupt handler takes care of bit
962 * ordering and alignment. An 8-bit time slot will always end up
963 * in the low-order 8 bits, filled either MSB-first or LSB-first,
964 * depending on the settings passed to setup_pipe()
965 */
966 static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data)
967 {
968 volatile s32 *cmd;
969
970 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
971 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
972 return;
973 }
974
975 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
976 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
977 return;
978 }
979
980 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
981 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
982 return;
983 }
984
985 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
986 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
987 return;
988 }
989
990 /* DBRI short pipes always transmit LSB first */
991
992 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
993 data = reverse_bytes(data, dbri->pipes[pipe].length);
994
995 cmd = dbri_cmdlock(dbri, GetLock);
996
997 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
998 *(cmd++) = data;
999
1000 dbri_cmdsend(dbri, cmd);
1001 }
1002
1003 static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr)
1004 {
1005 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1006 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n");
1007 return;
1008 }
1009
1010 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1011 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
1012 return;
1013 }
1014
1015 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1016 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe);
1017 return;
1018 }
1019
1020 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1021 }
1022
1023 /* setup_descs()
1024 *
1025 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1026 * with a DMA buffer.
1027 *
1028 * Only pipe numbers 0-15 can be used in this mode.
1029 *
1030 * This function takes a stream number pointing to a data buffer,
1031 * and work by building chains of descriptors which identify the
1032 * data buffers. Buffers too large for a single descriptor will
1033 * be spread across multiple descriptors.
1034 */
1035 static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period)
1036 {
1037 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1038 __u32 dvma_buffer;
1039 int desc = 0;
1040 int len;
1041 int first_desc = -1;
1042 int last_desc = -1;
1043
1044 if (info->pipe < 0 || info->pipe > 15) {
1045 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1046 return -2;
1047 }
1048
1049 if (dbri->pipes[info->pipe].sdp == 0) {
1050 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1051 info->pipe);
1052 return -2;
1053 }
1054
1055 dvma_buffer = info->dvma_buffer;
1056 len = info->size;
1057
1058 if (streamno == DBRI_PLAY) {
1059 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1060 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n",
1061 info->pipe);
1062 return -2;
1063 }
1064 } else {
1065 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1066 printk(KERN_ERR
1067 "DBRI: setup_descs: Called on transmit pipe %d\n",
1068 info->pipe);
1069 return -2;
1070 }
1071 /* Should be able to queue multiple buffers to receive on a pipe */
1072 if (pipe_active(dbri, info->pipe)) {
1073 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n",
1074 info->pipe);
1075 return -2;
1076 }
1077
1078 /* Make sure buffer size is multiple of four */
1079 len &= ~3;
1080 }
1081
1082 while (len > 0) {
1083 int mylen;
1084
1085 for (; desc < DBRI_NO_DESCS; desc++) {
1086 if (!dbri->dma->desc[desc].ba)
1087 break;
1088 }
1089 if (desc == DBRI_NO_DESCS) {
1090 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1091 return -1;
1092 }
1093
1094 if (len > DBRI_TD_MAXCNT) {
1095 mylen = DBRI_TD_MAXCNT; /* 8KB - 1 */
1096 } else {
1097 mylen = len;
1098 }
1099 if (mylen > period) {
1100 mylen = period;
1101 }
1102
1103 dbri->next_desc[desc] = -1;
1104 dbri->dma->desc[desc].ba = dvma_buffer;
1105 dbri->dma->desc[desc].nda = 0;
1106
1107 if (streamno == DBRI_PLAY) {
1108 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1109 dbri->dma->desc[desc].word4 = 0;
1110 if (first_desc != -1)
1111 dbri->dma->desc[desc].word1 |= DBRI_TD_M;
1112 } else {
1113 dbri->dma->desc[desc].word1 = 0;
1114 dbri->dma->desc[desc].word4 =
1115 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1116 }
1117
1118 if (first_desc == -1) {
1119 first_desc = desc;
1120 } else {
1121 dbri->next_desc[last_desc] = desc;
1122 dbri->dma->desc[last_desc].nda =
1123 dbri->dma_dvma + dbri_dma_off(desc, desc);
1124 }
1125
1126 last_desc = desc;
1127 dvma_buffer += mylen;
1128 len -= mylen;
1129 }
1130
1131 if (first_desc == -1 || last_desc == -1) {
1132 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n");
1133 return -1;
1134 }
1135
1136 dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M;
1137 if (streamno == DBRI_PLAY) {
1138 dbri->dma->desc[last_desc].word1 |=
1139 DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
1140 }
1141 dbri->pipes[info->pipe].first_desc = first_desc;
1142 dbri->pipes[info->pipe].desc = first_desc;
1143
1144 for (desc = first_desc; desc != -1; desc = dbri->next_desc[desc]) {
1145 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1146 desc,
1147 dbri->dma->desc[desc].word1,
1148 dbri->dma->desc[desc].ba,
1149 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1150 }
1151 return 0;
1152 }
1153
1154 /*
1155 ****************************************************************************
1156 ************************** DBRI - CHI interface ****************************
1157 ****************************************************************************
1158
1159 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1160 multiplexed serial interface which the DBRI can operate in either master
1161 (give clock/frame sync) or slave (take clock/frame sync) mode.
1162
1163 */
1164
1165 enum master_or_slave { CHImaster, CHIslave };
1166
1167 static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave,
1168 int bits_per_frame)
1169 {
1170 volatile s32 *cmd;
1171 int val;
1172 static int chi_initialized = 0; /* FIXME: mutex? */
1173
1174 if (!chi_initialized) {
1175
1176 cmd = dbri_cmdlock(dbri, GetLock);
1177
1178 /* Set CHI Anchor: Pipe 16 */
1179
1180 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1181 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1182 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1183 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1184 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1185
1186 dbri->pipes[16].sdp = 1;
1187 dbri->pipes[16].nextpipe = 16;
1188
1189 #if 0
1190 chi_initialized++;
1191 #endif
1192 } else {
1193 int pipe;
1194
1195 for (pipe = dbri->chi_in_pipe;
1196 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
1197 unlink_time_slot(dbri, pipe, PIPEinput,
1198 16, dbri->pipes[pipe].nextpipe);
1199 }
1200 for (pipe = dbri->chi_out_pipe;
1201 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
1202 unlink_time_slot(dbri, pipe, PIPEoutput,
1203 16, dbri->pipes[pipe].nextpipe);
1204 }
1205
1206 cmd = dbri_cmdlock(dbri, GetLock);
1207 }
1208 dbri->chi_in_pipe = 16;
1209 dbri->chi_out_pipe = 16;
1210
1211 if (master_or_slave == CHIslave) {
1212 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1213 *
1214 * CHICM = 0 (slave mode, 8 kHz frame rate)
1215 * IR = give immediate CHI status interrupt
1216 * EN = give CHI status interrupt upon change
1217 */
1218 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1219 } else {
1220 /* Setup DBRI for CHI Master - generate clock, FS
1221 *
1222 * BPF = bits per 8 kHz frame
1223 * 12.288 MHz / CHICM_divisor = clock rate
1224 * FD = 1 - drive CHIFS on rising edge of CHICK
1225 */
1226 int clockrate = bits_per_frame * 8;
1227 int divisor = 12288 / clockrate;
1228
1229 if (divisor > 255 || divisor * clockrate != 12288)
1230 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n");
1231
1232 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1233 | D_CHI_BPF(bits_per_frame));
1234 }
1235
1236 dbri->chi_bpf = bits_per_frame;
1237
1238 /* CHI Data Mode
1239 *
1240 * RCE = 0 - receive on falling edge of CHICK
1241 * XCE = 1 - transmit on rising edge of CHICK
1242 * XEN = 1 - enable transmitter
1243 * REN = 1 - enable receiver
1244 */
1245
1246 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1247 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1248
1249 dbri_cmdsend(dbri, cmd);
1250 }
1251
1252 /*
1253 ****************************************************************************
1254 *********************** CS4215 audio codec management **********************
1255 ****************************************************************************
1256
1257 In the standard SPARC audio configuration, the CS4215 codec is attached
1258 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1259
1260 */
1261 static void cs4215_setup_pipes(struct snd_dbri * dbri)
1262 {
1263 /*
1264 * Data mode:
1265 * Pipe 4: Send timeslots 1-4 (audio data)
1266 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1267 * Pipe 6: Receive timeslots 1-4 (audio data)
1268 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1269 * interrupt, and the rest of the data (slot 5 and 8) is
1270 * not relevant for us (only for doublechecking).
1271 *
1272 * Control mode:
1273 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1274 * Pipe 18: Receive timeslot 1 (clb).
1275 * Pipe 19: Receive timeslot 7 (version).
1276 */
1277
1278 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1279 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1280 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1281 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1282
1283 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1284 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1285 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1286 }
1287
1288 static int cs4215_init_data(struct cs4215 *mm)
1289 {
1290 /*
1291 * No action, memory resetting only.
1292 *
1293 * Data Time Slot 5-8
1294 * Speaker,Line and Headphone enable. Gain set to the half.
1295 * Input is mike.
1296 */
1297 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1298 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1299 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1300 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1301
1302 /*
1303 * Control Time Slot 1-4
1304 * 0: Default I/O voltage scale
1305 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1306 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1307 * 3: Tests disabled
1308 */
1309 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1310 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1311 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1312 mm->ctrl[3] = 0;
1313
1314 mm->status = 0;
1315 mm->version = 0xff;
1316 mm->precision = 8; /* For ULAW */
1317 mm->channels = 2;
1318
1319 return 0;
1320 }
1321
1322 static void cs4215_setdata(struct snd_dbri * dbri, int muted)
1323 {
1324 if (muted) {
1325 dbri->mm.data[0] |= 63;
1326 dbri->mm.data[1] |= 63;
1327 dbri->mm.data[2] &= ~15;
1328 dbri->mm.data[3] &= ~15;
1329 } else {
1330 /* Start by setting the playback attenuation. */
1331 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1332 int left_gain = info->left_gain & 0x3f;
1333 int right_gain = info->right_gain & 0x3f;
1334
1335 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1336 dbri->mm.data[1] &= ~0x3f;
1337 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1338 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1339
1340 /* Now set the recording gain. */
1341 info = &dbri->stream_info[DBRI_REC];
1342 left_gain = info->left_gain & 0xf;
1343 right_gain = info->right_gain & 0xf;
1344 dbri->mm.data[2] |= CS4215_LG(left_gain);
1345 dbri->mm.data[3] |= CS4215_RG(right_gain);
1346 }
1347
1348 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1349 }
1350
1351 /*
1352 * Set the CS4215 to data mode.
1353 */
1354 static void cs4215_open(struct snd_dbri * dbri)
1355 {
1356 int data_width;
1357 u32 tmp;
1358
1359 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1360 dbri->mm.channels, dbri->mm.precision);
1361
1362 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1363 * to make sure this takes. This avoids clicking noises.
1364 */
1365
1366 cs4215_setdata(dbri, 1);
1367 udelay(125);
1368
1369 /*
1370 * Data mode:
1371 * Pipe 4: Send timeslots 1-4 (audio data)
1372 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1373 * Pipe 6: Receive timeslots 1-4 (audio data)
1374 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1375 * interrupt, and the rest of the data (slot 5 and 8) is
1376 * not relevant for us (only for doublechecking).
1377 *
1378 * Just like in control mode, the time slots are all offset by eight
1379 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1380 * even if it's the CHI master. Don't ask me...
1381 */
1382 tmp = sbus_readl(dbri->regs + REG0);
1383 tmp &= ~(D_C); /* Disable CHI */
1384 sbus_writel(tmp, dbri->regs + REG0);
1385
1386 /* Switch CS4215 to data mode - set PIO3 to 1 */
1387 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1388 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1389
1390 reset_chi(dbri, CHIslave, 128);
1391
1392 /* Note: this next doesn't work for 8-bit stereo, because the two
1393 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1394 * (See CS4215 datasheet Fig 15)
1395 *
1396 * DBRI non-contiguous mode would be required to make this work.
1397 */
1398 data_width = dbri->mm.channels * dbri->mm.precision;
1399
1400 link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32);
1401 link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset);
1402 link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset);
1403 link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40);
1404
1405 /* FIXME: enable CHI after _setdata? */
1406 tmp = sbus_readl(dbri->regs + REG0);
1407 tmp |= D_C; /* Enable CHI */
1408 sbus_writel(tmp, dbri->regs + REG0);
1409
1410 cs4215_setdata(dbri, 0);
1411 }
1412
1413 /*
1414 * Send the control information (i.e. audio format)
1415 */
1416 static int cs4215_setctrl(struct snd_dbri * dbri)
1417 {
1418 int i, val;
1419 u32 tmp;
1420
1421 /* FIXME - let the CPU do something useful during these delays */
1422
1423 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1424 * to make sure this takes. This avoids clicking noises.
1425 */
1426 cs4215_setdata(dbri, 1);
1427 udelay(125);
1428
1429 /*
1430 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1431 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1432 */
1433 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1434 sbus_writel(val, dbri->regs + REG2);
1435 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1436 udelay(34);
1437
1438 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1439 * operate as CHI master, supplying clocking and frame synchronization.
1440 *
1441 * In Data mode, however, the CS4215 must be CHI master to insure
1442 * that its data stream is synchronous with its codec.
1443 *
1444 * The upshot of all this? We start by putting the DBRI into master
1445 * mode, program the CS4215 in Control mode, then switch the CS4215
1446 * into Data mode and put the DBRI into slave mode. Various timing
1447 * requirements must be observed along the way.
1448 *
1449 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1450 * others?), the addressing of the CS4215's time slots is
1451 * offset by eight bits, so we add eight to all the "cycle"
1452 * values in the Define Time Slot (DTS) commands. This is
1453 * done in hardware by a TI 248 that delays the DBRI->4215
1454 * frame sync signal by eight clock cycles. Anybody know why?
1455 */
1456 tmp = sbus_readl(dbri->regs + REG0);
1457 tmp &= ~D_C; /* Disable CHI */
1458 sbus_writel(tmp, dbri->regs + REG0);
1459
1460 reset_chi(dbri, CHImaster, 128);
1461
1462 /*
1463 * Control mode:
1464 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1465 * Pipe 18: Receive timeslot 1 (clb).
1466 * Pipe 19: Receive timeslot 7 (version).
1467 */
1468
1469 link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset);
1470 link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset);
1471 link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48);
1472
1473 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1474 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1475 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1476
1477 tmp = sbus_readl(dbri->regs + REG0);
1478 tmp |= D_C; /* Enable CHI */
1479 sbus_writel(tmp, dbri->regs + REG0);
1480
1481 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) {
1482 msleep_interruptible(1);
1483 }
1484 if (i == 0) {
1485 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1486 dbri->mm.status);
1487 return -1;
1488 }
1489
1490 /* Disable changes to our copy of the version number, as we are about
1491 * to leave control mode.
1492 */
1493 recv_fixed(dbri, 19, NULL);
1494
1495 /* Terminate CS4215 control mode - data sheet says
1496 * "Set CLB=1 and send two more frames of valid control info"
1497 */
1498 dbri->mm.ctrl[0] |= CS4215_CLB;
1499 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1500
1501 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1502 udelay(250);
1503
1504 cs4215_setdata(dbri, 0);
1505
1506 return 0;
1507 }
1508
1509 /*
1510 * Setup the codec with the sampling rate, audio format and number of
1511 * channels.
1512 * As part of the process we resend the settings for the data
1513 * timeslots as well.
1514 */
1515 static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate,
1516 snd_pcm_format_t format, unsigned int channels)
1517 {
1518 int freq_idx;
1519 int ret = 0;
1520
1521 /* Lookup index for this rate */
1522 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1523 if (CS4215_FREQ[freq_idx].freq == rate)
1524 break;
1525 }
1526 if (CS4215_FREQ[freq_idx].freq != rate) {
1527 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1528 return -1;
1529 }
1530
1531 switch (format) {
1532 case SNDRV_PCM_FORMAT_MU_LAW:
1533 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1534 dbri->mm.precision = 8;
1535 break;
1536 case SNDRV_PCM_FORMAT_A_LAW:
1537 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1538 dbri->mm.precision = 8;
1539 break;
1540 case SNDRV_PCM_FORMAT_U8:
1541 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1542 dbri->mm.precision = 8;
1543 break;
1544 case SNDRV_PCM_FORMAT_S16_BE:
1545 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1546 dbri->mm.precision = 16;
1547 break;
1548 default:
1549 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1550 return -1;
1551 }
1552
1553 /* Add rate parameters */
1554 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1555 dbri->mm.ctrl[2] = CS4215_XCLK |
1556 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1557
1558 dbri->mm.channels = channels;
1559 /* Stereo bit: 8 bit stereo not working yet. */
1560 if ((channels > 1) && (dbri->mm.precision == 16))
1561 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1562
1563 ret = cs4215_setctrl(dbri);
1564 if (ret == 0)
1565 cs4215_open(dbri); /* set codec to data mode */
1566
1567 return ret;
1568 }
1569
1570 /*
1571 *
1572 */
1573 static int cs4215_init(struct snd_dbri * dbri)
1574 {
1575 u32 reg2 = sbus_readl(dbri->regs + REG2);
1576 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1577
1578 /* Look for the cs4215 chips */
1579 if (reg2 & D_PIO2) {
1580 dprintk(D_MM, "Onboard CS4215 detected\n");
1581 dbri->mm.onboard = 1;
1582 }
1583 if (reg2 & D_PIO0) {
1584 dprintk(D_MM, "Speakerbox detected\n");
1585 dbri->mm.onboard = 0;
1586
1587 if (reg2 & D_PIO2) {
1588 printk(KERN_INFO "DBRI: Using speakerbox / "
1589 "ignoring onboard mmcodec.\n");
1590 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1591 }
1592 }
1593
1594 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1595 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1596 return -EIO;
1597 }
1598
1599 cs4215_setup_pipes(dbri);
1600
1601 cs4215_init_data(&dbri->mm);
1602
1603 /* Enable capture of the status & version timeslots. */
1604 recv_fixed(dbri, 18, &dbri->mm.status);
1605 recv_fixed(dbri, 19, &dbri->mm.version);
1606
1607 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1608 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1609 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1610 dbri->mm.offset);
1611 return -EIO;
1612 }
1613 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1614
1615 return 0;
1616 }
1617
1618 /*
1619 ****************************************************************************
1620 *************************** DBRI interrupt handler *************************
1621 ****************************************************************************
1622
1623 The DBRI communicates with the CPU mainly via a circular interrupt
1624 buffer. When an interrupt is signaled, the CPU walks through the
1625 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1626 Complicated interrupts are handled by dedicated functions (which
1627 appear first in this file). Any pending interrupts can be serviced by
1628 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1629 interrupts are disabled. This function is used by dbri_cmdlock()
1630 to make sure we're synced up with the chip before each command sequence,
1631 even if we're running cli'ed.
1632
1633 */
1634
1635 /* xmit_descs()
1636 *
1637 * Transmit the current TD's for recording/playing, if needed.
1638 * For playback, ALSA has filled the DMA memory with new data (we hope).
1639 */
1640 static void xmit_descs(unsigned long data)
1641 {
1642 struct snd_dbri *dbri = (struct snd_dbri *) data;
1643 struct dbri_streaminfo *info;
1644 volatile s32 *cmd;
1645 unsigned long flags;
1646 int first_td;
1647
1648 if (dbri == NULL)
1649 return; /* Disabled */
1650
1651 /* First check the recording stream for buffer overflow */
1652 info = &dbri->stream_info[DBRI_REC];
1653 spin_lock_irqsave(&dbri->lock, flags);
1654
1655 if ((info->left >= info->size) && (info->pipe >= 0)) {
1656 first_td = dbri->pipes[info->pipe].first_desc;
1657
1658 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1659
1660 /* Stream could be closed by the time we run. */
1661 if (first_td < 0) {
1662 goto play;
1663 }
1664
1665 cmd = dbri_cmdlock(dbri, NoGetLock);
1666 *(cmd++) = DBRI_CMD(D_SDP, 0,
1667 dbri->pipes[info->pipe].sdp
1668 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1669 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1670 dbri_cmdsend(dbri, cmd);
1671
1672 /* Reset our admin of the pipe & bytes read. */
1673 dbri->pipes[info->pipe].desc = first_td;
1674 info->left = 0;
1675 }
1676
1677 play:
1678 spin_unlock_irqrestore(&dbri->lock, flags);
1679
1680 /* Now check the playback stream for buffer underflow */
1681 info = &dbri->stream_info[DBRI_PLAY];
1682 spin_lock_irqsave(&dbri->lock, flags);
1683
1684 if ((info->left <= 0) && (info->pipe >= 0)) {
1685 first_td = dbri->pipes[info->pipe].first_desc;
1686
1687 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1688
1689 /* Stream could be closed by the time we run. */
1690 if (first_td < 0) {
1691 spin_unlock_irqrestore(&dbri->lock, flags);
1692 return;
1693 }
1694
1695 cmd = dbri_cmdlock(dbri, NoGetLock);
1696 *(cmd++) = DBRI_CMD(D_SDP, 0,
1697 dbri->pipes[info->pipe].sdp
1698 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1699 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1700 dbri_cmdsend(dbri, cmd);
1701
1702 /* Reset our admin of the pipe & bytes written. */
1703 dbri->pipes[info->pipe].desc = first_td;
1704 info->left = info->size;
1705 }
1706 spin_unlock_irqrestore(&dbri->lock, flags);
1707 }
1708
1709 static DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0);
1710
1711 /* transmission_complete_intr()
1712 *
1713 * Called by main interrupt handler when DBRI signals transmission complete
1714 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1715 *
1716 * Walks through the pipe's list of transmit buffer descriptors and marks
1717 * them as available. Stops when the first descriptor is found without
1718 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1719 *
1720 * The DMA buffers are not released, but re-used. Since the transmit buffer
1721 * descriptors are not clobbered, they can be re-submitted as is. This is
1722 * done by the xmit_descs() tasklet above since that could take longer.
1723 */
1724
1725 static void transmission_complete_intr(struct snd_dbri * dbri, int pipe)
1726 {
1727 struct dbri_streaminfo *info;
1728 int td;
1729 int status;
1730 int len;
1731
1732 info = &dbri->stream_info[DBRI_PLAY];
1733
1734 td = dbri->pipes[pipe].desc;
1735 while (td >= 0) {
1736 if (td >= DBRI_NO_DESCS) {
1737 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1738 return;
1739 }
1740
1741 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1742 if (!(status & DBRI_TD_TBC)) {
1743 break;
1744 }
1745
1746 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1747
1748 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1749 len = DBRI_RD_CNT(dbri->dma->desc[td].word1);
1750 info->offset += len;
1751 info->left -= len;
1752
1753 /* On the last TD, transmit them all again. */
1754 if (dbri->next_desc[td] == -1) {
1755 if (info->left > 0) {
1756 printk(KERN_WARNING
1757 "%d bytes left after last transfer.\n",
1758 info->left);
1759 info->left = 0;
1760 }
1761 tasklet_schedule(&xmit_descs_task);
1762 }
1763
1764 td = dbri->next_desc[td];
1765 dbri->pipes[pipe].desc = td;
1766 }
1767
1768 /* Notify ALSA */
1769 if (spin_is_locked(&dbri->lock)) {
1770 spin_unlock(&dbri->lock);
1771 snd_pcm_period_elapsed(info->substream);
1772 spin_lock(&dbri->lock);
1773 } else
1774 snd_pcm_period_elapsed(info->substream);
1775 }
1776
1777 static void reception_complete_intr(struct snd_dbri * dbri, int pipe)
1778 {
1779 struct dbri_streaminfo *info;
1780 int rd = dbri->pipes[pipe].desc;
1781 s32 status;
1782
1783 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1784 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1785 return;
1786 }
1787
1788 dbri->dma->desc[rd].ba = 0;
1789 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1790 status = dbri->dma->desc[rd].word1;
1791 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1792
1793 info = &dbri->stream_info[DBRI_REC];
1794 info->offset += DBRI_RD_CNT(status);
1795 info->left += DBRI_RD_CNT(status);
1796
1797 /* FIXME: Check status */
1798
1799 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1800 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1801
1802 /* On the last TD, transmit them all again. */
1803 if (dbri->next_desc[rd] == -1) {
1804 if (info->left > info->size) {
1805 printk(KERN_WARNING
1806 "%d bytes recorded in %d size buffer.\n",
1807 info->left, info->size);
1808 }
1809 tasklet_schedule(&xmit_descs_task);
1810 }
1811
1812 /* Notify ALSA */
1813 if (spin_is_locked(&dbri->lock)) {
1814 spin_unlock(&dbri->lock);
1815 snd_pcm_period_elapsed(info->substream);
1816 spin_lock(&dbri->lock);
1817 } else
1818 snd_pcm_period_elapsed(info->substream);
1819 }
1820
1821 static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x)
1822 {
1823 int val = D_INTR_GETVAL(x);
1824 int channel = D_INTR_GETCHAN(x);
1825 int command = D_INTR_GETCMD(x);
1826 int code = D_INTR_GETCODE(x);
1827 #ifdef DBRI_DEBUG
1828 int rval = D_INTR_GETRVAL(x);
1829 #endif
1830
1831 if (channel == D_INTR_CMD) {
1832 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1833 cmds[command], val);
1834 } else {
1835 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1836 channel, code, rval);
1837 }
1838
1839 if (channel == D_INTR_CMD && command == D_WAIT) {
1840 dbri->wait_ackd = val;
1841 if (dbri->wait_send != val) {
1842 printk(KERN_ERR "Processing wait command %d when %d was send.\n",
1843 val, dbri->wait_send);
1844 }
1845 return;
1846 }
1847
1848 switch (code) {
1849 case D_INTR_BRDY:
1850 reception_complete_intr(dbri, channel);
1851 break;
1852 case D_INTR_XCMP:
1853 case D_INTR_MINT:
1854 transmission_complete_intr(dbri, channel);
1855 break;
1856 case D_INTR_UNDR:
1857 /* UNDR - Transmission underrun
1858 * resend SDP command with clear pipe bit (C) set
1859 */
1860 {
1861 volatile s32 *cmd;
1862
1863 int pipe = channel;
1864 int td = dbri->pipes[pipe].desc;
1865
1866 dbri->dma->desc[td].word4 = 0;
1867 cmd = dbri_cmdlock(dbri, NoGetLock);
1868 *(cmd++) = DBRI_CMD(D_SDP, 0,
1869 dbri->pipes[pipe].sdp
1870 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1871 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1872 dbri_cmdsend(dbri, cmd);
1873 }
1874 break;
1875 case D_INTR_FXDT:
1876 /* FXDT - Fixed data change */
1877 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1878 val = reverse_bytes(val, dbri->pipes[channel].length);
1879
1880 if (dbri->pipes[channel].recv_fixed_ptr)
1881 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1882 break;
1883 default:
1884 if (channel != D_INTR_CMD)
1885 printk(KERN_WARNING
1886 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1887 }
1888 }
1889
1890 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1891 * buffer until it finds a zero word (indicating nothing more to do
1892 * right now). Non-zero words require processing and are handed off
1893 * to dbri_process_one_interrupt AFTER advancing the pointer. This
1894 * order is important since we might recurse back into this function
1895 * and need to make sure the pointer has been advanced first.
1896 */
1897 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri)
1898 {
1899 s32 x;
1900
1901 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1902 dbri->dma->intr[dbri->dbri_irqp] = 0;
1903 dbri->dbri_irqp++;
1904 if (dbri->dbri_irqp == DBRI_INT_BLK)
1905 dbri->dbri_irqp = 1;
1906
1907 dbri_process_one_interrupt(dbri, x);
1908 }
1909 }
1910
1911 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id,
1912 struct pt_regs *regs)
1913 {
1914 struct snd_dbri *dbri = dev_id;
1915 static int errcnt = 0;
1916 int x;
1917
1918 if (dbri == NULL)
1919 return IRQ_NONE;
1920 spin_lock(&dbri->lock);
1921
1922 /*
1923 * Read it, so the interrupt goes away.
1924 */
1925 x = sbus_readl(dbri->regs + REG1);
1926
1927 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1928 u32 tmp;
1929
1930 if (x & D_MRR)
1931 printk(KERN_ERR
1932 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1933 x);
1934 if (x & D_MLE)
1935 printk(KERN_ERR
1936 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1937 x);
1938 if (x & D_LBG)
1939 printk(KERN_ERR
1940 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1941 if (x & D_MBE)
1942 printk(KERN_ERR
1943 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1944
1945 /* Some of these SBus errors cause the chip's SBus circuitry
1946 * to be disabled, so just re-enable and try to keep going.
1947 *
1948 * The only one I've seen is MRR, which will be triggered
1949 * if you let a transmit pipe underrun, then try to CDP it.
1950 *
1951 * If these things persist, we reset the chip.
1952 */
1953 if ((++errcnt) % 10 == 0) {
1954 dprintk(D_INT, "Interrupt errors exceeded.\n");
1955 dbri_reset(dbri);
1956 } else {
1957 tmp = sbus_readl(dbri->regs + REG0);
1958 tmp &= ~(D_D);
1959 sbus_writel(tmp, dbri->regs + REG0);
1960 }
1961 }
1962
1963 dbri_process_interrupt_buffer(dbri);
1964
1965 /* FIXME: Write 0 into regs to ACK interrupt */
1966
1967 spin_unlock(&dbri->lock);
1968
1969 return IRQ_HANDLED;
1970 }
1971
1972 /****************************************************************************
1973 PCM Interface
1974 ****************************************************************************/
1975 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1976 .info = (SNDRV_PCM_INFO_MMAP |
1977 SNDRV_PCM_INFO_INTERLEAVED |
1978 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1979 SNDRV_PCM_INFO_MMAP_VALID),
1980 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1981 SNDRV_PCM_FMTBIT_A_LAW |
1982 SNDRV_PCM_FMTBIT_U8 |
1983 SNDRV_PCM_FMTBIT_S16_BE,
1984 .rates = SNDRV_PCM_RATE_8000_48000,
1985 .rate_min = 8000,
1986 .rate_max = 48000,
1987 .channels_min = 1,
1988 .channels_max = 2,
1989 .buffer_bytes_max = (64 * 1024),
1990 .period_bytes_min = 1,
1991 .period_bytes_max = DBRI_TD_MAXCNT,
1992 .periods_min = 1,
1993 .periods_max = 1024,
1994 };
1995
1996 static int snd_dbri_open(struct snd_pcm_substream *substream)
1997 {
1998 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
1999 struct snd_pcm_runtime *runtime = substream->runtime;
2000 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2001 unsigned long flags;
2002
2003 dprintk(D_USR, "open audio output.\n");
2004 runtime->hw = snd_dbri_pcm_hw;
2005
2006 spin_lock_irqsave(&dbri->lock, flags);
2007 info->substream = substream;
2008 info->left = 0;
2009 info->offset = 0;
2010 info->dvma_buffer = 0;
2011 info->pipe = -1;
2012 spin_unlock_irqrestore(&dbri->lock, flags);
2013
2014 cs4215_open(dbri);
2015
2016 return 0;
2017 }
2018
2019 static int snd_dbri_close(struct snd_pcm_substream *substream)
2020 {
2021 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2022 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2023
2024 dprintk(D_USR, "close audio output.\n");
2025 info->substream = NULL;
2026 info->left = 0;
2027 info->offset = 0;
2028
2029 return 0;
2030 }
2031
2032 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2033 struct snd_pcm_hw_params *hw_params)
2034 {
2035 struct snd_pcm_runtime *runtime = substream->runtime;
2036 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2037 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2038 int direction;
2039 int ret;
2040
2041 /* set sampling rate, audio format and number of channels */
2042 ret = cs4215_prepare(dbri, params_rate(hw_params),
2043 params_format(hw_params),
2044 params_channels(hw_params));
2045 if (ret != 0)
2046 return ret;
2047
2048 if ((ret = snd_pcm_lib_malloc_pages(substream,
2049 params_buffer_bytes(hw_params))) < 0) {
2050 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2051 return ret;
2052 }
2053
2054 /* hw_params can get called multiple times. Only map the DMA once.
2055 */
2056 if (info->dvma_buffer == 0) {
2057 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2058 direction = SBUS_DMA_TODEVICE;
2059 else
2060 direction = SBUS_DMA_FROMDEVICE;
2061
2062 info->dvma_buffer = sbus_map_single(dbri->sdev,
2063 runtime->dma_area,
2064 params_buffer_bytes(hw_params),
2065 direction);
2066 }
2067
2068 direction = params_buffer_bytes(hw_params);
2069 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2070 direction, info->dvma_buffer);
2071 return 0;
2072 }
2073
2074 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2075 {
2076 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2077 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2078 int direction;
2079 dprintk(D_USR, "hw_free.\n");
2080
2081 /* hw_free can get called multiple times. Only unmap the DMA once.
2082 */
2083 if (info->dvma_buffer) {
2084 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2085 direction = SBUS_DMA_TODEVICE;
2086 else
2087 direction = SBUS_DMA_FROMDEVICE;
2088
2089 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2090 substream->runtime->buffer_size, direction);
2091 info->dvma_buffer = 0;
2092 }
2093 info->pipe = -1;
2094
2095 return snd_pcm_lib_free_pages(substream);
2096 }
2097
2098 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2099 {
2100 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2101 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2102 struct snd_pcm_runtime *runtime = substream->runtime;
2103 int ret;
2104
2105 info->size = snd_pcm_lib_buffer_bytes(substream);
2106 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2107 info->pipe = 4; /* Send pipe */
2108 else {
2109 info->pipe = 6; /* Receive pipe */
2110 info->left = info->size; /* To trigger submittal */
2111 }
2112
2113 spin_lock_irq(&dbri->lock);
2114
2115 /* Setup the all the transmit/receive desciptors to cover the
2116 * whole DMA buffer.
2117 */
2118 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2119 snd_pcm_lib_period_bytes(substream));
2120
2121 runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels;
2122
2123 spin_unlock_irq(&dbri->lock);
2124
2125 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2126 return ret;
2127 }
2128
2129 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2130 {
2131 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2132 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2133 int ret = 0;
2134
2135 switch (cmd) {
2136 case SNDRV_PCM_TRIGGER_START:
2137 dprintk(D_USR, "start audio, period is %d bytes\n",
2138 (int)snd_pcm_lib_period_bytes(substream));
2139 /* Enable & schedule the tasklet that re-submits the TDs. */
2140 xmit_descs_task.data = (unsigned long)dbri;
2141 tasklet_schedule(&xmit_descs_task);
2142 break;
2143 case SNDRV_PCM_TRIGGER_STOP:
2144 dprintk(D_USR, "stop audio.\n");
2145 /* Make the tasklet bail out immediately. */
2146 xmit_descs_task.data = 0;
2147 reset_pipe(dbri, info->pipe);
2148 break;
2149 default:
2150 ret = -EINVAL;
2151 }
2152
2153 return ret;
2154 }
2155
2156 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2157 {
2158 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2159 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2160 snd_pcm_uframes_t ret;
2161
2162 ret = bytes_to_frames(substream->runtime, info->offset)
2163 % substream->runtime->buffer_size;
2164 dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n",
2165 ret, info->left);
2166 return ret;
2167 }
2168
2169 static struct snd_pcm_ops snd_dbri_ops = {
2170 .open = snd_dbri_open,
2171 .close = snd_dbri_close,
2172 .ioctl = snd_pcm_lib_ioctl,
2173 .hw_params = snd_dbri_hw_params,
2174 .hw_free = snd_dbri_hw_free,
2175 .prepare = snd_dbri_prepare,
2176 .trigger = snd_dbri_trigger,
2177 .pointer = snd_dbri_pointer,
2178 };
2179
2180 static int __devinit snd_dbri_pcm(struct snd_dbri * dbri)
2181 {
2182 struct snd_pcm *pcm;
2183 int err;
2184
2185 if ((err = snd_pcm_new(dbri->card,
2186 /* ID */ "sun_dbri",
2187 /* device */ 0,
2188 /* playback count */ 1,
2189 /* capture count */ 1, &pcm)) < 0)
2190 return err;
2191 snd_assert(pcm != NULL, return -EINVAL);
2192
2193 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2194 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2195
2196 pcm->private_data = dbri;
2197 pcm->info_flags = 0;
2198 strcpy(pcm->name, dbri->card->shortname);
2199
2200 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2201 SNDRV_DMA_TYPE_CONTINUOUS,
2202 snd_dma_continuous_data(GFP_KERNEL),
2203 64 * 1024, 64 * 1024)) < 0) {
2204 return err;
2205 }
2206
2207 return 0;
2208 }
2209
2210 /*****************************************************************************
2211 Mixer interface
2212 *****************************************************************************/
2213
2214 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2215 struct snd_ctl_elem_info *uinfo)
2216 {
2217 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2218 uinfo->count = 2;
2219 uinfo->value.integer.min = 0;
2220 if (kcontrol->private_value == DBRI_PLAY) {
2221 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2222 } else {
2223 uinfo->value.integer.max = DBRI_MAX_GAIN;
2224 }
2225 return 0;
2226 }
2227
2228 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2229 struct snd_ctl_elem_value *ucontrol)
2230 {
2231 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2232 struct dbri_streaminfo *info;
2233 snd_assert(dbri != NULL, return -EINVAL);
2234 info = &dbri->stream_info[kcontrol->private_value];
2235 snd_assert(info != NULL, return -EINVAL);
2236
2237 ucontrol->value.integer.value[0] = info->left_gain;
2238 ucontrol->value.integer.value[1] = info->right_gain;
2239 return 0;
2240 }
2241
2242 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2243 struct snd_ctl_elem_value *ucontrol)
2244 {
2245 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2246 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value];
2247 unsigned long flags;
2248 int changed = 0;
2249
2250 if (info->left_gain != ucontrol->value.integer.value[0]) {
2251 info->left_gain = ucontrol->value.integer.value[0];
2252 changed = 1;
2253 }
2254 if (info->right_gain != ucontrol->value.integer.value[1]) {
2255 info->right_gain = ucontrol->value.integer.value[1];
2256 changed = 1;
2257 }
2258 if (changed == 1) {
2259 /* First mute outputs, and wait 1/8000 sec (125 us)
2260 * to make sure this takes. This avoids clicking noises.
2261 */
2262 spin_lock_irqsave(&dbri->lock, flags);
2263
2264 cs4215_setdata(dbri, 1);
2265 udelay(125);
2266 cs4215_setdata(dbri, 0);
2267
2268 spin_unlock_irqrestore(&dbri->lock, flags);
2269 }
2270 return changed;
2271 }
2272
2273 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2274 struct snd_ctl_elem_info *uinfo)
2275 {
2276 int mask = (kcontrol->private_value >> 16) & 0xff;
2277
2278 uinfo->type = (mask == 1) ?
2279 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2280 uinfo->count = 1;
2281 uinfo->value.integer.min = 0;
2282 uinfo->value.integer.max = mask;
2283 return 0;
2284 }
2285
2286 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2287 struct snd_ctl_elem_value *ucontrol)
2288 {
2289 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2290 int elem = kcontrol->private_value & 0xff;
2291 int shift = (kcontrol->private_value >> 8) & 0xff;
2292 int mask = (kcontrol->private_value >> 16) & 0xff;
2293 int invert = (kcontrol->private_value >> 24) & 1;
2294 snd_assert(dbri != NULL, return -EINVAL);
2295
2296 if (elem < 4) {
2297 ucontrol->value.integer.value[0] =
2298 (dbri->mm.data[elem] >> shift) & mask;
2299 } else {
2300 ucontrol->value.integer.value[0] =
2301 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2302 }
2303
2304 if (invert == 1) {
2305 ucontrol->value.integer.value[0] =
2306 mask - ucontrol->value.integer.value[0];
2307 }
2308 return 0;
2309 }
2310
2311 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2312 struct snd_ctl_elem_value *ucontrol)
2313 {
2314 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2315 unsigned long flags;
2316 int elem = kcontrol->private_value & 0xff;
2317 int shift = (kcontrol->private_value >> 8) & 0xff;
2318 int mask = (kcontrol->private_value >> 16) & 0xff;
2319 int invert = (kcontrol->private_value >> 24) & 1;
2320 int changed = 0;
2321 unsigned short val;
2322 snd_assert(dbri != NULL, return -EINVAL);
2323
2324 val = (ucontrol->value.integer.value[0] & mask);
2325 if (invert == 1)
2326 val = mask - val;
2327 val <<= shift;
2328
2329 if (elem < 4) {
2330 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2331 ~(mask << shift)) | val;
2332 changed = (val != dbri->mm.data[elem]);
2333 } else {
2334 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2335 ~(mask << shift)) | val;
2336 changed = (val != dbri->mm.ctrl[elem - 4]);
2337 }
2338
2339 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2340 "mixer-value=%ld, mm-value=0x%x\n",
2341 mask, changed, ucontrol->value.integer.value[0],
2342 dbri->mm.data[elem & 3]);
2343
2344 if (changed) {
2345 /* First mute outputs, and wait 1/8000 sec (125 us)
2346 * to make sure this takes. This avoids clicking noises.
2347 */
2348 spin_lock_irqsave(&dbri->lock, flags);
2349
2350 cs4215_setdata(dbri, 1);
2351 udelay(125);
2352 cs4215_setdata(dbri, 0);
2353
2354 spin_unlock_irqrestore(&dbri->lock, flags);
2355 }
2356 return changed;
2357 }
2358
2359 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2360 timeslots. Shift is the bit offset in the timeslot, mask defines the
2361 number of bits. invert is a boolean for use with attenuation.
2362 */
2363 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2364 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2365 .info = snd_cs4215_info_single, \
2366 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2367 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
2368
2369 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2370 {
2371 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2372 .name = "Playback Volume",
2373 .info = snd_cs4215_info_volume,
2374 .get = snd_cs4215_get_volume,
2375 .put = snd_cs4215_put_volume,
2376 .private_value = DBRI_PLAY,
2377 },
2378 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2379 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2380 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2381 {
2382 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2383 .name = "Capture Volume",
2384 .info = snd_cs4215_info_volume,
2385 .get = snd_cs4215_get_volume,
2386 .put = snd_cs4215_put_volume,
2387 .private_value = DBRI_REC,
2388 },
2389 /* FIXME: mic/line switch */
2390 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2391 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2392 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2393 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2394 };
2395
2396 #define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(struct snd_kcontrol_new))
2397
2398 static int __init snd_dbri_mixer(struct snd_dbri * dbri)
2399 {
2400 struct snd_card *card;
2401 int idx, err;
2402
2403 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2404
2405 card = dbri->card;
2406 strcpy(card->mixername, card->shortname);
2407
2408 for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) {
2409 if ((err = snd_ctl_add(card,
2410 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0)
2411 return err;
2412 }
2413
2414 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2415 dbri->stream_info[idx].left_gain = 0;
2416 dbri->stream_info[idx].right_gain = 0;
2417 }
2418
2419 return 0;
2420 }
2421
2422 /****************************************************************************
2423 /proc interface
2424 ****************************************************************************/
2425 static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
2426 {
2427 struct snd_dbri *dbri = entry->private_data;
2428
2429 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2430 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2431 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2432 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2433 }
2434
2435 #ifdef DBRI_DEBUG
2436 static void dbri_debug_read(struct snd_info_entry * entry,
2437 struct snd_info_buffer *buffer)
2438 {
2439 struct snd_dbri *dbri = entry->private_data;
2440 int pipe;
2441 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2442
2443 for (pipe = 0; pipe < 32; pipe++) {
2444 if (pipe_active(dbri, pipe)) {
2445 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2446 snd_iprintf(buffer,
2447 "Pipe %d: %s SDP=0x%x desc=%d, "
2448 "len=%d @ %d next %d\n",
2449 pipe,
2450 ((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"),
2451 pptr->sdp, pptr->desc,
2452 pptr->length, pptr->cycle, pptr->nextpipe);
2453 }
2454 }
2455 }
2456 #endif
2457
2458 void snd_dbri_proc(struct snd_dbri * dbri)
2459 {
2460 struct snd_info_entry *entry;
2461
2462 if (! snd_card_proc_new(dbri->card, "regs", &entry))
2463 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2464
2465 #ifdef DBRI_DEBUG
2466 if (! snd_card_proc_new(dbri->card, "debug", &entry)) {
2467 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2468 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2469 }
2470 #endif
2471 }
2472
2473 /*
2474 ****************************************************************************
2475 **************************** Initialization ********************************
2476 ****************************************************************************
2477 */
2478 static void snd_dbri_free(struct snd_dbri * dbri);
2479
2480 static int __init snd_dbri_create(struct snd_card *card,
2481 struct sbus_dev *sdev,
2482 struct linux_prom_irqs *irq, int dev)
2483 {
2484 struct snd_dbri *dbri = card->private_data;
2485 int err;
2486
2487 spin_lock_init(&dbri->lock);
2488 dbri->card = card;
2489 dbri->sdev = sdev;
2490 dbri->irq = irq->pri;
2491
2492 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2493 &dbri->dma_dvma);
2494 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2495
2496 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2497 dbri->dma, dbri->dma_dvma);
2498
2499 /* Map the registers into memory. */
2500 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2501 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2502 dbri->regs_size, "DBRI Registers");
2503 if (!dbri->regs) {
2504 printk(KERN_ERR "DBRI: could not allocate registers\n");
2505 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2506 (void *)dbri->dma, dbri->dma_dvma);
2507 return -EIO;
2508 }
2509
2510 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2511 "DBRI audio", dbri);
2512 if (err) {
2513 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2514 sbus_iounmap(dbri->regs, dbri->regs_size);
2515 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2516 (void *)dbri->dma, dbri->dma_dvma);
2517 return err;
2518 }
2519
2520 /* Do low level initialization of the DBRI and CS4215 chips */
2521 dbri_initialize(dbri);
2522 err = cs4215_init(dbri);
2523 if (err) {
2524 snd_dbri_free(dbri);
2525 return err;
2526 }
2527
2528 dbri->next = dbri_list;
2529 dbri_list = dbri;
2530
2531 return 0;
2532 }
2533
2534 static void snd_dbri_free(struct snd_dbri * dbri)
2535 {
2536 dprintk(D_GEN, "snd_dbri_free\n");
2537 dbri_reset(dbri);
2538
2539 if (dbri->irq)
2540 free_irq(dbri->irq, dbri);
2541
2542 if (dbri->regs)
2543 sbus_iounmap(dbri->regs, dbri->regs_size);
2544
2545 if (dbri->dma)
2546 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2547 (void *)dbri->dma, dbri->dma_dvma);
2548 }
2549
2550 static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2551 {
2552 struct snd_dbri *dbri;
2553 struct linux_prom_irqs irq;
2554 struct resource *rp;
2555 struct snd_card *card;
2556 static int dev = 0;
2557 int err;
2558
2559 if (sdev->prom_name[9] < 'e') {
2560 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2561 sdev->prom_name[9]);
2562 return -EIO;
2563 }
2564
2565 if (dev >= SNDRV_CARDS)
2566 return -ENODEV;
2567 if (!enable[dev]) {
2568 dev++;
2569 return -ENOENT;
2570 }
2571
2572 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2573 if (err < 0) {
2574 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev);
2575 return -ENODEV;
2576 }
2577
2578 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2579 sizeof(struct snd_dbri));
2580 if (card == NULL)
2581 return -ENOMEM;
2582
2583 strcpy(card->driver, "DBRI");
2584 strcpy(card->shortname, "Sun DBRI");
2585 rp = &sdev->resource[0];
2586 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2587 card->shortname,
2588 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
2589
2590 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2591 snd_card_free(card);
2592 return err;
2593 }
2594
2595 dbri = card->private_data;
2596 if ((err = snd_dbri_pcm(dbri)) < 0)
2597 goto _err;
2598
2599 if ((err = snd_dbri_mixer(dbri)) < 0)
2600 goto _err;
2601
2602 /* /proc file handling */
2603 snd_dbri_proc(dbri);
2604
2605 if ((err = snd_card_register(card)) < 0)
2606 goto _err;
2607
2608 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2609 dev, dbri->regs,
2610 dbri->irq, sdev->prom_name[9], dbri->mm.version);
2611 dev++;
2612
2613 return 0;
2614
2615 _err:
2616 snd_dbri_free(dbri);
2617 snd_card_free(card);
2618 return err;
2619 }
2620
2621 /* Probe for the dbri chip and then attach the driver. */
2622 static int __init dbri_init(void)
2623 {
2624 struct sbus_bus *sbus;
2625 struct sbus_dev *sdev;
2626 int found = 0;
2627
2628 /* Probe each SBUS for the DBRI chip(s). */
2629 for_all_sbusdev(sdev, sbus) {
2630 /*
2631 * The version is coded in the last character
2632 */
2633 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2634 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2635 sdev->prom_name, sdev->slot);
2636
2637 if (dbri_attach(sdev->prom_node, sdev) == 0)
2638 found++;
2639 }
2640 }
2641
2642 return (found > 0) ? 0 : -EIO;
2643 }
2644
2645 static void __exit dbri_exit(void)
2646 {
2647 struct snd_dbri *this = dbri_list;
2648
2649 while (this != NULL) {
2650 struct snd_dbri *next = this->next;
2651 struct snd_card *card = this->card;
2652
2653 snd_dbri_free(this);
2654 snd_card_free(card);
2655 this = next;
2656 }
2657 dbri_list = NULL;
2658 }
2659
2660 module_init(dbri_init);
2661 module_exit(dbri_exit);
Linux kernel - Deliverables
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