virt/kvm/arm/vgic/vgic-its.c

   1 /*
   2  * GICv3 ITS emulation
   3  *
   4  * Copyright (C) 2015,2016 ARM Ltd.
   5  * Author: Andre Przywara <andre.przywara@arm.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/cpu.h>
  21 #include <linux/kvm.h>
  22 #include <linux/kvm_host.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/list.h>
  25 #include <linux/uaccess.h>
  26
  27 #include <linux/irqchip/arm-gic-v3.h>
  28
  29 #include <asm/kvm_emulate.h>
  30 #include <asm/kvm_arm.h>
  31 #include <asm/kvm_mmu.h>
  32
  33 #include "vgic.h"
  34 #include "vgic-mmio.h"
  35
  36 struct its_device {
  37         struct list_head dev_list;
  38
  39         /* the head for the list of ITTEs */
  40         struct list_head itt_head;
  41         u32 device_id;
  42 };
  43
  44 #define COLLECTION_NOT_MAPPED ((u32)~0)
  45
  46 struct its_collection {
  47         struct list_head coll_list;
  48
  49         u32 collection_id;
  50         u32 target_addr;
  51 };
  52
  53 #define its_is_collection_mapped(coll) ((coll) && \
  54                                 ((coll)->target_addr != COLLECTION_NOT_MAPPED))
  55
  56 struct its_itte {
  57         struct list_head itte_list;
  58
  59         struct vgic_irq *irq;
  60         struct its_collection *collection;
  61         u32 lpi;
  62         u32 event_id;
  63 };
  64
  65 /*
  66  * We only implement 48 bits of PA at the moment, although the ITS
  67  * supports more. Let's be restrictive here.
  68  */
  69 #define CBASER_ADDRESS(x)       ((x) & GENMASK_ULL(47, 12))
  70 #define PENDBASER_ADDRESS(x)    ((x) & GENMASK_ULL(47, 16))
  71 #define PROPBASER_ADDRESS(x)    ((x) & GENMASK_ULL(47, 12))
  72
  73 #define GIC_LPI_OFFSET 8192
  74
  75 #define LPI_PROP_ENABLE_BIT(p)  ((p) & LPI_PROP_ENABLED)
  76 #define LPI_PROP_PRIORITY(p)    ((p) & 0xfc)
  77
  78 /*
  79  * Reads the configuration data for a given LPI from guest memory and
  80  * updates the fields in struct vgic_irq.
  81  * If filter_vcpu is not NULL, applies only if the IRQ is targeting this
  82  * VCPU. Unconditionally applies if filter_vcpu is NULL.
  83  */
  84 static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
  85                              struct kvm_vcpu *filter_vcpu)
  86 {
  87         u64 propbase = PROPBASER_ADDRESS(kvm->arch.vgic.propbaser);
  88         u8 prop;
  89         int ret;
  90
  91         ret = kvm_read_guest(kvm, propbase + irq->intid - GIC_LPI_OFFSET,
  92                              &prop, 1);
  93
  94         if (ret)
  95                 return ret;
  96
  97         spin_lock(&irq->irq_lock);
  98
  99         if (!filter_vcpu || filter_vcpu == irq->target_vcpu) {
 100                 irq->priority = LPI_PROP_PRIORITY(prop);
 101                 irq->enabled = LPI_PROP_ENABLE_BIT(prop);
 102
 103                 vgic_queue_irq_unlock(kvm, irq);
 104         } else {
 105                 spin_unlock(&irq->irq_lock);
 106         }
 107
 108         return 0;
 109 }
 110
 111 /*
 112  * Create a snapshot of the current LPI list, so that we can enumerate all
 113  * LPIs without holding any lock.
 114  * Returns the array length and puts the kmalloc'ed array into intid_ptr.
 115  */
 116 static int vgic_copy_lpi_list(struct kvm *kvm, u32 **intid_ptr)
 117 {
 118         struct vgic_dist *dist = &kvm->arch.vgic;
 119         struct vgic_irq *irq;
 120         u32 *intids;
 121         int irq_count = dist->lpi_list_count, i = 0;
 122
 123         /*
 124          * We use the current value of the list length, which may change
 125          * after the kmalloc. We don't care, because the guest shouldn't
 126          * change anything while the command handling is still running,
 127          * and in the worst case we would miss a new IRQ, which one wouldn't
 128          * expect to be covered by this command anyway.
 129          */
 130         intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL);
 131         if (!intids)
 132                 return -ENOMEM;
 133
 134         spin_lock(&dist->lpi_list_lock);
 135         list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
 136                 /* We don't need to "get" the IRQ, as we hold the list lock. */
 137                 intids[i] = irq->intid;
 138                 if (++i == irq_count)
 139                         break;
 140         }
 141         spin_unlock(&dist->lpi_list_lock);
 142
 143         *intid_ptr = intids;
 144         return irq_count;
 145 }
 146
 147 /*
 148  * Scan the whole LPI pending table and sync the pending bit in there
 149  * with our own data structures. This relies on the LPI being
 150  * mapped before.
 151  */
 152 static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
 153 {
 154         gpa_t pendbase = PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 155         struct vgic_irq *irq;
 156         int last_byte_offset = -1;
 157         int ret = 0;
 158         u32 *intids;
 159         int nr_irqs, i;
 160
 161         nr_irqs = vgic_copy_lpi_list(vcpu->kvm, &intids);
 162         if (nr_irqs < 0)
 163                 return nr_irqs;
 164
 165         for (i = 0; i < nr_irqs; i++) {
 166                 int byte_offset, bit_nr;
 167                 u8 pendmask;
 168
 169                 byte_offset = intids[i] / BITS_PER_BYTE;
 170                 bit_nr = intids[i] % BITS_PER_BYTE;
 171
 172                 /*
 173                  * For contiguously allocated LPIs chances are we just read
 174                  * this very same byte in the last iteration. Reuse that.
 175                  */
 176                 if (byte_offset != last_byte_offset) {
 177                         ret = kvm_read_guest(vcpu->kvm, pendbase + byte_offset,
 178                                              &pendmask, 1);
 179                         if (ret) {
 180                                 kfree(intids);
 181                                 return ret;
 182                         }
 183                         last_byte_offset = byte_offset;
 184                 }
 185
 186                 irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
 187                 spin_lock(&irq->irq_lock);
 188                 irq->pending = pendmask & (1U << bit_nr);
 189                 vgic_queue_irq_unlock(vcpu->kvm, irq);
 190                 vgic_put_irq(vcpu->kvm, irq);
 191         }
 192
 193         kfree(intids);
 194
 195         return ret;
 196 }
 197
 198 static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
 199                                              struct vgic_its *its,
 200                                              gpa_t addr, unsigned int len)
 201 {
 202         u32 reg = 0;
 203
 204         mutex_lock(&its->cmd_lock);
 205         if (its->creadr == its->cwriter)
 206                 reg |= GITS_CTLR_QUIESCENT;
 207         if (its->enabled)
 208                 reg |= GITS_CTLR_ENABLE;
 209         mutex_unlock(&its->cmd_lock);
 210
 211         return reg;
 212 }
 213
 214 static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
 215                                      gpa_t addr, unsigned int len,
 216                                      unsigned long val)
 217 {
 218         its->enabled = !!(val & GITS_CTLR_ENABLE);
 219 }
 220
 221 static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
 222                                               struct vgic_its *its,
 223                                               gpa_t addr, unsigned int len)
 224 {
 225         u64 reg = GITS_TYPER_PLPIS;
 226
 227         /*
 228          * We use linear CPU numbers for redistributor addressing,
 229          * so GITS_TYPER.PTA is 0.
 230          * Also we force all PROPBASER registers to be the same, so
 231          * CommonLPIAff is 0 as well.
 232          * To avoid memory waste in the guest, we keep the number of IDBits and
 233          * DevBits low - as least for the time being.
 234          */
 235         reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
 236         reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
 237
 238         return extract_bytes(reg, addr & 7, len);
 239 }
 240
 241 static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
 242                                              struct vgic_its *its,
 243                                              gpa_t addr, unsigned int len)
 244 {
 245         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 246 }
 247
 248 static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
 249                                                struct vgic_its *its,
 250                                                gpa_t addr, unsigned int len)
 251 {
 252         switch (addr & 0xffff) {
 253         case GITS_PIDR0:
 254                 return 0x92;    /* part number, bits[7:0] */
 255         case GITS_PIDR1:
 256                 return 0xb4;    /* part number, bits[11:8] */
 257         case GITS_PIDR2:
 258                 return GIC_PIDR2_ARCH_GICv3 | 0x0b;
 259         case GITS_PIDR4:
 260                 return 0x40;    /* This is a 64K software visible page */
 261         /* The following are the ID registers for (any) GIC. */
 262         case GITS_CIDR0:
 263                 return 0x0d;
 264         case GITS_CIDR1:
 265                 return 0xf0;
 266         case GITS_CIDR2:
 267                 return 0x05;
 268         case GITS_CIDR3:
 269                 return 0xb1;
 270         }
 271
 272         return 0;
 273 }
 274
 275 /* Requires the its_lock to be held. */
 276 static void its_free_itte(struct kvm *kvm, struct its_itte *itte)
 277 {
 278         list_del(&itte->itte_list);
 279
 280         /* This put matches the get in vgic_add_lpi. */
 281         vgic_put_irq(kvm, itte->irq);
 282
 283         kfree(itte);
 284 }
 285
 286 static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
 287                                    u64 *its_cmd)
 288 {
 289         return -ENODEV;
 290 }
 291
 292 static u64 vgic_sanitise_its_baser(u64 reg)
 293 {
 294         reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
 295                                   GITS_BASER_SHAREABILITY_SHIFT,
 296                                   vgic_sanitise_shareability);
 297         reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
 298                                   GITS_BASER_INNER_CACHEABILITY_SHIFT,
 299                                   vgic_sanitise_inner_cacheability);
 300         reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
 301                                   GITS_BASER_OUTER_CACHEABILITY_SHIFT,
 302                                   vgic_sanitise_outer_cacheability);
 303
 304         /* Bits 15:12 contain bits 51:48 of the PA, which we don't support. */
 305         reg &= ~GENMASK_ULL(15, 12);
 306
 307         /* We support only one (ITS) page size: 64K */
 308         reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
 309
 310         return reg;
 311 }
 312
 313 static u64 vgic_sanitise_its_cbaser(u64 reg)
 314 {
 315         reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
 316                                   GITS_CBASER_SHAREABILITY_SHIFT,
 317                                   vgic_sanitise_shareability);
 318         reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
 319                                   GITS_CBASER_INNER_CACHEABILITY_SHIFT,
 320                                   vgic_sanitise_inner_cacheability);
 321         reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
 322                                   GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
 323                                   vgic_sanitise_outer_cacheability);
 324
 325         /*
 326          * Sanitise the physical address to be 64k aligned.
 327          * Also limit the physical addresses to 48 bits.
 328          */
 329         reg &= ~(GENMASK_ULL(51, 48) | GENMASK_ULL(15, 12));
 330
 331         return reg;
 332 }
 333
 334 static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
 335                                                struct vgic_its *its,
 336                                                gpa_t addr, unsigned int len)
 337 {
 338         return extract_bytes(its->cbaser, addr & 7, len);
 339 }
 340
 341 static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
 342                                        gpa_t addr, unsigned int len,
 343                                        unsigned long val)
 344 {
 345         /* When GITS_CTLR.Enable is 1, this register is RO. */
 346         if (its->enabled)
 347                 return;
 348
 349         mutex_lock(&its->cmd_lock);
 350         its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
 351         its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
 352         its->creadr = 0;
 353         /*
 354          * CWRITER is architecturally UNKNOWN on reset, but we need to reset
 355          * it to CREADR to make sure we start with an empty command buffer.
 356          */
 357         its->cwriter = its->creadr;
 358         mutex_unlock(&its->cmd_lock);
 359 }
 360
 361 #define ITS_CMD_BUFFER_SIZE(baser)      ((((baser) & 0xff) + 1) << 12)
 362 #define ITS_CMD_SIZE                    32
 363 #define ITS_CMD_OFFSET(reg)             ((reg) & GENMASK(19, 5))
 364
 365 /*
 366  * By writing to CWRITER the guest announces new commands to be processed.
 367  * To avoid any races in the first place, we take the its_cmd lock, which
 368  * protects our ring buffer variables, so that there is only one user
 369  * per ITS handling commands at a given time.
 370  */
 371 static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
 372                                         gpa_t addr, unsigned int len,
 373                                         unsigned long val)
 374 {
 375         gpa_t cbaser;
 376         u64 cmd_buf[4];
 377         u32 reg;
 378
 379         if (!its)
 380                 return;
 381
 382         mutex_lock(&its->cmd_lock);
 383
 384         reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
 385         reg = ITS_CMD_OFFSET(reg);
 386         if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
 387                 mutex_unlock(&its->cmd_lock);
 388                 return;
 389         }
 390
 391         its->cwriter = reg;
 392         cbaser = CBASER_ADDRESS(its->cbaser);
 393
 394         while (its->cwriter != its->creadr) {
 395                 int ret = kvm_read_guest(kvm, cbaser + its->creadr,
 396                                          cmd_buf, ITS_CMD_SIZE);
 397                 /*
 398                  * If kvm_read_guest() fails, this could be due to the guest
 399                  * programming a bogus value in CBASER or something else going
 400                  * wrong from which we cannot easily recover.
 401                  * According to section 6.3.2 in the GICv3 spec we can just
 402                  * ignore that command then.
 403                  */
 404                 if (!ret)
 405                         vgic_its_handle_command(kvm, its, cmd_buf);
 406
 407                 its->creadr += ITS_CMD_SIZE;
 408                 if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
 409                         its->creadr = 0;
 410         }
 411
 412         mutex_unlock(&its->cmd_lock);
 413 }
 414
 415 static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
 416                                                 struct vgic_its *its,
 417                                                 gpa_t addr, unsigned int len)
 418 {
 419         return extract_bytes(its->cwriter, addr & 0x7, len);
 420 }
 421
 422 static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
 423                                                struct vgic_its *its,
 424                                                gpa_t addr, unsigned int len)
 425 {
 426         return extract_bytes(its->creadr, addr & 0x7, len);
 427 }
 428
 429 #define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
 430 static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
 431                                               struct vgic_its *its,
 432                                               gpa_t addr, unsigned int len)
 433 {
 434         u64 reg;
 435
 436         switch (BASER_INDEX(addr)) {
 437         case 0:
 438                 reg = its->baser_device_table;
 439                 break;
 440         case 1:
 441                 reg = its->baser_coll_table;
 442                 break;
 443         default:
 444                 reg = 0;
 445                 break;
 446         }
 447
 448         return extract_bytes(reg, addr & 7, len);
 449 }
 450
 451 #define GITS_BASER_RO_MASK      (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
 452 static void vgic_mmio_write_its_baser(struct kvm *kvm,
 453                                       struct vgic_its *its,
 454                                       gpa_t addr, unsigned int len,
 455                                       unsigned long val)
 456 {
 457         u64 entry_size, device_type;
 458         u64 reg, *regptr, clearbits = 0;
 459
 460         /* When GITS_CTLR.Enable is 1, we ignore write accesses. */
 461         if (its->enabled)
 462                 return;
 463
 464         switch (BASER_INDEX(addr)) {
 465         case 0:
 466                 regptr = &its->baser_device_table;
 467                 entry_size = 8;
 468                 device_type = GITS_BASER_TYPE_DEVICE;
 469                 break;
 470         case 1:
 471                 regptr = &its->baser_coll_table;
 472                 entry_size = 8;
 473                 device_type = GITS_BASER_TYPE_COLLECTION;
 474                 clearbits = GITS_BASER_INDIRECT;
 475                 break;
 476         default:
 477                 return;
 478         }
 479
 480         reg = update_64bit_reg(*regptr, addr & 7, len, val);
 481         reg &= ~GITS_BASER_RO_MASK;
 482         reg &= ~clearbits;
 483
 484         reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
 485         reg |= device_type << GITS_BASER_TYPE_SHIFT;
 486         reg = vgic_sanitise_its_baser(reg);
 487
 488         *regptr = reg;
 489 }
 490
 491 #define REGISTER_ITS_DESC(off, rd, wr, length, acc)             \
 492 {                                                               \
 493         .reg_offset = off,                                      \
 494         .len = length,                                          \
 495         .access_flags = acc,                                    \
 496         .its_read = rd,                                         \
 497         .its_write = wr,                                        \
 498 }
 499
 500 static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
 501                               gpa_t addr, unsigned int len, unsigned long val)
 502 {
 503         /* Ignore */
 504 }
 505
 506 static struct vgic_register_region its_registers[] = {
 507         REGISTER_ITS_DESC(GITS_CTLR,
 508                 vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
 509                 VGIC_ACCESS_32bit),
 510         REGISTER_ITS_DESC(GITS_IIDR,
 511                 vgic_mmio_read_its_iidr, its_mmio_write_wi, 4,
 512                 VGIC_ACCESS_32bit),
 513         REGISTER_ITS_DESC(GITS_TYPER,
 514                 vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
 515                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 516         REGISTER_ITS_DESC(GITS_CBASER,
 517                 vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
 518                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 519         REGISTER_ITS_DESC(GITS_CWRITER,
 520                 vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
 521                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 522         REGISTER_ITS_DESC(GITS_CREADR,
 523                 vgic_mmio_read_its_creadr, its_mmio_write_wi, 8,
 524                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 525         REGISTER_ITS_DESC(GITS_BASER,
 526                 vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
 527                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 528         REGISTER_ITS_DESC(GITS_IDREGS_BASE,
 529                 vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
 530                 VGIC_ACCESS_32bit),
 531 };
 532
 533 /* This is called on setting the LPI enable bit in the redistributor. */
 534 void vgic_enable_lpis(struct kvm_vcpu *vcpu)
 535 {
 536         if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
 537                 its_sync_lpi_pending_table(vcpu);
 538 }
 539
 540 static int vgic_its_init_its(struct kvm *kvm, struct vgic_its *its)
 541 {
 542         struct vgic_io_device *iodev = &its->iodev;
 543         int ret;
 544
 545         if (its->initialized)
 546                 return 0;
 547
 548         if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base))
 549                 return -ENXIO;
 550
 551         iodev->regions = its_registers;
 552         iodev->nr_regions = ARRAY_SIZE(its_registers);
 553         kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
 554
 555         iodev->base_addr = its->vgic_its_base;
 556         iodev->iodev_type = IODEV_ITS;
 557         iodev->its = its;
 558         mutex_lock(&kvm->slots_lock);
 559         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
 560                                       KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
 561         mutex_unlock(&kvm->slots_lock);
 562
 563         if (!ret)
 564                 its->initialized = true;
 565
 566         return ret;
 567 }
 568
 569 #define INITIAL_BASER_VALUE                                               \
 570         (GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb)                | \
 571          GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner)         | \
 572          GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)             | \
 573          ((8ULL - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)                    | \
 574          GITS_BASER_PAGE_SIZE_64K)
 575
 576 #define INITIAL_PROPBASER_VALUE                                           \
 577         (GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb)            | \
 578          GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner)     | \
 579          GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
 580
 581 static int vgic_its_create(struct kvm_device *dev, u32 type)
 582 {
 583         struct vgic_its *its;
 584
 585         if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
 586                 return -ENODEV;
 587
 588         its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL);
 589         if (!its)
 590                 return -ENOMEM;
 591
 592         mutex_init(&its->its_lock);
 593         mutex_init(&its->cmd_lock);
 594
 595         its->vgic_its_base = VGIC_ADDR_UNDEF;
 596
 597         INIT_LIST_HEAD(&its->device_list);
 598         INIT_LIST_HEAD(&its->collection_list);
 599
 600         dev->kvm->arch.vgic.has_its = true;
 601         its->initialized = false;
 602         its->enabled = false;
 603
 604         its->baser_device_table = INITIAL_BASER_VALUE                   |
 605                 ((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
 606         its->baser_coll_table = INITIAL_BASER_VALUE |
 607                 ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
 608         dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
 609
 610         dev->private = its;
 611
 612         return 0;
 613 }
 614
 615 static void vgic_its_destroy(struct kvm_device *kvm_dev)
 616 {
 617         struct kvm *kvm = kvm_dev->kvm;
 618         struct vgic_its *its = kvm_dev->private;
 619         struct its_device *dev;
 620         struct its_itte *itte;
 621         struct list_head *dev_cur, *dev_temp;
 622         struct list_head *cur, *temp;
 623
 624         /*
 625          * We may end up here without the lists ever having been initialized.
 626          * Check this and bail out early to avoid dereferencing a NULL pointer.
 627          */
 628         if (!its->device_list.next)
 629                 return;
 630
 631         mutex_lock(&its->its_lock);
 632         list_for_each_safe(dev_cur, dev_temp, &its->device_list) {
 633                 dev = container_of(dev_cur, struct its_device, dev_list);
 634                 list_for_each_safe(cur, temp, &dev->itt_head) {
 635                         itte = (container_of(cur, struct its_itte, itte_list));
 636                         its_free_itte(kvm, itte);
 637                 }
 638                 list_del(dev_cur);
 639                 kfree(dev);
 640         }
 641
 642         list_for_each_safe(cur, temp, &its->collection_list) {
 643                 list_del(cur);
 644                 kfree(container_of(cur, struct its_collection, coll_list));
 645         }
 646         mutex_unlock(&its->its_lock);
 647
 648         kfree(its);
 649 }
 650
 651 static int vgic_its_has_attr(struct kvm_device *dev,
 652                              struct kvm_device_attr *attr)
 653 {
 654         switch (attr->group) {
 655         case KVM_DEV_ARM_VGIC_GRP_ADDR:
 656                 switch (attr->attr) {
 657                 case KVM_VGIC_ITS_ADDR_TYPE:
 658                         return 0;
 659                 }
 660                 break;
 661         case KVM_DEV_ARM_VGIC_GRP_CTRL:
 662                 switch (attr->attr) {
 663                 case KVM_DEV_ARM_VGIC_CTRL_INIT:
 664                         return 0;
 665                 }
 666                 break;
 667         }
 668         return -ENXIO;
 669 }
 670
 671 static int vgic_its_set_attr(struct kvm_device *dev,
 672                              struct kvm_device_attr *attr)
 673 {
 674         struct vgic_its *its = dev->private;
 675         int ret;
 676
 677         switch (attr->group) {
 678         case KVM_DEV_ARM_VGIC_GRP_ADDR: {
 679                 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
 680                 unsigned long type = (unsigned long)attr->attr;
 681                 u64 addr;
 682
 683                 if (type != KVM_VGIC_ITS_ADDR_TYPE)
 684                         return -ENODEV;
 685
 686                 if (its->initialized)
 687                         return -EBUSY;
 688
 689                 if (copy_from_user(&addr, uaddr, sizeof(addr)))
 690                         return -EFAULT;
 691
 692                 ret = vgic_check_ioaddr(dev->kvm, &its->vgic_its_base,
 693                                         addr, SZ_64K);
 694                 if (ret)
 695                         return ret;
 696
 697                 its->vgic_its_base = addr;
 698
 699                 return 0;
 700         }
 701         case KVM_DEV_ARM_VGIC_GRP_CTRL:
 702                 switch (attr->attr) {
 703                 case KVM_DEV_ARM_VGIC_CTRL_INIT:
 704                         return vgic_its_init_its(dev->kvm, its);
 705                 }
 706                 break;
 707         }
 708         return -ENXIO;
 709 }
 710
 711 static int vgic_its_get_attr(struct kvm_device *dev,
 712                              struct kvm_device_attr *attr)
 713 {
 714         switch (attr->group) {
 715         case KVM_DEV_ARM_VGIC_GRP_ADDR: {
 716                 struct vgic_its *its = dev->private;
 717                 u64 addr = its->vgic_its_base;
 718                 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
 719                 unsigned long type = (unsigned long)attr->attr;
 720
 721                 if (type != KVM_VGIC_ITS_ADDR_TYPE)
 722                         return -ENODEV;
 723
 724                 if (copy_to_user(uaddr, &addr, sizeof(addr)))
 725                         return -EFAULT;
 726                 break;
 727         default:
 728                 return -ENXIO;
 729         }
 730         }
 731
 732         return 0;
 733 }
 734
 735 static struct kvm_device_ops kvm_arm_vgic_its_ops = {
 736         .name = "kvm-arm-vgic-its",
 737         .create = vgic_its_create,
 738         .destroy = vgic_its_destroy,
 739         .set_attr = vgic_its_set_attr,
 740         .get_attr = vgic_its_get_attr,
 741         .has_attr = vgic_its_has_attr,
 742 };
 743
 744 int kvm_vgic_register_its_device(void)
 745 {
 746         return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
 747                                        KVM_DEV_TYPE_ARM_VGIC_ITS);
 748 }