virt/kvm/arm/vgic-v2.c

   1 /*
   2  * Copyright (C) 2012,2013 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/kvm.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/irqchip/arm-gic.h>
  28
  29 #include <asm/kvm_emulate.h>
  30 #include <asm/kvm_arm.h>
  31 #include <asm/kvm_mmu.h>
  32
  33 static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
  34 {
  35         struct vgic_lr lr_desc;
  36         u32 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr];
  37
  38         lr_desc.irq     = val & GICH_LR_VIRTUALID;
  39         if (lr_desc.irq <= 15)
  40                 lr_desc.source  = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
  41         else
  42                 lr_desc.source = 0;
  43         lr_desc.state   = 0;
  44
  45         if (val & GICH_LR_PENDING_BIT)
  46                 lr_desc.state |= LR_STATE_PENDING;
  47         if (val & GICH_LR_ACTIVE_BIT)
  48                 lr_desc.state |= LR_STATE_ACTIVE;
  49         if (val & GICH_LR_EOI)
  50                 lr_desc.state |= LR_EOI_INT;
  51
  52         return lr_desc;
  53 }
  54
  55 static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
  56                            struct vgic_lr lr_desc)
  57 {
  58         u32 lr_val = (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT) | lr_desc.irq;
  59
  60         if (lr_desc.state & LR_STATE_PENDING)
  61                 lr_val |= GICH_LR_PENDING_BIT;
  62         if (lr_desc.state & LR_STATE_ACTIVE)
  63                 lr_val |= GICH_LR_ACTIVE_BIT;
  64         if (lr_desc.state & LR_EOI_INT)
  65                 lr_val |= GICH_LR_EOI;
  66
  67         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;
  68 }
  69
  70 static void vgic_v2_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
  71                                   struct vgic_lr lr_desc)
  72 {
  73         if (!(lr_desc.state & LR_STATE_MASK))
  74                 vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr |= (1ULL << lr);
  75 }
  76
  77 static u64 vgic_v2_get_elrsr(const struct kvm_vcpu *vcpu)
  78 {
  79         return vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr;
  80 }
  81
  82 static u64 vgic_v2_get_eisr(const struct kvm_vcpu *vcpu)
  83 {
  84         return vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr;
  85 }
  86
  87 static u32 vgic_v2_get_interrupt_status(const struct kvm_vcpu *vcpu)
  88 {
  89         u32 misr = vcpu->arch.vgic_cpu.vgic_v2.vgic_misr;
  90         u32 ret = 0;
  91
  92         if (misr & GICH_MISR_EOI)
  93                 ret |= INT_STATUS_EOI;
  94         if (misr & GICH_MISR_U)
  95                 ret |= INT_STATUS_UNDERFLOW;
  96
  97         return ret;
  98 }
  99
 100 static void vgic_v2_enable_underflow(struct kvm_vcpu *vcpu)
 101 {
 102         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr |= GICH_HCR_UIE;
 103 }
 104
 105 static void vgic_v2_disable_underflow(struct kvm_vcpu *vcpu)
 106 {
 107         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
 108 }
 109
 110 static void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 111 {
 112         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
 113
 114         vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >> GICH_VMCR_CTRL_SHIFT;
 115         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >> GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 116         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >> GICH_VMCR_BINPOINT_SHIFT;
 117         vmcrp->pmr  = (vmcr & GICH_VMCR_PRIMASK_MASK) >> GICH_VMCR_PRIMASK_SHIFT;
 118 }
 119
 120 static void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 121 {
 122         u32 vmcr;
 123
 124         vmcr  = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
 125         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) & GICH_VMCR_ALIAS_BINPOINT_MASK;
 126         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) & GICH_VMCR_BINPOINT_MASK;
 127         vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 128
 129         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
 130 }
 131
 132 static void vgic_v2_enable(struct kvm_vcpu *vcpu)
 133 {
 134         /*
 135          * By forcing VMCR to zero, the GIC will restore the binary
 136          * points to their reset values. Anything else resets to zero
 137          * anyway.
 138          */
 139         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 140
 141         /* Get the show on the road... */
 142         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 143 }
 144
 145 static const struct vgic_ops vgic_v2_ops = {
 146         .get_lr                 = vgic_v2_get_lr,
 147         .set_lr                 = vgic_v2_set_lr,
 148         .sync_lr_elrsr          = vgic_v2_sync_lr_elrsr,
 149         .get_elrsr              = vgic_v2_get_elrsr,
 150         .get_eisr               = vgic_v2_get_eisr,
 151         .get_interrupt_status   = vgic_v2_get_interrupt_status,
 152         .enable_underflow       = vgic_v2_enable_underflow,
 153         .disable_underflow      = vgic_v2_disable_underflow,
 154         .get_vmcr               = vgic_v2_get_vmcr,
 155         .set_vmcr               = vgic_v2_set_vmcr,
 156         .enable                 = vgic_v2_enable,
 157 };
 158
 159 static struct vgic_params vgic_v2_params;
 160
 161 /**
 162  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 163  * @node:       pointer to the DT node
 164  * @ops:        address of a pointer to the GICv2 operations
 165  * @params:     address of a pointer to HW-specific parameters
 166  *
 167  * Returns 0 if a GICv2 has been found, with the low level operations
 168  * in *ops and the HW parameters in *params. Returns an error code
 169  * otherwise.
 170  */
 171 int vgic_v2_probe(struct device_node *vgic_node,
 172                   const struct vgic_ops **ops,
 173                   const struct vgic_params **params)
 174 {
 175         int ret;
 176         struct resource vctrl_res;
 177         struct resource vcpu_res;
 178         struct vgic_params *vgic = &vgic_v2_params;
 179
 180         vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
 181         if (!vgic->maint_irq) {
 182                 kvm_err("error getting vgic maintenance irq from DT\n");
 183                 ret = -ENXIO;
 184                 goto out;
 185         }
 186
 187         ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
 188         if (ret) {
 189                 kvm_err("Cannot obtain GICH resource\n");
 190                 goto out;
 191         }
 192
 193         vgic->vctrl_base = of_iomap(vgic_node, 2);
 194         if (!vgic->vctrl_base) {
 195                 kvm_err("Cannot ioremap GICH\n");
 196                 ret = -ENOMEM;
 197                 goto out;
 198         }
 199
 200         vgic->nr_lr = readl_relaxed(vgic->vctrl_base + GICH_VTR);
 201         vgic->nr_lr = (vgic->nr_lr & 0x3f) + 1;
 202
 203         ret = create_hyp_io_mappings(vgic->vctrl_base,
 204                                      vgic->vctrl_base + resource_size(&vctrl_res),
 205                                      vctrl_res.start);
 206         if (ret) {
 207                 kvm_err("Cannot map VCTRL into hyp\n");
 208                 goto out_unmap;
 209         }
 210
 211         if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
 212                 kvm_err("Cannot obtain GICV resource\n");
 213                 ret = -ENXIO;
 214                 goto out_unmap;
 215         }
 216
 217         if (!PAGE_ALIGNED(vcpu_res.start)) {
 218                 kvm_err("GICV physical address 0x%llx not page aligned\n",
 219                         (unsigned long long)vcpu_res.start);
 220                 ret = -ENXIO;
 221                 goto out_unmap;
 222         }
 223
 224         if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
 225                 kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 226                         (unsigned long long)resource_size(&vcpu_res),
 227                         PAGE_SIZE);
 228                 ret = -ENXIO;
 229                 goto out_unmap;
 230         }
 231
 232         vgic->can_emulate_gicv2 = true;
 233         kvm_register_device_ops(&kvm_arm_vgic_v2_ops, KVM_DEV_TYPE_ARM_VGIC_V2);
 234
 235         vgic->vcpu_base = vcpu_res.start;
 236
 237         kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
 238                  vctrl_res.start, vgic->maint_irq);
 239
 240         vgic->type = VGIC_V2;
 241         vgic->max_gic_vcpus = VGIC_V2_MAX_CPUS;
 242         *ops = &vgic_v2_ops;
 243         *params = vgic;
 244         goto out;
 245
 246 out_unmap:
 247         iounmap(vgic->vctrl_base);
 248 out:
 249         of_node_put(vgic_node);
 250         return ret;
 251 }