2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/rculist.h>
28 #include <linux/uaccess.h>
30 #include <asm/kvm_emulate.h>
31 #include <asm/kvm_arm.h>
32 #include <asm/kvm_mmu.h>
33 #include <trace/events/kvm.h>
35 #include <kvm/iodev.h>
38 * How the whole thing works (courtesy of Christoffer Dall):
40 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
41 * something is pending on the CPU interface.
42 * - Interrupts that are pending on the distributor are stored on the
43 * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
44 * ioctls and guest mmio ops, and other in-kernel peripherals such as the
46 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
48 * - To calculate the oracle, we need info for each cpu from
49 * compute_pending_for_cpu, which considers:
50 * - PPI: dist->irq_pending & dist->irq_enable
51 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
52 * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
53 * registers, stored on each vcpu. We only keep one bit of
54 * information per interrupt, making sure that only one vcpu can
55 * accept the interrupt.
56 * - If any of the above state changes, we must recalculate the oracle.
57 * - The same is true when injecting an interrupt, except that we only
58 * consider a single interrupt at a time. The irq_spi_cpu array
59 * contains the target CPU for each SPI.
61 * The handling of level interrupts adds some extra complexity. We
62 * need to track when the interrupt has been EOIed, so we can sample
63 * the 'line' again. This is achieved as such:
65 * - When a level interrupt is moved onto a vcpu, the corresponding
66 * bit in irq_queued is set. As long as this bit is set, the line
67 * will be ignored for further interrupts. The interrupt is injected
68 * into the vcpu with the GICH_LR_EOI bit set (generate a
69 * maintenance interrupt on EOI).
70 * - When the interrupt is EOIed, the maintenance interrupt fires,
71 * and clears the corresponding bit in irq_queued. This allows the
72 * interrupt line to be sampled again.
73 * - Note that level-triggered interrupts can also be set to pending from
74 * writes to GICD_ISPENDRn and lowering the external input line does not
75 * cause the interrupt to become inactive in such a situation.
76 * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
77 * inactive as long as the external input line is held high.
80 * Initialization rules: there are multiple stages to the vgic
81 * initialization, both for the distributor and the CPU interfaces.
85 * - kvm_vgic_early_init(): initialization of static data that doesn't
86 * depend on any sizing information or emulation type. No allocation
89 * - vgic_init(): allocation and initialization of the generic data
90 * structures that depend on sizing information (number of CPUs,
91 * number of interrupts). Also initializes the vcpu specific data
92 * structures. Can be executed lazily for GICv2.
93 * [to be renamed to kvm_vgic_init??]
97 * - kvm_vgic_cpu_early_init(): initialization of static data that
98 * doesn't depend on any sizing information or emulation type. No
99 * allocation is allowed there.
104 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
);
105 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
);
106 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
);
107 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr lr_desc
);
108 static struct irq_phys_map
*vgic_irq_map_search(struct kvm_vcpu
*vcpu
,
111 static const struct vgic_ops
*vgic_ops
;
112 static const struct vgic_params
*vgic
;
114 static void add_sgi_source(struct kvm_vcpu
*vcpu
, int irq
, int source
)
116 vcpu
->kvm
->arch
.vgic
.vm_ops
.add_sgi_source(vcpu
, irq
, source
);
119 static bool queue_sgi(struct kvm_vcpu
*vcpu
, int irq
)
121 return vcpu
->kvm
->arch
.vgic
.vm_ops
.queue_sgi(vcpu
, irq
);
124 int kvm_vgic_map_resources(struct kvm
*kvm
)
126 return kvm
->arch
.vgic
.vm_ops
.map_resources(kvm
, vgic
);
130 * struct vgic_bitmap contains a bitmap made of unsigned longs, but
131 * extracts u32s out of them.
133 * This does not work on 64-bit BE systems, because the bitmap access
134 * will store two consecutive 32-bit words with the higher-addressed
135 * register's bits at the lower index and the lower-addressed register's
136 * bits at the higher index.
138 * Therefore, swizzle the register index when accessing the 32-bit word
139 * registers to access the right register's value.
141 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
142 #define REG_OFFSET_SWIZZLE 1
144 #define REG_OFFSET_SWIZZLE 0
147 static int vgic_init_bitmap(struct vgic_bitmap
*b
, int nr_cpus
, int nr_irqs
)
151 nr_longs
= nr_cpus
+ BITS_TO_LONGS(nr_irqs
- VGIC_NR_PRIVATE_IRQS
);
153 b
->private = kzalloc(sizeof(unsigned long) * nr_longs
, GFP_KERNEL
);
157 b
->shared
= b
->private + nr_cpus
;
162 static void vgic_free_bitmap(struct vgic_bitmap
*b
)
170 * Call this function to convert a u64 value to an unsigned long * bitmask
171 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
173 * Warning: Calling this function may modify *val.
175 static unsigned long *u64_to_bitmask(u64
*val
)
177 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
178 *val
= (*val
>> 32) | (*val
<< 32);
180 return (unsigned long *)val
;
183 u32
*vgic_bitmap_get_reg(struct vgic_bitmap
*x
, int cpuid
, u32 offset
)
187 return (u32
*)(x
->private + cpuid
) + REG_OFFSET_SWIZZLE
;
189 return (u32
*)(x
->shared
) + ((offset
- 1) ^ REG_OFFSET_SWIZZLE
);
192 static int vgic_bitmap_get_irq_val(struct vgic_bitmap
*x
,
195 if (irq
< VGIC_NR_PRIVATE_IRQS
)
196 return test_bit(irq
, x
->private + cpuid
);
198 return test_bit(irq
- VGIC_NR_PRIVATE_IRQS
, x
->shared
);
201 void vgic_bitmap_set_irq_val(struct vgic_bitmap
*x
, int cpuid
,
206 if (irq
< VGIC_NR_PRIVATE_IRQS
) {
207 reg
= x
->private + cpuid
;
210 irq
-= VGIC_NR_PRIVATE_IRQS
;
219 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap
*x
, int cpuid
)
221 return x
->private + cpuid
;
224 unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap
*x
)
229 static int vgic_init_bytemap(struct vgic_bytemap
*x
, int nr_cpus
, int nr_irqs
)
233 size
= nr_cpus
* VGIC_NR_PRIVATE_IRQS
;
234 size
+= nr_irqs
- VGIC_NR_PRIVATE_IRQS
;
236 x
->private = kzalloc(size
, GFP_KERNEL
);
240 x
->shared
= x
->private + nr_cpus
* VGIC_NR_PRIVATE_IRQS
/ sizeof(u32
);
244 static void vgic_free_bytemap(struct vgic_bytemap
*b
)
251 u32
*vgic_bytemap_get_reg(struct vgic_bytemap
*x
, int cpuid
, u32 offset
)
255 if (offset
< VGIC_NR_PRIVATE_IRQS
) {
257 offset
+= cpuid
* VGIC_NR_PRIVATE_IRQS
;
260 offset
-= VGIC_NR_PRIVATE_IRQS
;
263 return reg
+ (offset
/ sizeof(u32
));
266 #define VGIC_CFG_LEVEL 0
267 #define VGIC_CFG_EDGE 1
269 static bool vgic_irq_is_edge(struct kvm_vcpu
*vcpu
, int irq
)
271 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
274 irq_val
= vgic_bitmap_get_irq_val(&dist
->irq_cfg
, vcpu
->vcpu_id
, irq
);
275 return irq_val
== VGIC_CFG_EDGE
;
278 static int vgic_irq_is_enabled(struct kvm_vcpu
*vcpu
, int irq
)
280 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
282 return vgic_bitmap_get_irq_val(&dist
->irq_enabled
, vcpu
->vcpu_id
, irq
);
285 static int vgic_irq_is_queued(struct kvm_vcpu
*vcpu
, int irq
)
287 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
289 return vgic_bitmap_get_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
);
292 static int vgic_irq_is_active(struct kvm_vcpu
*vcpu
, int irq
)
294 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
296 return vgic_bitmap_get_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
);
299 static void vgic_irq_set_queued(struct kvm_vcpu
*vcpu
, int irq
)
301 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
303 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 1);
306 static void vgic_irq_clear_queued(struct kvm_vcpu
*vcpu
, int irq
)
308 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
310 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 0);
313 static void vgic_irq_set_active(struct kvm_vcpu
*vcpu
, int irq
)
315 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
317 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 1);
320 static void vgic_irq_clear_active(struct kvm_vcpu
*vcpu
, int irq
)
322 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
324 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 0);
327 static int vgic_dist_irq_get_level(struct kvm_vcpu
*vcpu
, int irq
)
329 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
331 return vgic_bitmap_get_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
);
334 static void vgic_dist_irq_set_level(struct kvm_vcpu
*vcpu
, int irq
)
336 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
338 vgic_bitmap_set_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
, 1);
341 static void vgic_dist_irq_clear_level(struct kvm_vcpu
*vcpu
, int irq
)
343 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
345 vgic_bitmap_set_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
, 0);
348 static int vgic_dist_irq_soft_pend(struct kvm_vcpu
*vcpu
, int irq
)
350 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
352 return vgic_bitmap_get_irq_val(&dist
->irq_soft_pend
, vcpu
->vcpu_id
, irq
);
355 static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu
*vcpu
, int irq
)
357 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
359 vgic_bitmap_set_irq_val(&dist
->irq_soft_pend
, vcpu
->vcpu_id
, irq
, 0);
362 static int vgic_dist_irq_is_pending(struct kvm_vcpu
*vcpu
, int irq
)
364 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
366 return vgic_bitmap_get_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
);
369 void vgic_dist_irq_set_pending(struct kvm_vcpu
*vcpu
, int irq
)
371 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
373 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 1);
376 void vgic_dist_irq_clear_pending(struct kvm_vcpu
*vcpu
, int irq
)
378 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
380 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 0);
383 static void vgic_cpu_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
385 if (irq
< VGIC_NR_PRIVATE_IRQS
)
386 set_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
388 set_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
389 vcpu
->arch
.vgic_cpu
.pending_shared
);
392 void vgic_cpu_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
394 if (irq
< VGIC_NR_PRIVATE_IRQS
)
395 clear_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
397 clear_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
398 vcpu
->arch
.vgic_cpu
.pending_shared
);
401 static bool vgic_can_sample_irq(struct kvm_vcpu
*vcpu
, int irq
)
403 return !vgic_irq_is_queued(vcpu
, irq
);
407 * vgic_reg_access - access vgic register
408 * @mmio: pointer to the data describing the mmio access
409 * @reg: pointer to the virtual backing of vgic distributor data
410 * @offset: least significant 2 bits used for word offset
411 * @mode: ACCESS_ mode (see defines above)
413 * Helper to make vgic register access easier using one of the access
414 * modes defined for vgic register access
415 * (read,raz,write-ignored,setbit,clearbit,write)
417 void vgic_reg_access(struct kvm_exit_mmio
*mmio
, u32
*reg
,
418 phys_addr_t offset
, int mode
)
420 int word_offset
= (offset
& 3) * 8;
421 u32 mask
= (1UL << (mmio
->len
* 8)) - 1;
425 * Any alignment fault should have been delivered to the guest
426 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
432 BUG_ON(mode
!= (ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
));
436 if (mmio
->is_write
) {
437 u32 data
= mmio_data_read(mmio
, mask
) << word_offset
;
438 switch (ACCESS_WRITE_MASK(mode
)) {
439 case ACCESS_WRITE_IGNORED
:
442 case ACCESS_WRITE_SETBIT
:
446 case ACCESS_WRITE_CLEARBIT
:
450 case ACCESS_WRITE_VALUE
:
451 regval
= (regval
& ~(mask
<< word_offset
)) | data
;
456 switch (ACCESS_READ_MASK(mode
)) {
457 case ACCESS_READ_RAZ
:
461 case ACCESS_READ_VALUE
:
462 mmio_data_write(mmio
, mask
, regval
>> word_offset
);
467 bool handle_mmio_raz_wi(struct kvm_vcpu
*vcpu
, struct kvm_exit_mmio
*mmio
,
470 vgic_reg_access(mmio
, NULL
, offset
,
471 ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
);
475 bool vgic_handle_enable_reg(struct kvm
*kvm
, struct kvm_exit_mmio
*mmio
,
476 phys_addr_t offset
, int vcpu_id
, int access
)
479 int mode
= ACCESS_READ_VALUE
| access
;
480 struct kvm_vcpu
*target_vcpu
= kvm_get_vcpu(kvm
, vcpu_id
);
482 reg
= vgic_bitmap_get_reg(&kvm
->arch
.vgic
.irq_enabled
, vcpu_id
, offset
);
483 vgic_reg_access(mmio
, reg
, offset
, mode
);
484 if (mmio
->is_write
) {
485 if (access
& ACCESS_WRITE_CLEARBIT
) {
486 if (offset
< 4) /* Force SGI enabled */
488 vgic_retire_disabled_irqs(target_vcpu
);
490 vgic_update_state(kvm
);
497 bool vgic_handle_set_pending_reg(struct kvm
*kvm
,
498 struct kvm_exit_mmio
*mmio
,
499 phys_addr_t offset
, int vcpu_id
)
503 int mode
= ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
;
504 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
506 reg
= vgic_bitmap_get_reg(&dist
->irq_cfg
, vcpu_id
, offset
);
507 level_mask
= (~(*reg
));
509 /* Mark both level and edge triggered irqs as pending */
510 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
512 vgic_reg_access(mmio
, reg
, offset
, mode
);
514 if (mmio
->is_write
) {
515 /* Set the soft-pending flag only for level-triggered irqs */
516 reg
= vgic_bitmap_get_reg(&dist
->irq_soft_pend
,
518 vgic_reg_access(mmio
, reg
, offset
, mode
);
521 /* Ignore writes to SGIs */
524 *reg
|= orig
& 0xffff;
527 vgic_update_state(kvm
);
535 * If a mapped interrupt's state has been modified by the guest such that it
536 * is no longer active or pending, without it have gone through the sync path,
537 * then the map->active field must be cleared so the interrupt can be taken
540 static void vgic_handle_clear_mapped_irq(struct kvm_vcpu
*vcpu
)
542 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
543 struct list_head
*root
;
544 struct irq_phys_map_entry
*entry
;
545 struct irq_phys_map
*map
;
550 root
= &vgic_cpu
->irq_phys_map_list
;
551 list_for_each_entry_rcu(entry
, root
, entry
) {
554 if (!vgic_dist_irq_is_pending(vcpu
, map
->virt_irq
) &&
555 !vgic_irq_is_active(vcpu
, map
->virt_irq
))
562 bool vgic_handle_clear_pending_reg(struct kvm
*kvm
,
563 struct kvm_exit_mmio
*mmio
,
564 phys_addr_t offset
, int vcpu_id
)
568 int mode
= ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
;
569 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
571 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
573 vgic_reg_access(mmio
, reg
, offset
, mode
);
574 if (mmio
->is_write
) {
575 /* Re-set level triggered level-active interrupts */
576 level_active
= vgic_bitmap_get_reg(&dist
->irq_level
,
578 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
579 *reg
|= *level_active
;
581 /* Ignore writes to SGIs */
584 *reg
|= orig
& 0xffff;
587 /* Clear soft-pending flags */
588 reg
= vgic_bitmap_get_reg(&dist
->irq_soft_pend
,
590 vgic_reg_access(mmio
, reg
, offset
, mode
);
592 vgic_handle_clear_mapped_irq(kvm_get_vcpu(kvm
, vcpu_id
));
593 vgic_update_state(kvm
);
599 bool vgic_handle_set_active_reg(struct kvm
*kvm
,
600 struct kvm_exit_mmio
*mmio
,
601 phys_addr_t offset
, int vcpu_id
)
604 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
606 reg
= vgic_bitmap_get_reg(&dist
->irq_active
, vcpu_id
, offset
);
607 vgic_reg_access(mmio
, reg
, offset
,
608 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
610 if (mmio
->is_write
) {
611 vgic_update_state(kvm
);
618 bool vgic_handle_clear_active_reg(struct kvm
*kvm
,
619 struct kvm_exit_mmio
*mmio
,
620 phys_addr_t offset
, int vcpu_id
)
623 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
625 reg
= vgic_bitmap_get_reg(&dist
->irq_active
, vcpu_id
, offset
);
626 vgic_reg_access(mmio
, reg
, offset
,
627 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
629 if (mmio
->is_write
) {
630 vgic_handle_clear_mapped_irq(kvm_get_vcpu(kvm
, vcpu_id
));
631 vgic_update_state(kvm
);
638 static u32
vgic_cfg_expand(u16 val
)
644 * Turn a 16bit value like abcd...mnop into a 32bit word
645 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
647 for (i
= 0; i
< 16; i
++)
648 res
|= ((val
>> i
) & VGIC_CFG_EDGE
) << (2 * i
+ 1);
653 static u16
vgic_cfg_compress(u32 val
)
659 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
660 * abcd...mnop which is what we really care about.
662 for (i
= 0; i
< 16; i
++)
663 res
|= ((val
>> (i
* 2 + 1)) & VGIC_CFG_EDGE
) << i
;
669 * The distributor uses 2 bits per IRQ for the CFG register, but the
670 * LSB is always 0. As such, we only keep the upper bit, and use the
671 * two above functions to compress/expand the bits
673 bool vgic_handle_cfg_reg(u32
*reg
, struct kvm_exit_mmio
*mmio
,
683 val
= vgic_cfg_expand(val
);
684 vgic_reg_access(mmio
, &val
, offset
,
685 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
686 if (mmio
->is_write
) {
688 *reg
= ~0U; /* Force PPIs/SGIs to 1 */
692 val
= vgic_cfg_compress(val
);
697 *reg
&= 0xffff << 16;
706 * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor
707 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
709 * Move any IRQs that have already been assigned to LRs back to the
710 * emulated distributor state so that the complete emulated state can be read
711 * from the main emulation structures without investigating the LRs.
713 void vgic_unqueue_irqs(struct kvm_vcpu
*vcpu
)
715 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
718 for_each_set_bit(i
, vgic_cpu
->lr_used
, vgic_cpu
->nr_lr
) {
719 struct vgic_lr lr
= vgic_get_lr(vcpu
, i
);
722 * There are three options for the state bits:
726 * 11: pending and active
728 BUG_ON(!(lr
.state
& LR_STATE_MASK
));
730 /* Reestablish SGI source for pending and active IRQs */
731 if (lr
.irq
< VGIC_NR_SGIS
)
732 add_sgi_source(vcpu
, lr
.irq
, lr
.source
);
735 * If the LR holds an active (10) or a pending and active (11)
736 * interrupt then move the active state to the
737 * distributor tracking bit.
739 if (lr
.state
& LR_STATE_ACTIVE
) {
740 vgic_irq_set_active(vcpu
, lr
.irq
);
741 lr
.state
&= ~LR_STATE_ACTIVE
;
745 * Reestablish the pending state on the distributor and the
746 * CPU interface. It may have already been pending, but that
747 * is fine, then we are only setting a few bits that were
750 if (lr
.state
& LR_STATE_PENDING
) {
751 vgic_dist_irq_set_pending(vcpu
, lr
.irq
);
752 lr
.state
&= ~LR_STATE_PENDING
;
755 vgic_set_lr(vcpu
, i
, lr
);
758 * Mark the LR as free for other use.
760 BUG_ON(lr
.state
& LR_STATE_MASK
);
761 vgic_retire_lr(i
, lr
.irq
, vcpu
);
762 vgic_irq_clear_queued(vcpu
, lr
.irq
);
764 /* Finally update the VGIC state. */
765 vgic_update_state(vcpu
->kvm
);
770 struct vgic_io_range
*vgic_find_range(const struct vgic_io_range
*ranges
,
771 int len
, gpa_t offset
)
773 while (ranges
->len
) {
774 if (offset
>= ranges
->base
&&
775 (offset
+ len
) <= (ranges
->base
+ ranges
->len
))
783 static bool vgic_validate_access(const struct vgic_dist
*dist
,
784 const struct vgic_io_range
*range
,
785 unsigned long offset
)
789 if (!range
->bits_per_irq
)
790 return true; /* Not an irq-based access */
792 irq
= offset
* 8 / range
->bits_per_irq
;
793 if (irq
>= dist
->nr_irqs
)
800 * Call the respective handler function for the given range.
801 * We split up any 64 bit accesses into two consecutive 32 bit
802 * handler calls and merge the result afterwards.
803 * We do this in a little endian fashion regardless of the host's
804 * or guest's endianness, because the GIC is always LE and the rest of
805 * the code (vgic_reg_access) also puts it in a LE fashion already.
806 * At this point we have already identified the handle function, so
807 * range points to that one entry and offset is relative to this.
809 static bool call_range_handler(struct kvm_vcpu
*vcpu
,
810 struct kvm_exit_mmio
*mmio
,
811 unsigned long offset
,
812 const struct vgic_io_range
*range
)
814 struct kvm_exit_mmio mmio32
;
817 if (likely(mmio
->len
<= 4))
818 return range
->handle_mmio(vcpu
, mmio
, offset
);
821 * Any access bigger than 4 bytes (that we currently handle in KVM)
822 * is actually 8 bytes long, caused by a 64-bit access
826 mmio32
.is_write
= mmio
->is_write
;
827 mmio32
.private = mmio
->private;
829 mmio32
.phys_addr
= mmio
->phys_addr
+ 4;
830 mmio32
.data
= &((u32
*)mmio
->data
)[1];
831 ret
= range
->handle_mmio(vcpu
, &mmio32
, offset
+ 4);
833 mmio32
.phys_addr
= mmio
->phys_addr
;
834 mmio32
.data
= &((u32
*)mmio
->data
)[0];
835 ret
|= range
->handle_mmio(vcpu
, &mmio32
, offset
);
841 * vgic_handle_mmio_access - handle an in-kernel MMIO access
842 * This is called by the read/write KVM IO device wrappers below.
843 * @vcpu: pointer to the vcpu performing the access
844 * @this: pointer to the KVM IO device in charge
845 * @addr: guest physical address of the access
846 * @len: size of the access
847 * @val: pointer to the data region
848 * @is_write: read or write access
850 * returns true if the MMIO access could be performed
852 static int vgic_handle_mmio_access(struct kvm_vcpu
*vcpu
,
853 struct kvm_io_device
*this, gpa_t addr
,
854 int len
, void *val
, bool is_write
)
856 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
857 struct vgic_io_device
*iodev
= container_of(this,
858 struct vgic_io_device
, dev
);
859 struct kvm_run
*run
= vcpu
->run
;
860 const struct vgic_io_range
*range
;
861 struct kvm_exit_mmio mmio
;
865 offset
= addr
- iodev
->addr
;
866 range
= vgic_find_range(iodev
->reg_ranges
, len
, offset
);
867 if (unlikely(!range
|| !range
->handle_mmio
)) {
868 pr_warn("Unhandled access %d %08llx %d\n", is_write
, addr
, len
);
872 mmio
.phys_addr
= addr
;
874 mmio
.is_write
= is_write
;
876 mmio
.private = iodev
->redist_vcpu
;
878 spin_lock(&dist
->lock
);
879 offset
-= range
->base
;
880 if (vgic_validate_access(dist
, range
, offset
)) {
881 updated_state
= call_range_handler(vcpu
, &mmio
, offset
, range
);
885 updated_state
= false;
887 spin_unlock(&dist
->lock
);
888 run
->mmio
.is_write
= is_write
;
890 run
->mmio
.phys_addr
= addr
;
891 memcpy(run
->mmio
.data
, val
, len
);
893 kvm_handle_mmio_return(vcpu
, run
);
896 vgic_kick_vcpus(vcpu
->kvm
);
901 static int vgic_handle_mmio_read(struct kvm_vcpu
*vcpu
,
902 struct kvm_io_device
*this,
903 gpa_t addr
, int len
, void *val
)
905 return vgic_handle_mmio_access(vcpu
, this, addr
, len
, val
, false);
908 static int vgic_handle_mmio_write(struct kvm_vcpu
*vcpu
,
909 struct kvm_io_device
*this,
910 gpa_t addr
, int len
, const void *val
)
912 return vgic_handle_mmio_access(vcpu
, this, addr
, len
, (void *)val
,
916 struct kvm_io_device_ops vgic_io_ops
= {
917 .read
= vgic_handle_mmio_read
,
918 .write
= vgic_handle_mmio_write
,
922 * vgic_register_kvm_io_dev - register VGIC register frame on the KVM I/O bus
923 * @kvm: The VM structure pointer
924 * @base: The (guest) base address for the register frame
925 * @len: Length of the register frame window
926 * @ranges: Describing the handler functions for each register
927 * @redist_vcpu_id: The VCPU ID to pass on to the handlers on call
928 * @iodev: Points to memory to be passed on to the handler
930 * @iodev stores the parameters of this function to be usable by the handler
931 * respectively the dispatcher function (since the KVM I/O bus framework lacks
932 * an opaque parameter). Initialization is done in this function, but the
933 * reference should be valid and unique for the whole VGIC lifetime.
934 * If the register frame is not mapped for a specific VCPU, pass -1 to
937 int vgic_register_kvm_io_dev(struct kvm
*kvm
, gpa_t base
, int len
,
938 const struct vgic_io_range
*ranges
,
940 struct vgic_io_device
*iodev
)
942 struct kvm_vcpu
*vcpu
= NULL
;
945 if (redist_vcpu_id
>= 0)
946 vcpu
= kvm_get_vcpu(kvm
, redist_vcpu_id
);
950 iodev
->reg_ranges
= ranges
;
951 iodev
->redist_vcpu
= vcpu
;
953 kvm_iodevice_init(&iodev
->dev
, &vgic_io_ops
);
955 mutex_lock(&kvm
->slots_lock
);
957 ret
= kvm_io_bus_register_dev(kvm
, KVM_MMIO_BUS
, base
, len
,
959 mutex_unlock(&kvm
->slots_lock
);
961 /* Mark the iodev as invalid if registration fails. */
963 iodev
->dev
.ops
= NULL
;
968 static int vgic_nr_shared_irqs(struct vgic_dist
*dist
)
970 return dist
->nr_irqs
- VGIC_NR_PRIVATE_IRQS
;
973 static int compute_active_for_cpu(struct kvm_vcpu
*vcpu
)
975 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
976 unsigned long *active
, *enabled
, *act_percpu
, *act_shared
;
977 unsigned long active_private
, active_shared
;
978 int nr_shared
= vgic_nr_shared_irqs(dist
);
981 vcpu_id
= vcpu
->vcpu_id
;
982 act_percpu
= vcpu
->arch
.vgic_cpu
.active_percpu
;
983 act_shared
= vcpu
->arch
.vgic_cpu
.active_shared
;
985 active
= vgic_bitmap_get_cpu_map(&dist
->irq_active
, vcpu_id
);
986 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
987 bitmap_and(act_percpu
, active
, enabled
, VGIC_NR_PRIVATE_IRQS
);
989 active
= vgic_bitmap_get_shared_map(&dist
->irq_active
);
990 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
991 bitmap_and(act_shared
, active
, enabled
, nr_shared
);
992 bitmap_and(act_shared
, act_shared
,
993 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
996 active_private
= find_first_bit(act_percpu
, VGIC_NR_PRIVATE_IRQS
);
997 active_shared
= find_first_bit(act_shared
, nr_shared
);
999 return (active_private
< VGIC_NR_PRIVATE_IRQS
||
1000 active_shared
< nr_shared
);
1003 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
)
1005 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1006 unsigned long *pending
, *enabled
, *pend_percpu
, *pend_shared
;
1007 unsigned long pending_private
, pending_shared
;
1008 int nr_shared
= vgic_nr_shared_irqs(dist
);
1011 vcpu_id
= vcpu
->vcpu_id
;
1012 pend_percpu
= vcpu
->arch
.vgic_cpu
.pending_percpu
;
1013 pend_shared
= vcpu
->arch
.vgic_cpu
.pending_shared
;
1015 if (!dist
->enabled
) {
1016 bitmap_zero(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
1017 bitmap_zero(pend_shared
, nr_shared
);
1021 pending
= vgic_bitmap_get_cpu_map(&dist
->irq_pending
, vcpu_id
);
1022 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
1023 bitmap_and(pend_percpu
, pending
, enabled
, VGIC_NR_PRIVATE_IRQS
);
1025 pending
= vgic_bitmap_get_shared_map(&dist
->irq_pending
);
1026 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
1027 bitmap_and(pend_shared
, pending
, enabled
, nr_shared
);
1028 bitmap_and(pend_shared
, pend_shared
,
1029 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
1032 pending_private
= find_first_bit(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
1033 pending_shared
= find_first_bit(pend_shared
, nr_shared
);
1034 return (pending_private
< VGIC_NR_PRIVATE_IRQS
||
1035 pending_shared
< vgic_nr_shared_irqs(dist
));
1039 * Update the interrupt state and determine which CPUs have pending
1040 * or active interrupts. Must be called with distributor lock held.
1042 void vgic_update_state(struct kvm
*kvm
)
1044 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1045 struct kvm_vcpu
*vcpu
;
1048 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1049 if (compute_pending_for_cpu(vcpu
))
1050 set_bit(c
, dist
->irq_pending_on_cpu
);
1052 if (compute_active_for_cpu(vcpu
))
1053 set_bit(c
, dist
->irq_active_on_cpu
);
1055 clear_bit(c
, dist
->irq_active_on_cpu
);
1059 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
)
1061 return vgic_ops
->get_lr(vcpu
, lr
);
1064 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
,
1067 vgic_ops
->set_lr(vcpu
, lr
, vlr
);
1070 static void vgic_sync_lr_elrsr(struct kvm_vcpu
*vcpu
, int lr
,
1073 vgic_ops
->sync_lr_elrsr(vcpu
, lr
, vlr
);
1076 static inline u64
vgic_get_elrsr(struct kvm_vcpu
*vcpu
)
1078 return vgic_ops
->get_elrsr(vcpu
);
1081 static inline u64
vgic_get_eisr(struct kvm_vcpu
*vcpu
)
1083 return vgic_ops
->get_eisr(vcpu
);
1086 static inline void vgic_clear_eisr(struct kvm_vcpu
*vcpu
)
1088 vgic_ops
->clear_eisr(vcpu
);
1091 static inline u32
vgic_get_interrupt_status(struct kvm_vcpu
*vcpu
)
1093 return vgic_ops
->get_interrupt_status(vcpu
);
1096 static inline void vgic_enable_underflow(struct kvm_vcpu
*vcpu
)
1098 vgic_ops
->enable_underflow(vcpu
);
1101 static inline void vgic_disable_underflow(struct kvm_vcpu
*vcpu
)
1103 vgic_ops
->disable_underflow(vcpu
);
1106 void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1108 vgic_ops
->get_vmcr(vcpu
, vmcr
);
1111 void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1113 vgic_ops
->set_vmcr(vcpu
, vmcr
);
1116 static inline void vgic_enable(struct kvm_vcpu
*vcpu
)
1118 vgic_ops
->enable(vcpu
);
1121 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
)
1123 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1124 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr_nr
);
1127 * We must transfer the pending state back to the distributor before
1128 * retiring the LR, otherwise we may loose edge-triggered interrupts.
1130 if (vlr
.state
& LR_STATE_PENDING
) {
1131 vgic_dist_irq_set_pending(vcpu
, irq
);
1136 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1137 clear_bit(lr_nr
, vgic_cpu
->lr_used
);
1138 vgic_cpu
->vgic_irq_lr_map
[irq
] = LR_EMPTY
;
1139 vgic_sync_lr_elrsr(vcpu
, lr_nr
, vlr
);
1143 * An interrupt may have been disabled after being made pending on the
1144 * CPU interface (the classic case is a timer running while we're
1145 * rebooting the guest - the interrupt would kick as soon as the CPU
1146 * interface gets enabled, with deadly consequences).
1148 * The solution is to examine already active LRs, and check the
1149 * interrupt is still enabled. If not, just retire it.
1151 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
)
1153 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1156 for_each_set_bit(lr
, vgic_cpu
->lr_used
, vgic
->nr_lr
) {
1157 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1159 if (!vgic_irq_is_enabled(vcpu
, vlr
.irq
)) {
1160 vgic_retire_lr(lr
, vlr
.irq
, vcpu
);
1161 if (vgic_irq_is_queued(vcpu
, vlr
.irq
))
1162 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1167 static void vgic_queue_irq_to_lr(struct kvm_vcpu
*vcpu
, int irq
,
1168 int lr_nr
, struct vgic_lr vlr
)
1170 if (vgic_irq_is_active(vcpu
, irq
)) {
1171 vlr
.state
|= LR_STATE_ACTIVE
;
1172 kvm_debug("Set active, clear distributor: 0x%x\n", vlr
.state
);
1173 vgic_irq_clear_active(vcpu
, irq
);
1174 vgic_update_state(vcpu
->kvm
);
1176 WARN_ON(!vgic_dist_irq_is_pending(vcpu
, irq
));
1177 vlr
.state
|= LR_STATE_PENDING
;
1178 kvm_debug("Set pending: 0x%x\n", vlr
.state
);
1181 if (!vgic_irq_is_edge(vcpu
, irq
))
1182 vlr
.state
|= LR_EOI_INT
;
1184 if (vlr
.irq
>= VGIC_NR_SGIS
) {
1185 struct irq_phys_map
*map
;
1186 map
= vgic_irq_map_search(vcpu
, irq
);
1189 vlr
.hwirq
= map
->phys_irq
;
1191 vlr
.state
&= ~LR_EOI_INT
;
1194 * Make sure we're not going to sample this
1195 * again, as a HW-backed interrupt cannot be
1196 * in the PENDING_ACTIVE stage.
1198 vgic_irq_set_queued(vcpu
, irq
);
1202 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1203 vgic_sync_lr_elrsr(vcpu
, lr_nr
, vlr
);
1207 * Queue an interrupt to a CPU virtual interface. Return true on success,
1208 * or false if it wasn't possible to queue it.
1209 * sgi_source must be zero for any non-SGI interrupts.
1211 bool vgic_queue_irq(struct kvm_vcpu
*vcpu
, u8 sgi_source_id
, int irq
)
1213 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1214 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1218 /* Sanitize the input... */
1219 BUG_ON(sgi_source_id
& ~7);
1220 BUG_ON(sgi_source_id
&& irq
>= VGIC_NR_SGIS
);
1221 BUG_ON(irq
>= dist
->nr_irqs
);
1223 kvm_debug("Queue IRQ%d\n", irq
);
1225 lr
= vgic_cpu
->vgic_irq_lr_map
[irq
];
1227 /* Do we have an active interrupt for the same CPUID? */
1228 if (lr
!= LR_EMPTY
) {
1229 vlr
= vgic_get_lr(vcpu
, lr
);
1230 if (vlr
.source
== sgi_source_id
) {
1231 kvm_debug("LR%d piggyback for IRQ%d\n", lr
, vlr
.irq
);
1232 BUG_ON(!test_bit(lr
, vgic_cpu
->lr_used
));
1233 vgic_queue_irq_to_lr(vcpu
, irq
, lr
, vlr
);
1238 /* Try to use another LR for this interrupt */
1239 lr
= find_first_zero_bit((unsigned long *)vgic_cpu
->lr_used
,
1241 if (lr
>= vgic
->nr_lr
)
1244 kvm_debug("LR%d allocated for IRQ%d %x\n", lr
, irq
, sgi_source_id
);
1245 vgic_cpu
->vgic_irq_lr_map
[irq
] = lr
;
1246 set_bit(lr
, vgic_cpu
->lr_used
);
1249 vlr
.source
= sgi_source_id
;
1251 vgic_queue_irq_to_lr(vcpu
, irq
, lr
, vlr
);
1256 static bool vgic_queue_hwirq(struct kvm_vcpu
*vcpu
, int irq
)
1258 if (!vgic_can_sample_irq(vcpu
, irq
))
1259 return true; /* level interrupt, already queued */
1261 if (vgic_queue_irq(vcpu
, 0, irq
)) {
1262 if (vgic_irq_is_edge(vcpu
, irq
)) {
1263 vgic_dist_irq_clear_pending(vcpu
, irq
);
1264 vgic_cpu_irq_clear(vcpu
, irq
);
1266 vgic_irq_set_queued(vcpu
, irq
);
1276 * Fill the list registers with pending interrupts before running the
1279 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1281 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1282 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1283 unsigned long *pa_percpu
, *pa_shared
;
1286 int nr_shared
= vgic_nr_shared_irqs(dist
);
1288 vcpu_id
= vcpu
->vcpu_id
;
1290 pa_percpu
= vcpu
->arch
.vgic_cpu
.pend_act_percpu
;
1291 pa_shared
= vcpu
->arch
.vgic_cpu
.pend_act_shared
;
1293 bitmap_or(pa_percpu
, vgic_cpu
->pending_percpu
, vgic_cpu
->active_percpu
,
1294 VGIC_NR_PRIVATE_IRQS
);
1295 bitmap_or(pa_shared
, vgic_cpu
->pending_shared
, vgic_cpu
->active_shared
,
1298 * We may not have any pending interrupt, or the interrupts
1299 * may have been serviced from another vcpu. In all cases,
1302 if (!kvm_vgic_vcpu_pending_irq(vcpu
) && !kvm_vgic_vcpu_active_irq(vcpu
))
1306 for_each_set_bit(i
, pa_percpu
, VGIC_NR_SGIS
) {
1307 if (!queue_sgi(vcpu
, i
))
1312 for_each_set_bit_from(i
, pa_percpu
, VGIC_NR_PRIVATE_IRQS
) {
1313 if (!vgic_queue_hwirq(vcpu
, i
))
1318 for_each_set_bit(i
, pa_shared
, nr_shared
) {
1319 if (!vgic_queue_hwirq(vcpu
, i
+ VGIC_NR_PRIVATE_IRQS
))
1328 vgic_enable_underflow(vcpu
);
1330 vgic_disable_underflow(vcpu
);
1332 * We're about to run this VCPU, and we've consumed
1333 * everything the distributor had in store for
1334 * us. Claim we don't have anything pending. We'll
1335 * adjust that if needed while exiting.
1337 clear_bit(vcpu_id
, dist
->irq_pending_on_cpu
);
1341 static bool vgic_process_maintenance(struct kvm_vcpu
*vcpu
)
1343 u32 status
= vgic_get_interrupt_status(vcpu
);
1344 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1345 bool level_pending
= false;
1346 struct kvm
*kvm
= vcpu
->kvm
;
1348 kvm_debug("STATUS = %08x\n", status
);
1350 if (status
& INT_STATUS_EOI
) {
1352 * Some level interrupts have been EOIed. Clear their
1355 u64 eisr
= vgic_get_eisr(vcpu
);
1356 unsigned long *eisr_ptr
= u64_to_bitmask(&eisr
);
1359 for_each_set_bit(lr
, eisr_ptr
, vgic
->nr_lr
) {
1360 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1361 WARN_ON(vgic_irq_is_edge(vcpu
, vlr
.irq
));
1363 spin_lock(&dist
->lock
);
1364 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1365 WARN_ON(vlr
.state
& LR_STATE_MASK
);
1367 vgic_set_lr(vcpu
, lr
, vlr
);
1370 * If the IRQ was EOIed it was also ACKed and we we
1371 * therefore assume we can clear the soft pending
1372 * state (should it had been set) for this interrupt.
1374 * Note: if the IRQ soft pending state was set after
1375 * the IRQ was acked, it actually shouldn't be
1376 * cleared, but we have no way of knowing that unless
1377 * we start trapping ACKs when the soft-pending state
1380 vgic_dist_irq_clear_soft_pend(vcpu
, vlr
.irq
);
1383 * kvm_notify_acked_irq calls kvm_set_irq()
1384 * to reset the IRQ level. Need to release the
1385 * lock for kvm_set_irq to grab it.
1387 spin_unlock(&dist
->lock
);
1389 kvm_notify_acked_irq(kvm
, 0,
1390 vlr
.irq
- VGIC_NR_PRIVATE_IRQS
);
1391 spin_lock(&dist
->lock
);
1393 /* Any additional pending interrupt? */
1394 if (vgic_dist_irq_get_level(vcpu
, vlr
.irq
)) {
1395 vgic_cpu_irq_set(vcpu
, vlr
.irq
);
1396 level_pending
= true;
1398 vgic_dist_irq_clear_pending(vcpu
, vlr
.irq
);
1399 vgic_cpu_irq_clear(vcpu
, vlr
.irq
);
1402 spin_unlock(&dist
->lock
);
1405 * Despite being EOIed, the LR may not have
1406 * been marked as empty.
1408 vgic_sync_lr_elrsr(vcpu
, lr
, vlr
);
1412 if (status
& INT_STATUS_UNDERFLOW
)
1413 vgic_disable_underflow(vcpu
);
1416 * In the next iterations of the vcpu loop, if we sync the vgic state
1417 * after flushing it, but before entering the guest (this happens for
1418 * pending signals and vmid rollovers), then make sure we don't pick
1419 * up any old maintenance interrupts here.
1421 vgic_clear_eisr(vcpu
);
1423 return level_pending
;
1427 * Save the physical active state, and reset it to inactive.
1429 * Return 1 if HW interrupt went from active to inactive, and 0 otherwise.
1431 static int vgic_sync_hwirq(struct kvm_vcpu
*vcpu
, struct vgic_lr vlr
)
1433 struct irq_phys_map
*map
;
1436 if (!(vlr
.state
& LR_HW
))
1439 map
= vgic_irq_map_search(vcpu
, vlr
.irq
);
1442 ret
= irq_get_irqchip_state(map
->irq
,
1443 IRQCHIP_STATE_ACTIVE
,
1454 /* Sync back the VGIC state after a guest run */
1455 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1457 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1458 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1460 unsigned long *elrsr_ptr
;
1464 level_pending
= vgic_process_maintenance(vcpu
);
1465 elrsr
= vgic_get_elrsr(vcpu
);
1466 elrsr_ptr
= u64_to_bitmask(&elrsr
);
1468 /* Deal with HW interrupts, and clear mappings for empty LRs */
1469 for (lr
= 0; lr
< vgic
->nr_lr
; lr
++) {
1472 if (!test_bit(lr
, vgic_cpu
->lr_used
))
1475 vlr
= vgic_get_lr(vcpu
, lr
);
1476 if (vgic_sync_hwirq(vcpu
, vlr
)) {
1478 * So this is a HW interrupt that the guest
1479 * EOI-ed. Clean the LR state and allow the
1480 * interrupt to be sampled again.
1484 vgic_set_lr(vcpu
, lr
, vlr
);
1485 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1486 set_bit(lr
, elrsr_ptr
);
1489 if (!test_bit(lr
, elrsr_ptr
))
1492 clear_bit(lr
, vgic_cpu
->lr_used
);
1494 BUG_ON(vlr
.irq
>= dist
->nr_irqs
);
1495 vgic_cpu
->vgic_irq_lr_map
[vlr
.irq
] = LR_EMPTY
;
1498 /* Check if we still have something up our sleeve... */
1499 pending
= find_first_zero_bit(elrsr_ptr
, vgic
->nr_lr
);
1500 if (level_pending
|| pending
< vgic
->nr_lr
)
1501 set_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
1504 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1506 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1508 if (!irqchip_in_kernel(vcpu
->kvm
))
1511 spin_lock(&dist
->lock
);
1512 __kvm_vgic_flush_hwstate(vcpu
);
1513 spin_unlock(&dist
->lock
);
1516 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1518 if (!irqchip_in_kernel(vcpu
->kvm
))
1521 __kvm_vgic_sync_hwstate(vcpu
);
1524 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
)
1526 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1528 if (!irqchip_in_kernel(vcpu
->kvm
))
1531 return test_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
1534 int kvm_vgic_vcpu_active_irq(struct kvm_vcpu
*vcpu
)
1536 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1538 if (!irqchip_in_kernel(vcpu
->kvm
))
1541 return test_bit(vcpu
->vcpu_id
, dist
->irq_active_on_cpu
);
1545 void vgic_kick_vcpus(struct kvm
*kvm
)
1547 struct kvm_vcpu
*vcpu
;
1551 * We've injected an interrupt, time to find out who deserves
1554 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1555 if (kvm_vgic_vcpu_pending_irq(vcpu
))
1556 kvm_vcpu_kick(vcpu
);
1560 static int vgic_validate_injection(struct kvm_vcpu
*vcpu
, int irq
, int level
)
1562 int edge_triggered
= vgic_irq_is_edge(vcpu
, irq
);
1565 * Only inject an interrupt if:
1566 * - edge triggered and we have a rising edge
1567 * - level triggered and we change level
1569 if (edge_triggered
) {
1570 int state
= vgic_dist_irq_is_pending(vcpu
, irq
);
1571 return level
> state
;
1573 int state
= vgic_dist_irq_get_level(vcpu
, irq
);
1574 return level
!= state
;
1578 static int vgic_update_irq_pending(struct kvm
*kvm
, int cpuid
,
1579 struct irq_phys_map
*map
,
1580 unsigned int irq_num
, bool level
)
1582 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1583 struct kvm_vcpu
*vcpu
;
1584 int edge_triggered
, level_triggered
;
1586 bool ret
= true, can_inject
= true;
1588 if (irq_num
>= min(kvm
->arch
.vgic
.nr_irqs
, 1020))
1591 spin_lock(&dist
->lock
);
1593 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1594 edge_triggered
= vgic_irq_is_edge(vcpu
, irq_num
);
1595 level_triggered
= !edge_triggered
;
1597 if (!vgic_validate_injection(vcpu
, irq_num
, level
)) {
1602 if (irq_num
>= VGIC_NR_PRIVATE_IRQS
) {
1603 cpuid
= dist
->irq_spi_cpu
[irq_num
- VGIC_NR_PRIVATE_IRQS
];
1604 if (cpuid
== VCPU_NOT_ALLOCATED
) {
1605 /* Pretend we use CPU0, and prevent injection */
1609 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1612 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num
, level
, cpuid
);
1615 if (level_triggered
)
1616 vgic_dist_irq_set_level(vcpu
, irq_num
);
1617 vgic_dist_irq_set_pending(vcpu
, irq_num
);
1619 if (level_triggered
) {
1620 vgic_dist_irq_clear_level(vcpu
, irq_num
);
1621 if (!vgic_dist_irq_soft_pend(vcpu
, irq_num
)) {
1622 vgic_dist_irq_clear_pending(vcpu
, irq_num
);
1623 vgic_cpu_irq_clear(vcpu
, irq_num
);
1624 if (!compute_pending_for_cpu(vcpu
))
1625 clear_bit(cpuid
, dist
->irq_pending_on_cpu
);
1633 enabled
= vgic_irq_is_enabled(vcpu
, irq_num
);
1635 if (!enabled
|| !can_inject
) {
1640 if (!vgic_can_sample_irq(vcpu
, irq_num
)) {
1642 * Level interrupt in progress, will be picked up
1650 vgic_cpu_irq_set(vcpu
, irq_num
);
1651 set_bit(cpuid
, dist
->irq_pending_on_cpu
);
1655 spin_unlock(&dist
->lock
);
1658 /* kick the specified vcpu */
1659 kvm_vcpu_kick(kvm_get_vcpu(kvm
, cpuid
));
1665 static int vgic_lazy_init(struct kvm
*kvm
)
1669 if (unlikely(!vgic_initialized(kvm
))) {
1671 * We only provide the automatic initialization of the VGIC
1672 * for the legacy case of a GICv2. Any other type must
1673 * be explicitly initialized once setup with the respective
1676 if (kvm
->arch
.vgic
.vgic_model
!= KVM_DEV_TYPE_ARM_VGIC_V2
)
1679 mutex_lock(&kvm
->lock
);
1680 ret
= vgic_init(kvm
);
1681 mutex_unlock(&kvm
->lock
);
1688 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1689 * @kvm: The VM structure pointer
1690 * @cpuid: The CPU for PPIs
1691 * @irq_num: The IRQ number that is assigned to the device. This IRQ
1692 * must not be mapped to a HW interrupt.
1693 * @level: Edge-triggered: true: to trigger the interrupt
1694 * false: to ignore the call
1695 * Level-sensitive true: raise the input signal
1696 * false: lower the input signal
1698 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1699 * level-sensitive interrupts. You can think of the level parameter as 1
1700 * being HIGH and 0 being LOW and all devices being active-HIGH.
1702 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int irq_num
,
1705 struct irq_phys_map
*map
;
1708 ret
= vgic_lazy_init(kvm
);
1712 map
= vgic_irq_map_search(kvm_get_vcpu(kvm
, cpuid
), irq_num
);
1716 return vgic_update_irq_pending(kvm
, cpuid
, NULL
, irq_num
, level
);
1720 * kvm_vgic_inject_mapped_irq - Inject a physically mapped IRQ to the vgic
1721 * @kvm: The VM structure pointer
1722 * @cpuid: The CPU for PPIs
1723 * @map: Pointer to a irq_phys_map structure describing the mapping
1724 * @level: Edge-triggered: true: to trigger the interrupt
1725 * false: to ignore the call
1726 * Level-sensitive true: raise the input signal
1727 * false: lower the input signal
1729 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1730 * level-sensitive interrupts. You can think of the level parameter as 1
1731 * being HIGH and 0 being LOW and all devices being active-HIGH.
1733 int kvm_vgic_inject_mapped_irq(struct kvm
*kvm
, int cpuid
,
1734 struct irq_phys_map
*map
, bool level
)
1738 ret
= vgic_lazy_init(kvm
);
1742 return vgic_update_irq_pending(kvm
, cpuid
, map
, map
->virt_irq
, level
);
1745 static irqreturn_t
vgic_maintenance_handler(int irq
, void *data
)
1748 * We cannot rely on the vgic maintenance interrupt to be
1749 * delivered synchronously. This means we can only use it to
1750 * exit the VM, and we perform the handling of EOIed
1751 * interrupts on the exit path (see vgic_process_maintenance).
1756 static struct list_head
*vgic_get_irq_phys_map_list(struct kvm_vcpu
*vcpu
,
1759 if (virt_irq
< VGIC_NR_PRIVATE_IRQS
)
1760 return &vcpu
->arch
.vgic_cpu
.irq_phys_map_list
;
1762 return &vcpu
->kvm
->arch
.vgic
.irq_phys_map_list
;
1766 * kvm_vgic_map_phys_irq - map a virtual IRQ to a physical IRQ
1767 * @vcpu: The VCPU pointer
1768 * @virt_irq: The virtual irq number
1769 * @irq: The Linux IRQ number
1771 * Establish a mapping between a guest visible irq (@virt_irq) and a
1772 * Linux irq (@irq). On injection, @virt_irq will be associated with
1773 * the physical interrupt represented by @irq. This mapping can be
1774 * established multiple times as long as the parameters are the same.
1776 * Returns a valid pointer on success, and an error pointer otherwise
1778 struct irq_phys_map
*kvm_vgic_map_phys_irq(struct kvm_vcpu
*vcpu
,
1779 int virt_irq
, int irq
)
1781 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1782 struct list_head
*root
= vgic_get_irq_phys_map_list(vcpu
, virt_irq
);
1783 struct irq_phys_map
*map
;
1784 struct irq_phys_map_entry
*entry
;
1785 struct irq_desc
*desc
;
1786 struct irq_data
*data
;
1789 desc
= irq_to_desc(irq
);
1791 kvm_err("%s: no interrupt descriptor\n", __func__
);
1792 return ERR_PTR(-EINVAL
);
1795 data
= irq_desc_get_irq_data(desc
);
1796 while (data
->parent_data
)
1797 data
= data
->parent_data
;
1799 phys_irq
= data
->hwirq
;
1801 /* Create a new mapping */
1802 entry
= kzalloc(sizeof(*entry
), GFP_KERNEL
);
1804 return ERR_PTR(-ENOMEM
);
1806 spin_lock(&dist
->irq_phys_map_lock
);
1808 /* Try to match an existing mapping */
1809 map
= vgic_irq_map_search(vcpu
, virt_irq
);
1811 /* Make sure this mapping matches */
1812 if (map
->phys_irq
!= phys_irq
||
1814 map
= ERR_PTR(-EINVAL
);
1816 /* Found an existing, valid mapping */
1821 map
->virt_irq
= virt_irq
;
1822 map
->phys_irq
= phys_irq
;
1825 list_add_tail_rcu(&entry
->entry
, root
);
1828 spin_unlock(&dist
->irq_phys_map_lock
);
1829 /* If we've found a hit in the existing list, free the useless
1831 if (IS_ERR(map
) || map
!= &entry
->map
)
1836 static struct irq_phys_map
*vgic_irq_map_search(struct kvm_vcpu
*vcpu
,
1839 struct list_head
*root
= vgic_get_irq_phys_map_list(vcpu
, virt_irq
);
1840 struct irq_phys_map_entry
*entry
;
1841 struct irq_phys_map
*map
;
1845 list_for_each_entry_rcu(entry
, root
, entry
) {
1847 if (map
->virt_irq
== virt_irq
) {
1858 static void vgic_free_phys_irq_map_rcu(struct rcu_head
*rcu
)
1860 struct irq_phys_map_entry
*entry
;
1862 entry
= container_of(rcu
, struct irq_phys_map_entry
, rcu
);
1867 * kvm_vgic_get_phys_irq_active - Return the active state of a mapped IRQ
1869 * Return the logical active state of a mapped interrupt. This doesn't
1870 * necessarily reflects the current HW state.
1872 bool kvm_vgic_get_phys_irq_active(struct irq_phys_map
*map
)
1879 * kvm_vgic_set_phys_irq_active - Set the active state of a mapped IRQ
1881 * Set the logical active state of a mapped interrupt. This doesn't
1882 * immediately affects the HW state.
1884 void kvm_vgic_set_phys_irq_active(struct irq_phys_map
*map
, bool active
)
1887 map
->active
= active
;
1891 * kvm_vgic_unmap_phys_irq - Remove a virtual to physical IRQ mapping
1892 * @vcpu: The VCPU pointer
1893 * @map: The pointer to a mapping obtained through kvm_vgic_map_phys_irq
1895 * Remove an existing mapping between virtual and physical interrupts.
1897 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu
*vcpu
, struct irq_phys_map
*map
)
1899 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1900 struct irq_phys_map_entry
*entry
;
1901 struct list_head
*root
;
1906 root
= vgic_get_irq_phys_map_list(vcpu
, map
->virt_irq
);
1908 spin_lock(&dist
->irq_phys_map_lock
);
1910 list_for_each_entry(entry
, root
, entry
) {
1911 if (&entry
->map
== map
) {
1912 list_del_rcu(&entry
->entry
);
1913 call_rcu(&entry
->rcu
, vgic_free_phys_irq_map_rcu
);
1918 spin_unlock(&dist
->irq_phys_map_lock
);
1923 static void vgic_destroy_irq_phys_map(struct kvm
*kvm
, struct list_head
*root
)
1925 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1926 struct irq_phys_map_entry
*entry
;
1928 spin_lock(&dist
->irq_phys_map_lock
);
1930 list_for_each_entry(entry
, root
, entry
) {
1931 list_del_rcu(&entry
->entry
);
1932 call_rcu(&entry
->rcu
, vgic_free_phys_irq_map_rcu
);
1935 spin_unlock(&dist
->irq_phys_map_lock
);
1938 void kvm_vgic_vcpu_destroy(struct kvm_vcpu
*vcpu
)
1940 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1942 kfree(vgic_cpu
->pending_shared
);
1943 kfree(vgic_cpu
->active_shared
);
1944 kfree(vgic_cpu
->pend_act_shared
);
1945 kfree(vgic_cpu
->vgic_irq_lr_map
);
1946 vgic_destroy_irq_phys_map(vcpu
->kvm
, &vgic_cpu
->irq_phys_map_list
);
1947 vgic_cpu
->pending_shared
= NULL
;
1948 vgic_cpu
->active_shared
= NULL
;
1949 vgic_cpu
->pend_act_shared
= NULL
;
1950 vgic_cpu
->vgic_irq_lr_map
= NULL
;
1953 static int vgic_vcpu_init_maps(struct kvm_vcpu
*vcpu
, int nr_irqs
)
1955 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1957 int sz
= (nr_irqs
- VGIC_NR_PRIVATE_IRQS
) / 8;
1958 vgic_cpu
->pending_shared
= kzalloc(sz
, GFP_KERNEL
);
1959 vgic_cpu
->active_shared
= kzalloc(sz
, GFP_KERNEL
);
1960 vgic_cpu
->pend_act_shared
= kzalloc(sz
, GFP_KERNEL
);
1961 vgic_cpu
->vgic_irq_lr_map
= kmalloc(nr_irqs
, GFP_KERNEL
);
1963 if (!vgic_cpu
->pending_shared
1964 || !vgic_cpu
->active_shared
1965 || !vgic_cpu
->pend_act_shared
1966 || !vgic_cpu
->vgic_irq_lr_map
) {
1967 kvm_vgic_vcpu_destroy(vcpu
);
1971 memset(vgic_cpu
->vgic_irq_lr_map
, LR_EMPTY
, nr_irqs
);
1974 * Store the number of LRs per vcpu, so we don't have to go
1975 * all the way to the distributor structure to find out. Only
1976 * assembly code should use this one.
1978 vgic_cpu
->nr_lr
= vgic
->nr_lr
;
1984 * kvm_vgic_vcpu_early_init - Earliest possible per-vcpu vgic init stage
1986 * No memory allocation should be performed here, only static init.
1988 void kvm_vgic_vcpu_early_init(struct kvm_vcpu
*vcpu
)
1990 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1991 INIT_LIST_HEAD(&vgic_cpu
->irq_phys_map_list
);
1995 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
1997 * The host's GIC naturally limits the maximum amount of VCPUs a guest
2000 int kvm_vgic_get_max_vcpus(void)
2002 return vgic
->max_gic_vcpus
;
2005 void kvm_vgic_destroy(struct kvm
*kvm
)
2007 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
2008 struct kvm_vcpu
*vcpu
;
2011 kvm_for_each_vcpu(i
, vcpu
, kvm
)
2012 kvm_vgic_vcpu_destroy(vcpu
);
2014 vgic_free_bitmap(&dist
->irq_enabled
);
2015 vgic_free_bitmap(&dist
->irq_level
);
2016 vgic_free_bitmap(&dist
->irq_pending
);
2017 vgic_free_bitmap(&dist
->irq_soft_pend
);
2018 vgic_free_bitmap(&dist
->irq_queued
);
2019 vgic_free_bitmap(&dist
->irq_cfg
);
2020 vgic_free_bytemap(&dist
->irq_priority
);
2021 if (dist
->irq_spi_target
) {
2022 for (i
= 0; i
< dist
->nr_cpus
; i
++)
2023 vgic_free_bitmap(&dist
->irq_spi_target
[i
]);
2025 kfree(dist
->irq_sgi_sources
);
2026 kfree(dist
->irq_spi_cpu
);
2027 kfree(dist
->irq_spi_mpidr
);
2028 kfree(dist
->irq_spi_target
);
2029 kfree(dist
->irq_pending_on_cpu
);
2030 kfree(dist
->irq_active_on_cpu
);
2031 vgic_destroy_irq_phys_map(kvm
, &dist
->irq_phys_map_list
);
2032 dist
->irq_sgi_sources
= NULL
;
2033 dist
->irq_spi_cpu
= NULL
;
2034 dist
->irq_spi_target
= NULL
;
2035 dist
->irq_pending_on_cpu
= NULL
;
2036 dist
->irq_active_on_cpu
= NULL
;
2041 * Allocate and initialize the various data structures. Must be called
2042 * with kvm->lock held!
2044 int vgic_init(struct kvm
*kvm
)
2046 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
2047 struct kvm_vcpu
*vcpu
;
2048 int nr_cpus
, nr_irqs
;
2049 int ret
, i
, vcpu_id
;
2051 if (vgic_initialized(kvm
))
2054 nr_cpus
= dist
->nr_cpus
= atomic_read(&kvm
->online_vcpus
);
2055 if (!nr_cpus
) /* No vcpus? Can't be good... */
2059 * If nobody configured the number of interrupts, use the
2063 dist
->nr_irqs
= VGIC_NR_IRQS_LEGACY
;
2065 nr_irqs
= dist
->nr_irqs
;
2067 ret
= vgic_init_bitmap(&dist
->irq_enabled
, nr_cpus
, nr_irqs
);
2068 ret
|= vgic_init_bitmap(&dist
->irq_level
, nr_cpus
, nr_irqs
);
2069 ret
|= vgic_init_bitmap(&dist
->irq_pending
, nr_cpus
, nr_irqs
);
2070 ret
|= vgic_init_bitmap(&dist
->irq_soft_pend
, nr_cpus
, nr_irqs
);
2071 ret
|= vgic_init_bitmap(&dist
->irq_queued
, nr_cpus
, nr_irqs
);
2072 ret
|= vgic_init_bitmap(&dist
->irq_active
, nr_cpus
, nr_irqs
);
2073 ret
|= vgic_init_bitmap(&dist
->irq_cfg
, nr_cpus
, nr_irqs
);
2074 ret
|= vgic_init_bytemap(&dist
->irq_priority
, nr_cpus
, nr_irqs
);
2079 dist
->irq_sgi_sources
= kzalloc(nr_cpus
* VGIC_NR_SGIS
, GFP_KERNEL
);
2080 dist
->irq_spi_cpu
= kzalloc(nr_irqs
- VGIC_NR_PRIVATE_IRQS
, GFP_KERNEL
);
2081 dist
->irq_spi_target
= kzalloc(sizeof(*dist
->irq_spi_target
) * nr_cpus
,
2083 dist
->irq_pending_on_cpu
= kzalloc(BITS_TO_LONGS(nr_cpus
) * sizeof(long),
2085 dist
->irq_active_on_cpu
= kzalloc(BITS_TO_LONGS(nr_cpus
) * sizeof(long),
2087 if (!dist
->irq_sgi_sources
||
2088 !dist
->irq_spi_cpu
||
2089 !dist
->irq_spi_target
||
2090 !dist
->irq_pending_on_cpu
||
2091 !dist
->irq_active_on_cpu
) {
2096 for (i
= 0; i
< nr_cpus
; i
++)
2097 ret
|= vgic_init_bitmap(&dist
->irq_spi_target
[i
],
2103 ret
= kvm
->arch
.vgic
.vm_ops
.init_model(kvm
);
2107 kvm_for_each_vcpu(vcpu_id
, vcpu
, kvm
) {
2108 ret
= vgic_vcpu_init_maps(vcpu
, nr_irqs
);
2110 kvm_err("VGIC: Failed to allocate vcpu memory\n");
2114 for (i
= 0; i
< dist
->nr_irqs
; i
++) {
2115 if (i
< VGIC_NR_PPIS
)
2116 vgic_bitmap_set_irq_val(&dist
->irq_enabled
,
2117 vcpu
->vcpu_id
, i
, 1);
2118 if (i
< VGIC_NR_PRIVATE_IRQS
)
2119 vgic_bitmap_set_irq_val(&dist
->irq_cfg
,
2129 kvm_vgic_destroy(kvm
);
2134 static int init_vgic_model(struct kvm
*kvm
, int type
)
2137 case KVM_DEV_TYPE_ARM_VGIC_V2
:
2138 vgic_v2_init_emulation(kvm
);
2140 #ifdef CONFIG_ARM_GIC_V3
2141 case KVM_DEV_TYPE_ARM_VGIC_V3
:
2142 vgic_v3_init_emulation(kvm
);
2149 if (atomic_read(&kvm
->online_vcpus
) > kvm
->arch
.max_vcpus
)
2156 * kvm_vgic_early_init - Earliest possible vgic initialization stage
2158 * No memory allocation should be performed here, only static init.
2160 void kvm_vgic_early_init(struct kvm
*kvm
)
2162 spin_lock_init(&kvm
->arch
.vgic
.lock
);
2163 spin_lock_init(&kvm
->arch
.vgic
.irq_phys_map_lock
);
2164 INIT_LIST_HEAD(&kvm
->arch
.vgic
.irq_phys_map_list
);
2167 int kvm_vgic_create(struct kvm
*kvm
, u32 type
)
2169 int i
, vcpu_lock_idx
= -1, ret
;
2170 struct kvm_vcpu
*vcpu
;
2172 mutex_lock(&kvm
->lock
);
2174 if (irqchip_in_kernel(kvm
)) {
2180 * This function is also called by the KVM_CREATE_IRQCHIP handler,
2181 * which had no chance yet to check the availability of the GICv2
2182 * emulation. So check this here again. KVM_CREATE_DEVICE does
2183 * the proper checks already.
2185 if (type
== KVM_DEV_TYPE_ARM_VGIC_V2
&& !vgic
->can_emulate_gicv2
) {
2191 * Any time a vcpu is run, vcpu_load is called which tries to grab the
2192 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
2193 * that no other VCPUs are run while we create the vgic.
2196 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
2197 if (!mutex_trylock(&vcpu
->mutex
))
2202 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
2203 if (vcpu
->arch
.has_run_once
)
2208 ret
= init_vgic_model(kvm
, type
);
2212 kvm
->arch
.vgic
.in_kernel
= true;
2213 kvm
->arch
.vgic
.vgic_model
= type
;
2214 kvm
->arch
.vgic
.vctrl_base
= vgic
->vctrl_base
;
2215 kvm
->arch
.vgic
.vgic_dist_base
= VGIC_ADDR_UNDEF
;
2216 kvm
->arch
.vgic
.vgic_cpu_base
= VGIC_ADDR_UNDEF
;
2217 kvm
->arch
.vgic
.vgic_redist_base
= VGIC_ADDR_UNDEF
;
2220 for (; vcpu_lock_idx
>= 0; vcpu_lock_idx
--) {
2221 vcpu
= kvm_get_vcpu(kvm
, vcpu_lock_idx
);
2222 mutex_unlock(&vcpu
->mutex
);
2226 mutex_unlock(&kvm
->lock
);
2230 static int vgic_ioaddr_overlap(struct kvm
*kvm
)
2232 phys_addr_t dist
= kvm
->arch
.vgic
.vgic_dist_base
;
2233 phys_addr_t cpu
= kvm
->arch
.vgic
.vgic_cpu_base
;
2235 if (IS_VGIC_ADDR_UNDEF(dist
) || IS_VGIC_ADDR_UNDEF(cpu
))
2237 if ((dist
<= cpu
&& dist
+ KVM_VGIC_V2_DIST_SIZE
> cpu
) ||
2238 (cpu
<= dist
&& cpu
+ KVM_VGIC_V2_CPU_SIZE
> dist
))
2243 static int vgic_ioaddr_assign(struct kvm
*kvm
, phys_addr_t
*ioaddr
,
2244 phys_addr_t addr
, phys_addr_t size
)
2248 if (addr
& ~KVM_PHYS_MASK
)
2251 if (addr
& (SZ_4K
- 1))
2254 if (!IS_VGIC_ADDR_UNDEF(*ioaddr
))
2256 if (addr
+ size
< addr
)
2260 ret
= vgic_ioaddr_overlap(kvm
);
2262 *ioaddr
= VGIC_ADDR_UNDEF
;
2268 * kvm_vgic_addr - set or get vgic VM base addresses
2269 * @kvm: pointer to the vm struct
2270 * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX
2271 * @addr: pointer to address value
2272 * @write: if true set the address in the VM address space, if false read the
2275 * Set or get the vgic base addresses for the distributor and the virtual CPU
2276 * interface in the VM physical address space. These addresses are properties
2277 * of the emulated core/SoC and therefore user space initially knows this
2280 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
)
2283 struct vgic_dist
*vgic
= &kvm
->arch
.vgic
;
2285 phys_addr_t
*addr_ptr
, block_size
;
2286 phys_addr_t alignment
;
2288 mutex_lock(&kvm
->lock
);
2290 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
2291 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V2
;
2292 addr_ptr
= &vgic
->vgic_dist_base
;
2293 block_size
= KVM_VGIC_V2_DIST_SIZE
;
2296 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
2297 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V2
;
2298 addr_ptr
= &vgic
->vgic_cpu_base
;
2299 block_size
= KVM_VGIC_V2_CPU_SIZE
;
2302 #ifdef CONFIG_ARM_GIC_V3
2303 case KVM_VGIC_V3_ADDR_TYPE_DIST
:
2304 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V3
;
2305 addr_ptr
= &vgic
->vgic_dist_base
;
2306 block_size
= KVM_VGIC_V3_DIST_SIZE
;
2309 case KVM_VGIC_V3_ADDR_TYPE_REDIST
:
2310 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V3
;
2311 addr_ptr
= &vgic
->vgic_redist_base
;
2312 block_size
= KVM_VGIC_V3_REDIST_SIZE
;
2321 if (vgic
->vgic_model
!= type_needed
) {
2327 if (!IS_ALIGNED(*addr
, alignment
))
2330 r
= vgic_ioaddr_assign(kvm
, addr_ptr
, *addr
,
2337 mutex_unlock(&kvm
->lock
);
2341 int vgic_set_common_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2345 switch (attr
->group
) {
2346 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
2347 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
2349 unsigned long type
= (unsigned long)attr
->attr
;
2351 if (copy_from_user(&addr
, uaddr
, sizeof(addr
)))
2354 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, true);
2355 return (r
== -ENODEV
) ? -ENXIO
: r
;
2357 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
: {
2358 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2362 if (get_user(val
, uaddr
))
2367 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
2368 * - at most 1024 interrupts
2369 * - a multiple of 32 interrupts
2371 if (val
< (VGIC_NR_PRIVATE_IRQS
+ 32) ||
2372 val
> VGIC_MAX_IRQS
||
2376 mutex_lock(&dev
->kvm
->lock
);
2378 if (vgic_ready(dev
->kvm
) || dev
->kvm
->arch
.vgic
.nr_irqs
)
2381 dev
->kvm
->arch
.vgic
.nr_irqs
= val
;
2383 mutex_unlock(&dev
->kvm
->lock
);
2387 case KVM_DEV_ARM_VGIC_GRP_CTRL
: {
2388 switch (attr
->attr
) {
2389 case KVM_DEV_ARM_VGIC_CTRL_INIT
:
2390 r
= vgic_init(dev
->kvm
);
2400 int vgic_get_common_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2404 switch (attr
->group
) {
2405 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
2406 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
2408 unsigned long type
= (unsigned long)attr
->attr
;
2410 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, false);
2412 return (r
== -ENODEV
) ? -ENXIO
: r
;
2414 if (copy_to_user(uaddr
, &addr
, sizeof(addr
)))
2418 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
: {
2419 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2421 r
= put_user(dev
->kvm
->arch
.vgic
.nr_irqs
, uaddr
);
2430 int vgic_has_attr_regs(const struct vgic_io_range
*ranges
, phys_addr_t offset
)
2432 if (vgic_find_range(ranges
, 4, offset
))
2438 static void vgic_init_maintenance_interrupt(void *info
)
2440 enable_percpu_irq(vgic
->maint_irq
, 0);
2443 static int vgic_cpu_notify(struct notifier_block
*self
,
2444 unsigned long action
, void *cpu
)
2448 case CPU_STARTING_FROZEN
:
2449 vgic_init_maintenance_interrupt(NULL
);
2452 case CPU_DYING_FROZEN
:
2453 disable_percpu_irq(vgic
->maint_irq
);
2460 static struct notifier_block vgic_cpu_nb
= {
2461 .notifier_call
= vgic_cpu_notify
,
2464 static const struct of_device_id vgic_ids
[] = {
2465 { .compatible
= "arm,cortex-a15-gic", .data
= vgic_v2_probe
, },
2466 { .compatible
= "arm,cortex-a7-gic", .data
= vgic_v2_probe
, },
2467 { .compatible
= "arm,gic-400", .data
= vgic_v2_probe
, },
2468 { .compatible
= "arm,gic-v3", .data
= vgic_v3_probe
, },
2472 int kvm_vgic_hyp_init(void)
2474 const struct of_device_id
*matched_id
;
2475 const int (*vgic_probe
)(struct device_node
*,const struct vgic_ops
**,
2476 const struct vgic_params
**);
2477 struct device_node
*vgic_node
;
2480 vgic_node
= of_find_matching_node_and_match(NULL
,
2481 vgic_ids
, &matched_id
);
2483 kvm_err("error: no compatible GIC node found\n");
2487 vgic_probe
= matched_id
->data
;
2488 ret
= vgic_probe(vgic_node
, &vgic_ops
, &vgic
);
2492 ret
= request_percpu_irq(vgic
->maint_irq
, vgic_maintenance_handler
,
2493 "vgic", kvm_get_running_vcpus());
2495 kvm_err("Cannot register interrupt %d\n", vgic
->maint_irq
);
2499 ret
= __register_cpu_notifier(&vgic_cpu_nb
);
2501 kvm_err("Cannot register vgic CPU notifier\n");
2505 on_each_cpu(vgic_init_maintenance_interrupt
, NULL
, 1);
2510 free_percpu_irq(vgic
->maint_irq
, kvm_get_running_vcpus());
2514 int kvm_irq_map_gsi(struct kvm
*kvm
,
2515 struct kvm_kernel_irq_routing_entry
*entries
,
2521 int kvm_irq_map_chip_pin(struct kvm
*kvm
, unsigned irqchip
, unsigned pin
)
2526 int kvm_set_irq(struct kvm
*kvm
, int irq_source_id
,
2527 u32 irq
, int level
, bool line_status
)
2529 unsigned int spi
= irq
+ VGIC_NR_PRIVATE_IRQS
;
2531 trace_kvm_set_irq(irq
, level
, irq_source_id
);
2533 BUG_ON(!vgic_initialized(kvm
));
2535 return kvm_vgic_inject_irq(kvm
, 0, spi
, level
);
2538 /* MSI not implemented yet */
2539 int kvm_set_msi(struct kvm_kernel_irq_routing_entry
*e
,
2540 struct kvm
*kvm
, int irq_source_id
,
2541 int level
, bool line_status
)