2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/uaccess.h>
29 #include <linux/irqchip/arm-gic.h>
31 #include <asm/kvm_emulate.h>
32 #include <asm/kvm_arm.h>
33 #include <asm/kvm_mmu.h>
36 * How the whole thing works (courtesy of Christoffer Dall):
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
39 * something is pending on the CPU interface.
40 * - Interrupts that are pending on the distributor are stored on the
41 * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
42 * ioctls and guest mmio ops, and other in-kernel peripherals such as the
44 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
48 * - PPI: dist->irq_pending & dist->irq_enable
49 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
50 * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
51 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
54 * - If any of the above state changes, we must recalculate the oracle.
55 * - The same is true when injecting an interrupt, except that we only
56 * consider a single interrupt at a time. The irq_spi_cpu array
57 * contains the target CPU for each SPI.
59 * The handling of level interrupts adds some extra complexity. We
60 * need to track when the interrupt has been EOIed, so we can sample
61 * the 'line' again. This is achieved as such:
63 * - When a level interrupt is moved onto a vcpu, the corresponding
64 * bit in irq_queued is set. As long as this bit is set, the line
65 * will be ignored for further interrupts. The interrupt is injected
66 * into the vcpu with the GICH_LR_EOI bit set (generate a
67 * maintenance interrupt on EOI).
68 * - When the interrupt is EOIed, the maintenance interrupt fires,
69 * and clears the corresponding bit in irq_queued. This allows the
70 * interrupt line to be sampled again.
71 * - Note that level-triggered interrupts can also be set to pending from
72 * writes to GICD_ISPENDRn and lowering the external input line does not
73 * cause the interrupt to become inactive in such a situation.
74 * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
75 * inactive as long as the external input line is held high.
80 #define GICC_ARCH_VERSION_V2 0x2
82 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
);
83 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
);
84 static u8
*vgic_get_sgi_sources(struct vgic_dist
*dist
, int vcpu_id
, int sgi
);
85 static void vgic_dispatch_sgi(struct kvm_vcpu
*vcpu
, u32 reg
);
86 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
);
87 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr lr_desc
);
89 static const struct vgic_ops
*vgic_ops
;
90 static const struct vgic_params
*vgic
;
92 static void add_sgi_source(struct kvm_vcpu
*vcpu
, int irq
, int source
)
94 vcpu
->kvm
->arch
.vgic
.vm_ops
.add_sgi_source(vcpu
, irq
, source
);
97 static bool queue_sgi(struct kvm_vcpu
*vcpu
, int irq
)
99 return vcpu
->kvm
->arch
.vgic
.vm_ops
.queue_sgi(vcpu
, irq
);
102 int kvm_vgic_map_resources(struct kvm
*kvm
)
104 return kvm
->arch
.vgic
.vm_ops
.map_resources(kvm
, vgic
);
108 * struct vgic_bitmap contains a bitmap made of unsigned longs, but
109 * extracts u32s out of them.
111 * This does not work on 64-bit BE systems, because the bitmap access
112 * will store two consecutive 32-bit words with the higher-addressed
113 * register's bits at the lower index and the lower-addressed register's
114 * bits at the higher index.
116 * Therefore, swizzle the register index when accessing the 32-bit word
117 * registers to access the right register's value.
119 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
120 #define REG_OFFSET_SWIZZLE 1
122 #define REG_OFFSET_SWIZZLE 0
125 static int vgic_init_bitmap(struct vgic_bitmap
*b
, int nr_cpus
, int nr_irqs
)
129 nr_longs
= nr_cpus
+ BITS_TO_LONGS(nr_irqs
- VGIC_NR_PRIVATE_IRQS
);
131 b
->private = kzalloc(sizeof(unsigned long) * nr_longs
, GFP_KERNEL
);
135 b
->shared
= b
->private + nr_cpus
;
140 static void vgic_free_bitmap(struct vgic_bitmap
*b
)
148 * Call this function to convert a u64 value to an unsigned long * bitmask
149 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
151 * Warning: Calling this function may modify *val.
153 static unsigned long *u64_to_bitmask(u64
*val
)
155 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
156 *val
= (*val
>> 32) | (*val
<< 32);
158 return (unsigned long *)val
;
161 u32
*vgic_bitmap_get_reg(struct vgic_bitmap
*x
, int cpuid
, u32 offset
)
165 return (u32
*)(x
->private + cpuid
) + REG_OFFSET_SWIZZLE
;
167 return (u32
*)(x
->shared
) + ((offset
- 1) ^ REG_OFFSET_SWIZZLE
);
170 static int vgic_bitmap_get_irq_val(struct vgic_bitmap
*x
,
173 if (irq
< VGIC_NR_PRIVATE_IRQS
)
174 return test_bit(irq
, x
->private + cpuid
);
176 return test_bit(irq
- VGIC_NR_PRIVATE_IRQS
, x
->shared
);
179 void vgic_bitmap_set_irq_val(struct vgic_bitmap
*x
, int cpuid
,
184 if (irq
< VGIC_NR_PRIVATE_IRQS
) {
185 reg
= x
->private + cpuid
;
188 irq
-= VGIC_NR_PRIVATE_IRQS
;
197 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap
*x
, int cpuid
)
199 return x
->private + cpuid
;
202 unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap
*x
)
207 static int vgic_init_bytemap(struct vgic_bytemap
*x
, int nr_cpus
, int nr_irqs
)
211 size
= nr_cpus
* VGIC_NR_PRIVATE_IRQS
;
212 size
+= nr_irqs
- VGIC_NR_PRIVATE_IRQS
;
214 x
->private = kzalloc(size
, GFP_KERNEL
);
218 x
->shared
= x
->private + nr_cpus
* VGIC_NR_PRIVATE_IRQS
/ sizeof(u32
);
222 static void vgic_free_bytemap(struct vgic_bytemap
*b
)
229 u32
*vgic_bytemap_get_reg(struct vgic_bytemap
*x
, int cpuid
, u32 offset
)
233 if (offset
< VGIC_NR_PRIVATE_IRQS
) {
235 offset
+= cpuid
* VGIC_NR_PRIVATE_IRQS
;
238 offset
-= VGIC_NR_PRIVATE_IRQS
;
241 return reg
+ (offset
/ sizeof(u32
));
244 #define VGIC_CFG_LEVEL 0
245 #define VGIC_CFG_EDGE 1
247 static bool vgic_irq_is_edge(struct kvm_vcpu
*vcpu
, int irq
)
249 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
252 irq_val
= vgic_bitmap_get_irq_val(&dist
->irq_cfg
, vcpu
->vcpu_id
, irq
);
253 return irq_val
== VGIC_CFG_EDGE
;
256 static int vgic_irq_is_enabled(struct kvm_vcpu
*vcpu
, int irq
)
258 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
260 return vgic_bitmap_get_irq_val(&dist
->irq_enabled
, vcpu
->vcpu_id
, irq
);
263 static int vgic_irq_is_queued(struct kvm_vcpu
*vcpu
, int irq
)
265 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
267 return vgic_bitmap_get_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
);
270 static void vgic_irq_set_queued(struct kvm_vcpu
*vcpu
, int irq
)
272 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
274 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 1);
277 static void vgic_irq_clear_queued(struct kvm_vcpu
*vcpu
, int irq
)
279 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
281 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 0);
284 static int vgic_dist_irq_get_level(struct kvm_vcpu
*vcpu
, int irq
)
286 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
288 return vgic_bitmap_get_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
);
291 static void vgic_dist_irq_set_level(struct kvm_vcpu
*vcpu
, int irq
)
293 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
295 vgic_bitmap_set_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
, 1);
298 static void vgic_dist_irq_clear_level(struct kvm_vcpu
*vcpu
, int irq
)
300 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
302 vgic_bitmap_set_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
, 0);
305 static int vgic_dist_irq_soft_pend(struct kvm_vcpu
*vcpu
, int irq
)
307 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
309 return vgic_bitmap_get_irq_val(&dist
->irq_soft_pend
, vcpu
->vcpu_id
, irq
);
312 static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu
*vcpu
, int irq
)
314 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
316 vgic_bitmap_set_irq_val(&dist
->irq_soft_pend
, vcpu
->vcpu_id
, irq
, 0);
319 static int vgic_dist_irq_is_pending(struct kvm_vcpu
*vcpu
, int irq
)
321 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
323 return vgic_bitmap_get_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
);
326 void vgic_dist_irq_set_pending(struct kvm_vcpu
*vcpu
, int irq
)
328 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
330 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 1);
333 void vgic_dist_irq_clear_pending(struct kvm_vcpu
*vcpu
, int irq
)
335 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
337 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 0);
340 static void vgic_cpu_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
342 if (irq
< VGIC_NR_PRIVATE_IRQS
)
343 set_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
345 set_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
346 vcpu
->arch
.vgic_cpu
.pending_shared
);
349 void vgic_cpu_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
351 if (irq
< VGIC_NR_PRIVATE_IRQS
)
352 clear_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
354 clear_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
355 vcpu
->arch
.vgic_cpu
.pending_shared
);
358 static bool vgic_can_sample_irq(struct kvm_vcpu
*vcpu
, int irq
)
360 return vgic_irq_is_edge(vcpu
, irq
) || !vgic_irq_is_queued(vcpu
, irq
);
364 * vgic_reg_access - access vgic register
365 * @mmio: pointer to the data describing the mmio access
366 * @reg: pointer to the virtual backing of vgic distributor data
367 * @offset: least significant 2 bits used for word offset
368 * @mode: ACCESS_ mode (see defines above)
370 * Helper to make vgic register access easier using one of the access
371 * modes defined for vgic register access
372 * (read,raz,write-ignored,setbit,clearbit,write)
374 void vgic_reg_access(struct kvm_exit_mmio
*mmio
, u32
*reg
,
375 phys_addr_t offset
, int mode
)
377 int word_offset
= (offset
& 3) * 8;
378 u32 mask
= (1UL << (mmio
->len
* 8)) - 1;
382 * Any alignment fault should have been delivered to the guest
383 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
389 BUG_ON(mode
!= (ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
));
393 if (mmio
->is_write
) {
394 u32 data
= mmio_data_read(mmio
, mask
) << word_offset
;
395 switch (ACCESS_WRITE_MASK(mode
)) {
396 case ACCESS_WRITE_IGNORED
:
399 case ACCESS_WRITE_SETBIT
:
403 case ACCESS_WRITE_CLEARBIT
:
407 case ACCESS_WRITE_VALUE
:
408 regval
= (regval
& ~(mask
<< word_offset
)) | data
;
413 switch (ACCESS_READ_MASK(mode
)) {
414 case ACCESS_READ_RAZ
:
418 case ACCESS_READ_VALUE
:
419 mmio_data_write(mmio
, mask
, regval
>> word_offset
);
424 static bool handle_mmio_misc(struct kvm_vcpu
*vcpu
,
425 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
428 u32 word_offset
= offset
& 3;
430 switch (offset
& ~3) {
431 case 0: /* GICD_CTLR */
432 reg
= vcpu
->kvm
->arch
.vgic
.enabled
;
433 vgic_reg_access(mmio
, ®
, word_offset
,
434 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
435 if (mmio
->is_write
) {
436 vcpu
->kvm
->arch
.vgic
.enabled
= reg
& 1;
437 vgic_update_state(vcpu
->kvm
);
442 case 4: /* GICD_TYPER */
443 reg
= (atomic_read(&vcpu
->kvm
->online_vcpus
) - 1) << 5;
444 reg
|= (vcpu
->kvm
->arch
.vgic
.nr_irqs
>> 5) - 1;
445 vgic_reg_access(mmio
, ®
, word_offset
,
446 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
449 case 8: /* GICD_IIDR */
450 reg
= (PRODUCT_ID_KVM
<< 24) | (IMPLEMENTER_ARM
<< 0);
451 vgic_reg_access(mmio
, ®
, word_offset
,
452 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
459 bool handle_mmio_raz_wi(struct kvm_vcpu
*vcpu
, struct kvm_exit_mmio
*mmio
,
462 vgic_reg_access(mmio
, NULL
, offset
,
463 ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
);
467 bool vgic_handle_enable_reg(struct kvm
*kvm
, struct kvm_exit_mmio
*mmio
,
468 phys_addr_t offset
, int vcpu_id
, int access
)
471 int mode
= ACCESS_READ_VALUE
| access
;
472 struct kvm_vcpu
*target_vcpu
= kvm_get_vcpu(kvm
, vcpu_id
);
474 reg
= vgic_bitmap_get_reg(&kvm
->arch
.vgic
.irq_enabled
, vcpu_id
, offset
);
475 vgic_reg_access(mmio
, reg
, offset
, mode
);
476 if (mmio
->is_write
) {
477 if (access
& ACCESS_WRITE_CLEARBIT
) {
478 if (offset
< 4) /* Force SGI enabled */
480 vgic_retire_disabled_irqs(target_vcpu
);
482 vgic_update_state(kvm
);
489 static bool handle_mmio_set_enable_reg(struct kvm_vcpu
*vcpu
,
490 struct kvm_exit_mmio
*mmio
,
493 return vgic_handle_enable_reg(vcpu
->kvm
, mmio
, offset
,
494 vcpu
->vcpu_id
, ACCESS_WRITE_SETBIT
);
497 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu
*vcpu
,
498 struct kvm_exit_mmio
*mmio
,
501 return vgic_handle_enable_reg(vcpu
->kvm
, mmio
, offset
,
502 vcpu
->vcpu_id
, ACCESS_WRITE_CLEARBIT
);
505 bool vgic_handle_set_pending_reg(struct kvm
*kvm
,
506 struct kvm_exit_mmio
*mmio
,
507 phys_addr_t offset
, int vcpu_id
)
511 int mode
= ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
;
512 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
514 reg
= vgic_bitmap_get_reg(&dist
->irq_cfg
, vcpu_id
, offset
);
515 level_mask
= (~(*reg
));
517 /* Mark both level and edge triggered irqs as pending */
518 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
520 vgic_reg_access(mmio
, reg
, offset
, mode
);
522 if (mmio
->is_write
) {
523 /* Set the soft-pending flag only for level-triggered irqs */
524 reg
= vgic_bitmap_get_reg(&dist
->irq_soft_pend
,
526 vgic_reg_access(mmio
, reg
, offset
, mode
);
529 /* Ignore writes to SGIs */
532 *reg
|= orig
& 0xffff;
535 vgic_update_state(kvm
);
542 bool vgic_handle_clear_pending_reg(struct kvm
*kvm
,
543 struct kvm_exit_mmio
*mmio
,
544 phys_addr_t offset
, int vcpu_id
)
548 int mode
= ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
;
549 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
551 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
553 vgic_reg_access(mmio
, reg
, offset
, mode
);
554 if (mmio
->is_write
) {
555 /* Re-set level triggered level-active interrupts */
556 level_active
= vgic_bitmap_get_reg(&dist
->irq_level
,
558 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
559 *reg
|= *level_active
;
561 /* Ignore writes to SGIs */
564 *reg
|= orig
& 0xffff;
567 /* Clear soft-pending flags */
568 reg
= vgic_bitmap_get_reg(&dist
->irq_soft_pend
,
570 vgic_reg_access(mmio
, reg
, offset
, mode
);
572 vgic_update_state(kvm
);
578 static bool handle_mmio_set_pending_reg(struct kvm_vcpu
*vcpu
,
579 struct kvm_exit_mmio
*mmio
,
582 return vgic_handle_set_pending_reg(vcpu
->kvm
, mmio
, offset
,
586 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu
*vcpu
,
587 struct kvm_exit_mmio
*mmio
,
590 return vgic_handle_clear_pending_reg(vcpu
->kvm
, mmio
, offset
,
594 static bool handle_mmio_priority_reg(struct kvm_vcpu
*vcpu
,
595 struct kvm_exit_mmio
*mmio
,
598 u32
*reg
= vgic_bytemap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_priority
,
599 vcpu
->vcpu_id
, offset
);
600 vgic_reg_access(mmio
, reg
, offset
,
601 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
605 #define GICD_ITARGETSR_SIZE 32
606 #define GICD_CPUTARGETS_BITS 8
607 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
608 static u32
vgic_get_target_reg(struct kvm
*kvm
, int irq
)
610 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
614 irq
-= VGIC_NR_PRIVATE_IRQS
;
616 for (i
= 0; i
< GICD_IRQS_PER_ITARGETSR
; i
++)
617 val
|= 1 << (dist
->irq_spi_cpu
[irq
+ i
] + i
* 8);
622 static void vgic_set_target_reg(struct kvm
*kvm
, u32 val
, int irq
)
624 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
625 struct kvm_vcpu
*vcpu
;
630 irq
-= VGIC_NR_PRIVATE_IRQS
;
633 * Pick the LSB in each byte. This ensures we target exactly
634 * one vcpu per IRQ. If the byte is null, assume we target
637 for (i
= 0; i
< GICD_IRQS_PER_ITARGETSR
; i
++) {
638 int shift
= i
* GICD_CPUTARGETS_BITS
;
639 target
= ffs((val
>> shift
) & 0xffU
);
640 target
= target
? (target
- 1) : 0;
641 dist
->irq_spi_cpu
[irq
+ i
] = target
;
642 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
643 bmap
= vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[c
]);
645 set_bit(irq
+ i
, bmap
);
647 clear_bit(irq
+ i
, bmap
);
652 static bool handle_mmio_target_reg(struct kvm_vcpu
*vcpu
,
653 struct kvm_exit_mmio
*mmio
,
658 /* We treat the banked interrupts targets as read-only */
660 u32 roreg
= 1 << vcpu
->vcpu_id
;
662 roreg
|= roreg
<< 16;
664 vgic_reg_access(mmio
, &roreg
, offset
,
665 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
669 reg
= vgic_get_target_reg(vcpu
->kvm
, offset
& ~3U);
670 vgic_reg_access(mmio
, ®
, offset
,
671 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
672 if (mmio
->is_write
) {
673 vgic_set_target_reg(vcpu
->kvm
, reg
, offset
& ~3U);
674 vgic_update_state(vcpu
->kvm
);
681 static u32
vgic_cfg_expand(u16 val
)
687 * Turn a 16bit value like abcd...mnop into a 32bit word
688 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
690 for (i
= 0; i
< 16; i
++)
691 res
|= ((val
>> i
) & VGIC_CFG_EDGE
) << (2 * i
+ 1);
696 static u16
vgic_cfg_compress(u32 val
)
702 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
703 * abcd...mnop which is what we really care about.
705 for (i
= 0; i
< 16; i
++)
706 res
|= ((val
>> (i
* 2 + 1)) & VGIC_CFG_EDGE
) << i
;
712 * The distributor uses 2 bits per IRQ for the CFG register, but the
713 * LSB is always 0. As such, we only keep the upper bit, and use the
714 * two above functions to compress/expand the bits
716 bool vgic_handle_cfg_reg(u32
*reg
, struct kvm_exit_mmio
*mmio
,
726 val
= vgic_cfg_expand(val
);
727 vgic_reg_access(mmio
, &val
, offset
,
728 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
729 if (mmio
->is_write
) {
731 *reg
= ~0U; /* Force PPIs/SGIs to 1 */
735 val
= vgic_cfg_compress(val
);
740 *reg
&= 0xffff << 16;
748 static bool handle_mmio_cfg_reg(struct kvm_vcpu
*vcpu
,
749 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
753 reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_cfg
,
754 vcpu
->vcpu_id
, offset
>> 1);
756 return vgic_handle_cfg_reg(reg
, mmio
, offset
);
759 static bool handle_mmio_sgi_reg(struct kvm_vcpu
*vcpu
,
760 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
763 vgic_reg_access(mmio
, ®
, offset
,
764 ACCESS_READ_RAZ
| ACCESS_WRITE_VALUE
);
765 if (mmio
->is_write
) {
766 vgic_dispatch_sgi(vcpu
, reg
);
767 vgic_update_state(vcpu
->kvm
);
774 static void vgic_v2_add_sgi_source(struct kvm_vcpu
*vcpu
, int irq
, int source
)
776 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
778 *vgic_get_sgi_sources(dist
, vcpu
->vcpu_id
, irq
) |= 1 << source
;
782 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
783 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
785 * Move any pending IRQs that have already been assigned to LRs back to the
786 * emulated distributor state so that the complete emulated state can be read
787 * from the main emulation structures without investigating the LRs.
789 * Note that IRQs in the active state in the LRs get their pending state moved
790 * to the distributor but the active state stays in the LRs, because we don't
791 * track the active state on the distributor side.
793 void vgic_unqueue_irqs(struct kvm_vcpu
*vcpu
)
795 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
798 for_each_set_bit(i
, vgic_cpu
->lr_used
, vgic_cpu
->nr_lr
) {
799 struct vgic_lr lr
= vgic_get_lr(vcpu
, i
);
802 * There are three options for the state bits:
806 * 11: pending and active
808 * If the LR holds only an active interrupt (not pending) then
809 * just leave it alone.
811 if ((lr
.state
& LR_STATE_MASK
) == LR_STATE_ACTIVE
)
815 * Reestablish the pending state on the distributor and the
816 * CPU interface. It may have already been pending, but that
817 * is fine, then we are only setting a few bits that were
820 vgic_dist_irq_set_pending(vcpu
, lr
.irq
);
821 if (lr
.irq
< VGIC_NR_SGIS
)
822 add_sgi_source(vcpu
, lr
.irq
, lr
.source
);
823 lr
.state
&= ~LR_STATE_PENDING
;
824 vgic_set_lr(vcpu
, i
, lr
);
827 * If there's no state left on the LR (it could still be
828 * active), then the LR does not hold any useful info and can
829 * be marked as free for other use.
831 if (!(lr
.state
& LR_STATE_MASK
)) {
832 vgic_retire_lr(i
, lr
.irq
, vcpu
);
833 vgic_irq_clear_queued(vcpu
, lr
.irq
);
836 /* Finally update the VGIC state. */
837 vgic_update_state(vcpu
->kvm
);
841 /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
842 static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu
*vcpu
,
843 struct kvm_exit_mmio
*mmio
,
846 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
848 int min_sgi
= (offset
& ~0x3);
849 int max_sgi
= min_sgi
+ 3;
850 int vcpu_id
= vcpu
->vcpu_id
;
853 /* Copy source SGIs from distributor side */
854 for (sgi
= min_sgi
; sgi
<= max_sgi
; sgi
++) {
855 int shift
= 8 * (sgi
- min_sgi
);
856 reg
|= ((u32
)*vgic_get_sgi_sources(dist
, vcpu_id
, sgi
)) << shift
;
859 mmio_data_write(mmio
, ~0, reg
);
863 static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu
*vcpu
,
864 struct kvm_exit_mmio
*mmio
,
865 phys_addr_t offset
, bool set
)
867 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
869 int min_sgi
= (offset
& ~0x3);
870 int max_sgi
= min_sgi
+ 3;
871 int vcpu_id
= vcpu
->vcpu_id
;
873 bool updated
= false;
875 reg
= mmio_data_read(mmio
, ~0);
877 /* Clear pending SGIs on the distributor */
878 for (sgi
= min_sgi
; sgi
<= max_sgi
; sgi
++) {
879 u8 mask
= reg
>> (8 * (sgi
- min_sgi
));
880 u8
*src
= vgic_get_sgi_sources(dist
, vcpu_id
, sgi
);
882 if ((*src
& mask
) != mask
)
893 vgic_update_state(vcpu
->kvm
);
898 static bool handle_mmio_sgi_set(struct kvm_vcpu
*vcpu
,
899 struct kvm_exit_mmio
*mmio
,
903 return read_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
);
905 return write_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
, true);
908 static bool handle_mmio_sgi_clear(struct kvm_vcpu
*vcpu
,
909 struct kvm_exit_mmio
*mmio
,
913 return read_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
);
915 return write_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
, false);
918 static const struct kvm_mmio_range vgic_dist_ranges
[] = {
920 .base
= GIC_DIST_CTRL
,
923 .handle_mmio
= handle_mmio_misc
,
926 .base
= GIC_DIST_IGROUP
,
927 .len
= VGIC_MAX_IRQS
/ 8,
929 .handle_mmio
= handle_mmio_raz_wi
,
932 .base
= GIC_DIST_ENABLE_SET
,
933 .len
= VGIC_MAX_IRQS
/ 8,
935 .handle_mmio
= handle_mmio_set_enable_reg
,
938 .base
= GIC_DIST_ENABLE_CLEAR
,
939 .len
= VGIC_MAX_IRQS
/ 8,
941 .handle_mmio
= handle_mmio_clear_enable_reg
,
944 .base
= GIC_DIST_PENDING_SET
,
945 .len
= VGIC_MAX_IRQS
/ 8,
947 .handle_mmio
= handle_mmio_set_pending_reg
,
950 .base
= GIC_DIST_PENDING_CLEAR
,
951 .len
= VGIC_MAX_IRQS
/ 8,
953 .handle_mmio
= handle_mmio_clear_pending_reg
,
956 .base
= GIC_DIST_ACTIVE_SET
,
957 .len
= VGIC_MAX_IRQS
/ 8,
959 .handle_mmio
= handle_mmio_raz_wi
,
962 .base
= GIC_DIST_ACTIVE_CLEAR
,
963 .len
= VGIC_MAX_IRQS
/ 8,
965 .handle_mmio
= handle_mmio_raz_wi
,
968 .base
= GIC_DIST_PRI
,
969 .len
= VGIC_MAX_IRQS
,
971 .handle_mmio
= handle_mmio_priority_reg
,
974 .base
= GIC_DIST_TARGET
,
975 .len
= VGIC_MAX_IRQS
,
977 .handle_mmio
= handle_mmio_target_reg
,
980 .base
= GIC_DIST_CONFIG
,
981 .len
= VGIC_MAX_IRQS
/ 4,
983 .handle_mmio
= handle_mmio_cfg_reg
,
986 .base
= GIC_DIST_SOFTINT
,
988 .handle_mmio
= handle_mmio_sgi_reg
,
991 .base
= GIC_DIST_SGI_PENDING_CLEAR
,
993 .handle_mmio
= handle_mmio_sgi_clear
,
996 .base
= GIC_DIST_SGI_PENDING_SET
,
998 .handle_mmio
= handle_mmio_sgi_set
,
1004 struct kvm_mmio_range
*vgic_find_range(const struct kvm_mmio_range
*ranges
,
1005 struct kvm_exit_mmio
*mmio
,
1008 const struct kvm_mmio_range
*r
= ranges
;
1011 if (offset
>= r
->base
&&
1012 (offset
+ mmio
->len
) <= (r
->base
+ r
->len
))
1020 static bool vgic_validate_access(const struct vgic_dist
*dist
,
1021 const struct kvm_mmio_range
*range
,
1022 unsigned long offset
)
1026 if (!range
->bits_per_irq
)
1027 return true; /* Not an irq-based access */
1029 irq
= offset
* 8 / range
->bits_per_irq
;
1030 if (irq
>= dist
->nr_irqs
)
1037 * Call the respective handler function for the given range.
1038 * We split up any 64 bit accesses into two consecutive 32 bit
1039 * handler calls and merge the result afterwards.
1040 * We do this in a little endian fashion regardless of the host's
1041 * or guest's endianness, because the GIC is always LE and the rest of
1042 * the code (vgic_reg_access) also puts it in a LE fashion already.
1043 * At this point we have already identified the handle function, so
1044 * range points to that one entry and offset is relative to this.
1046 static bool call_range_handler(struct kvm_vcpu
*vcpu
,
1047 struct kvm_exit_mmio
*mmio
,
1048 unsigned long offset
,
1049 const struct kvm_mmio_range
*range
)
1051 u32
*data32
= (void *)mmio
->data
;
1052 struct kvm_exit_mmio mmio32
;
1055 if (likely(mmio
->len
<= 4))
1056 return range
->handle_mmio(vcpu
, mmio
, offset
);
1059 * Any access bigger than 4 bytes (that we currently handle in KVM)
1060 * is actually 8 bytes long, caused by a 64-bit access
1064 mmio32
.is_write
= mmio
->is_write
;
1066 mmio32
.phys_addr
= mmio
->phys_addr
+ 4;
1068 *(u32
*)mmio32
.data
= data32
[1];
1069 ret
= range
->handle_mmio(vcpu
, &mmio32
, offset
+ 4);
1070 if (!mmio
->is_write
)
1071 data32
[1] = *(u32
*)mmio32
.data
;
1073 mmio32
.phys_addr
= mmio
->phys_addr
;
1075 *(u32
*)mmio32
.data
= data32
[0];
1076 ret
|= range
->handle_mmio(vcpu
, &mmio32
, offset
);
1077 if (!mmio
->is_write
)
1078 data32
[0] = *(u32
*)mmio32
.data
;
1084 * vgic_handle_mmio_range - handle an in-kernel MMIO access
1085 * @vcpu: pointer to the vcpu performing the access
1086 * @run: pointer to the kvm_run structure
1087 * @mmio: pointer to the data describing the access
1088 * @ranges: array of MMIO ranges in a given region
1089 * @mmio_base: base address of that region
1091 * returns true if the MMIO access could be performed
1093 bool vgic_handle_mmio_range(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
,
1094 struct kvm_exit_mmio
*mmio
,
1095 const struct kvm_mmio_range
*ranges
,
1096 unsigned long mmio_base
)
1098 const struct kvm_mmio_range
*range
;
1099 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1101 unsigned long offset
;
1103 offset
= mmio
->phys_addr
- mmio_base
;
1104 range
= vgic_find_range(ranges
, mmio
, offset
);
1105 if (unlikely(!range
|| !range
->handle_mmio
)) {
1106 pr_warn("Unhandled access %d %08llx %d\n",
1107 mmio
->is_write
, mmio
->phys_addr
, mmio
->len
);
1111 spin_lock(&vcpu
->kvm
->arch
.vgic
.lock
);
1112 offset
-= range
->base
;
1113 if (vgic_validate_access(dist
, range
, offset
)) {
1114 updated_state
= call_range_handler(vcpu
, mmio
, offset
, range
);
1116 if (!mmio
->is_write
)
1117 memset(mmio
->data
, 0, mmio
->len
);
1118 updated_state
= false;
1120 spin_unlock(&vcpu
->kvm
->arch
.vgic
.lock
);
1121 kvm_prepare_mmio(run
, mmio
);
1122 kvm_handle_mmio_return(vcpu
, run
);
1125 vgic_kick_vcpus(vcpu
->kvm
);
1130 static bool vgic_v2_handle_mmio(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
,
1131 struct kvm_exit_mmio
*mmio
)
1133 unsigned long base
= vcpu
->kvm
->arch
.vgic
.vgic_dist_base
;
1135 if (!is_in_range(mmio
->phys_addr
, mmio
->len
, base
,
1136 KVM_VGIC_V2_DIST_SIZE
))
1139 /* GICv2 does not support accesses wider than 32 bits */
1140 if (mmio
->len
> 4) {
1141 kvm_inject_dabt(vcpu
, mmio
->phys_addr
);
1145 return vgic_handle_mmio_range(vcpu
, run
, mmio
, vgic_dist_ranges
, base
);
1149 * vgic_handle_mmio - handle an in-kernel MMIO access for the GIC emulation
1150 * @vcpu: pointer to the vcpu performing the access
1151 * @run: pointer to the kvm_run structure
1152 * @mmio: pointer to the data describing the access
1154 * returns true if the MMIO access has been performed in kernel space,
1155 * and false if it needs to be emulated in user space.
1156 * Calls the actual handling routine for the selected VGIC model.
1158 bool vgic_handle_mmio(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
,
1159 struct kvm_exit_mmio
*mmio
)
1161 if (!irqchip_in_kernel(vcpu
->kvm
))
1165 * This will currently call either vgic_v2_handle_mmio() or
1166 * vgic_v3_handle_mmio(), which in turn will call
1167 * vgic_handle_mmio_range() defined above.
1169 return vcpu
->kvm
->arch
.vgic
.vm_ops
.handle_mmio(vcpu
, run
, mmio
);
1172 static u8
*vgic_get_sgi_sources(struct vgic_dist
*dist
, int vcpu_id
, int sgi
)
1174 return dist
->irq_sgi_sources
+ vcpu_id
* VGIC_NR_SGIS
+ sgi
;
1177 static void vgic_dispatch_sgi(struct kvm_vcpu
*vcpu
, u32 reg
)
1179 struct kvm
*kvm
= vcpu
->kvm
;
1180 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1181 int nrcpus
= atomic_read(&kvm
->online_vcpus
);
1183 int sgi
, mode
, c
, vcpu_id
;
1185 vcpu_id
= vcpu
->vcpu_id
;
1188 target_cpus
= (reg
>> 16) & 0xff;
1189 mode
= (reg
>> 24) & 3;
1198 target_cpus
= ((1 << nrcpus
) - 1) & ~(1 << vcpu_id
) & 0xff;
1202 target_cpus
= 1 << vcpu_id
;
1206 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1207 if (target_cpus
& 1) {
1208 /* Flag the SGI as pending */
1209 vgic_dist_irq_set_pending(vcpu
, sgi
);
1210 *vgic_get_sgi_sources(dist
, c
, sgi
) |= 1 << vcpu_id
;
1211 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi
, vcpu_id
, c
);
1218 static int vgic_nr_shared_irqs(struct vgic_dist
*dist
)
1220 return dist
->nr_irqs
- VGIC_NR_PRIVATE_IRQS
;
1223 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
)
1225 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1226 unsigned long *pending
, *enabled
, *pend_percpu
, *pend_shared
;
1227 unsigned long pending_private
, pending_shared
;
1228 int nr_shared
= vgic_nr_shared_irqs(dist
);
1231 vcpu_id
= vcpu
->vcpu_id
;
1232 pend_percpu
= vcpu
->arch
.vgic_cpu
.pending_percpu
;
1233 pend_shared
= vcpu
->arch
.vgic_cpu
.pending_shared
;
1235 pending
= vgic_bitmap_get_cpu_map(&dist
->irq_pending
, vcpu_id
);
1236 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
1237 bitmap_and(pend_percpu
, pending
, enabled
, VGIC_NR_PRIVATE_IRQS
);
1239 pending
= vgic_bitmap_get_shared_map(&dist
->irq_pending
);
1240 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
1241 bitmap_and(pend_shared
, pending
, enabled
, nr_shared
);
1242 bitmap_and(pend_shared
, pend_shared
,
1243 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
1246 pending_private
= find_first_bit(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
1247 pending_shared
= find_first_bit(pend_shared
, nr_shared
);
1248 return (pending_private
< VGIC_NR_PRIVATE_IRQS
||
1249 pending_shared
< vgic_nr_shared_irqs(dist
));
1253 * Update the interrupt state and determine which CPUs have pending
1254 * interrupts. Must be called with distributor lock held.
1256 void vgic_update_state(struct kvm
*kvm
)
1258 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1259 struct kvm_vcpu
*vcpu
;
1262 if (!dist
->enabled
) {
1263 set_bit(0, dist
->irq_pending_on_cpu
);
1267 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1268 if (compute_pending_for_cpu(vcpu
)) {
1269 pr_debug("CPU%d has pending interrupts\n", c
);
1270 set_bit(c
, dist
->irq_pending_on_cpu
);
1275 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
)
1277 return vgic_ops
->get_lr(vcpu
, lr
);
1280 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
,
1283 vgic_ops
->set_lr(vcpu
, lr
, vlr
);
1286 static void vgic_sync_lr_elrsr(struct kvm_vcpu
*vcpu
, int lr
,
1289 vgic_ops
->sync_lr_elrsr(vcpu
, lr
, vlr
);
1292 static inline u64
vgic_get_elrsr(struct kvm_vcpu
*vcpu
)
1294 return vgic_ops
->get_elrsr(vcpu
);
1297 static inline u64
vgic_get_eisr(struct kvm_vcpu
*vcpu
)
1299 return vgic_ops
->get_eisr(vcpu
);
1302 static inline u32
vgic_get_interrupt_status(struct kvm_vcpu
*vcpu
)
1304 return vgic_ops
->get_interrupt_status(vcpu
);
1307 static inline void vgic_enable_underflow(struct kvm_vcpu
*vcpu
)
1309 vgic_ops
->enable_underflow(vcpu
);
1312 static inline void vgic_disable_underflow(struct kvm_vcpu
*vcpu
)
1314 vgic_ops
->disable_underflow(vcpu
);
1317 void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1319 vgic_ops
->get_vmcr(vcpu
, vmcr
);
1322 void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1324 vgic_ops
->set_vmcr(vcpu
, vmcr
);
1327 static inline void vgic_enable(struct kvm_vcpu
*vcpu
)
1329 vgic_ops
->enable(vcpu
);
1332 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
)
1334 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1335 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr_nr
);
1338 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1339 clear_bit(lr_nr
, vgic_cpu
->lr_used
);
1340 vgic_cpu
->vgic_irq_lr_map
[irq
] = LR_EMPTY
;
1344 * An interrupt may have been disabled after being made pending on the
1345 * CPU interface (the classic case is a timer running while we're
1346 * rebooting the guest - the interrupt would kick as soon as the CPU
1347 * interface gets enabled, with deadly consequences).
1349 * The solution is to examine already active LRs, and check the
1350 * interrupt is still enabled. If not, just retire it.
1352 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
)
1354 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1357 for_each_set_bit(lr
, vgic_cpu
->lr_used
, vgic
->nr_lr
) {
1358 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1360 if (!vgic_irq_is_enabled(vcpu
, vlr
.irq
)) {
1361 vgic_retire_lr(lr
, vlr
.irq
, vcpu
);
1362 if (vgic_irq_is_queued(vcpu
, vlr
.irq
))
1363 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1369 * Queue an interrupt to a CPU virtual interface. Return true on success,
1370 * or false if it wasn't possible to queue it.
1372 bool vgic_queue_irq(struct kvm_vcpu
*vcpu
, u8 sgi_source_id
, int irq
)
1374 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1375 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1379 /* Sanitize the input... */
1380 BUG_ON(sgi_source_id
& ~7);
1381 BUG_ON(sgi_source_id
&& irq
>= VGIC_NR_SGIS
);
1382 BUG_ON(irq
>= dist
->nr_irqs
);
1384 kvm_debug("Queue IRQ%d\n", irq
);
1386 lr
= vgic_cpu
->vgic_irq_lr_map
[irq
];
1388 /* Do we have an active interrupt for the same CPUID? */
1389 if (lr
!= LR_EMPTY
) {
1390 vlr
= vgic_get_lr(vcpu
, lr
);
1391 if (vlr
.source
== sgi_source_id
) {
1392 kvm_debug("LR%d piggyback for IRQ%d\n", lr
, vlr
.irq
);
1393 BUG_ON(!test_bit(lr
, vgic_cpu
->lr_used
));
1394 vlr
.state
|= LR_STATE_PENDING
;
1395 vgic_set_lr(vcpu
, lr
, vlr
);
1400 /* Try to use another LR for this interrupt */
1401 lr
= find_first_zero_bit((unsigned long *)vgic_cpu
->lr_used
,
1403 if (lr
>= vgic
->nr_lr
)
1406 kvm_debug("LR%d allocated for IRQ%d %x\n", lr
, irq
, sgi_source_id
);
1407 vgic_cpu
->vgic_irq_lr_map
[irq
] = lr
;
1408 set_bit(lr
, vgic_cpu
->lr_used
);
1411 vlr
.source
= sgi_source_id
;
1412 vlr
.state
= LR_STATE_PENDING
;
1413 if (!vgic_irq_is_edge(vcpu
, irq
))
1414 vlr
.state
|= LR_EOI_INT
;
1416 vgic_set_lr(vcpu
, lr
, vlr
);
1421 static bool vgic_v2_queue_sgi(struct kvm_vcpu
*vcpu
, int irq
)
1423 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1424 unsigned long sources
;
1425 int vcpu_id
= vcpu
->vcpu_id
;
1428 sources
= *vgic_get_sgi_sources(dist
, vcpu_id
, irq
);
1430 for_each_set_bit(c
, &sources
, dist
->nr_cpus
) {
1431 if (vgic_queue_irq(vcpu
, c
, irq
))
1432 clear_bit(c
, &sources
);
1435 *vgic_get_sgi_sources(dist
, vcpu_id
, irq
) = sources
;
1438 * If the sources bitmap has been cleared it means that we
1439 * could queue all the SGIs onto link registers (see the
1440 * clear_bit above), and therefore we are done with them in
1441 * our emulated gic and can get rid of them.
1444 vgic_dist_irq_clear_pending(vcpu
, irq
);
1445 vgic_cpu_irq_clear(vcpu
, irq
);
1452 static bool vgic_queue_hwirq(struct kvm_vcpu
*vcpu
, int irq
)
1454 if (!vgic_can_sample_irq(vcpu
, irq
))
1455 return true; /* level interrupt, already queued */
1457 if (vgic_queue_irq(vcpu
, 0, irq
)) {
1458 if (vgic_irq_is_edge(vcpu
, irq
)) {
1459 vgic_dist_irq_clear_pending(vcpu
, irq
);
1460 vgic_cpu_irq_clear(vcpu
, irq
);
1462 vgic_irq_set_queued(vcpu
, irq
);
1472 * Fill the list registers with pending interrupts before running the
1475 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1477 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1478 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1482 vcpu_id
= vcpu
->vcpu_id
;
1485 * We may not have any pending interrupt, or the interrupts
1486 * may have been serviced from another vcpu. In all cases,
1489 if (!kvm_vgic_vcpu_pending_irq(vcpu
)) {
1490 pr_debug("CPU%d has no pending interrupt\n", vcpu_id
);
1495 for_each_set_bit(i
, vgic_cpu
->pending_percpu
, VGIC_NR_SGIS
) {
1496 if (!queue_sgi(vcpu
, i
))
1501 for_each_set_bit_from(i
, vgic_cpu
->pending_percpu
, VGIC_NR_PRIVATE_IRQS
) {
1502 if (!vgic_queue_hwirq(vcpu
, i
))
1507 for_each_set_bit(i
, vgic_cpu
->pending_shared
, vgic_nr_shared_irqs(dist
)) {
1508 if (!vgic_queue_hwirq(vcpu
, i
+ VGIC_NR_PRIVATE_IRQS
))
1514 vgic_enable_underflow(vcpu
);
1516 vgic_disable_underflow(vcpu
);
1518 * We're about to run this VCPU, and we've consumed
1519 * everything the distributor had in store for
1520 * us. Claim we don't have anything pending. We'll
1521 * adjust that if needed while exiting.
1523 clear_bit(vcpu_id
, dist
->irq_pending_on_cpu
);
1527 static bool vgic_process_maintenance(struct kvm_vcpu
*vcpu
)
1529 u32 status
= vgic_get_interrupt_status(vcpu
);
1530 bool level_pending
= false;
1532 kvm_debug("STATUS = %08x\n", status
);
1534 if (status
& INT_STATUS_EOI
) {
1536 * Some level interrupts have been EOIed. Clear their
1539 u64 eisr
= vgic_get_eisr(vcpu
);
1540 unsigned long *eisr_ptr
= u64_to_bitmask(&eisr
);
1543 for_each_set_bit(lr
, eisr_ptr
, vgic
->nr_lr
) {
1544 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1545 WARN_ON(vgic_irq_is_edge(vcpu
, vlr
.irq
));
1547 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1548 WARN_ON(vlr
.state
& LR_STATE_MASK
);
1550 vgic_set_lr(vcpu
, lr
, vlr
);
1553 * If the IRQ was EOIed it was also ACKed and we we
1554 * therefore assume we can clear the soft pending
1555 * state (should it had been set) for this interrupt.
1557 * Note: if the IRQ soft pending state was set after
1558 * the IRQ was acked, it actually shouldn't be
1559 * cleared, but we have no way of knowing that unless
1560 * we start trapping ACKs when the soft-pending state
1563 vgic_dist_irq_clear_soft_pend(vcpu
, vlr
.irq
);
1565 /* Any additional pending interrupt? */
1566 if (vgic_dist_irq_get_level(vcpu
, vlr
.irq
)) {
1567 vgic_cpu_irq_set(vcpu
, vlr
.irq
);
1568 level_pending
= true;
1570 vgic_dist_irq_clear_pending(vcpu
, vlr
.irq
);
1571 vgic_cpu_irq_clear(vcpu
, vlr
.irq
);
1575 * Despite being EOIed, the LR may not have
1576 * been marked as empty.
1578 vgic_sync_lr_elrsr(vcpu
, lr
, vlr
);
1582 if (status
& INT_STATUS_UNDERFLOW
)
1583 vgic_disable_underflow(vcpu
);
1585 return level_pending
;
1589 * Sync back the VGIC state after a guest run. The distributor lock is
1590 * needed so we don't get preempted in the middle of the state processing.
1592 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1594 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1595 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1597 unsigned long *elrsr_ptr
;
1601 level_pending
= vgic_process_maintenance(vcpu
);
1602 elrsr
= vgic_get_elrsr(vcpu
);
1603 elrsr_ptr
= u64_to_bitmask(&elrsr
);
1605 /* Clear mappings for empty LRs */
1606 for_each_set_bit(lr
, elrsr_ptr
, vgic
->nr_lr
) {
1609 if (!test_and_clear_bit(lr
, vgic_cpu
->lr_used
))
1612 vlr
= vgic_get_lr(vcpu
, lr
);
1614 BUG_ON(vlr
.irq
>= dist
->nr_irqs
);
1615 vgic_cpu
->vgic_irq_lr_map
[vlr
.irq
] = LR_EMPTY
;
1618 /* Check if we still have something up our sleeve... */
1619 pending
= find_first_zero_bit(elrsr_ptr
, vgic
->nr_lr
);
1620 if (level_pending
|| pending
< vgic
->nr_lr
)
1621 set_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
1624 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1626 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1628 if (!irqchip_in_kernel(vcpu
->kvm
))
1631 spin_lock(&dist
->lock
);
1632 __kvm_vgic_flush_hwstate(vcpu
);
1633 spin_unlock(&dist
->lock
);
1636 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1638 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1640 if (!irqchip_in_kernel(vcpu
->kvm
))
1643 spin_lock(&dist
->lock
);
1644 __kvm_vgic_sync_hwstate(vcpu
);
1645 spin_unlock(&dist
->lock
);
1648 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
)
1650 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1652 if (!irqchip_in_kernel(vcpu
->kvm
))
1655 return test_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
1658 void vgic_kick_vcpus(struct kvm
*kvm
)
1660 struct kvm_vcpu
*vcpu
;
1664 * We've injected an interrupt, time to find out who deserves
1667 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1668 if (kvm_vgic_vcpu_pending_irq(vcpu
))
1669 kvm_vcpu_kick(vcpu
);
1673 static int vgic_validate_injection(struct kvm_vcpu
*vcpu
, int irq
, int level
)
1675 int edge_triggered
= vgic_irq_is_edge(vcpu
, irq
);
1678 * Only inject an interrupt if:
1679 * - edge triggered and we have a rising edge
1680 * - level triggered and we change level
1682 if (edge_triggered
) {
1683 int state
= vgic_dist_irq_is_pending(vcpu
, irq
);
1684 return level
> state
;
1686 int state
= vgic_dist_irq_get_level(vcpu
, irq
);
1687 return level
!= state
;
1691 static int vgic_update_irq_pending(struct kvm
*kvm
, int cpuid
,
1692 unsigned int irq_num
, bool level
)
1694 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1695 struct kvm_vcpu
*vcpu
;
1696 int edge_triggered
, level_triggered
;
1700 spin_lock(&dist
->lock
);
1702 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1703 edge_triggered
= vgic_irq_is_edge(vcpu
, irq_num
);
1704 level_triggered
= !edge_triggered
;
1706 if (!vgic_validate_injection(vcpu
, irq_num
, level
)) {
1711 if (irq_num
>= VGIC_NR_PRIVATE_IRQS
) {
1712 cpuid
= dist
->irq_spi_cpu
[irq_num
- VGIC_NR_PRIVATE_IRQS
];
1713 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1716 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num
, level
, cpuid
);
1719 if (level_triggered
)
1720 vgic_dist_irq_set_level(vcpu
, irq_num
);
1721 vgic_dist_irq_set_pending(vcpu
, irq_num
);
1723 if (level_triggered
) {
1724 vgic_dist_irq_clear_level(vcpu
, irq_num
);
1725 if (!vgic_dist_irq_soft_pend(vcpu
, irq_num
))
1726 vgic_dist_irq_clear_pending(vcpu
, irq_num
);
1733 enabled
= vgic_irq_is_enabled(vcpu
, irq_num
);
1740 if (!vgic_can_sample_irq(vcpu
, irq_num
)) {
1742 * Level interrupt in progress, will be picked up
1750 vgic_cpu_irq_set(vcpu
, irq_num
);
1751 set_bit(cpuid
, dist
->irq_pending_on_cpu
);
1755 spin_unlock(&dist
->lock
);
1757 return ret
? cpuid
: -EINVAL
;
1761 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1762 * @kvm: The VM structure pointer
1763 * @cpuid: The CPU for PPIs
1764 * @irq_num: The IRQ number that is assigned to the device
1765 * @level: Edge-triggered: true: to trigger the interrupt
1766 * false: to ignore the call
1767 * Level-sensitive true: activates an interrupt
1768 * false: deactivates an interrupt
1770 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1771 * level-sensitive interrupts. You can think of the level parameter as 1
1772 * being HIGH and 0 being LOW and all devices being active-HIGH.
1774 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int irq_num
,
1780 if (unlikely(!vgic_initialized(kvm
))) {
1782 * We only provide the automatic initialization of the VGIC
1783 * for the legacy case of a GICv2. Any other type must
1784 * be explicitly initialized once setup with the respective
1787 if (kvm
->arch
.vgic
.vgic_model
!= KVM_DEV_TYPE_ARM_VGIC_V2
) {
1791 mutex_lock(&kvm
->lock
);
1792 ret
= vgic_init(kvm
);
1793 mutex_unlock(&kvm
->lock
);
1799 vcpu_id
= vgic_update_irq_pending(kvm
, cpuid
, irq_num
, level
);
1801 /* kick the specified vcpu */
1802 kvm_vcpu_kick(kvm_get_vcpu(kvm
, vcpu_id
));
1809 static irqreturn_t
vgic_maintenance_handler(int irq
, void *data
)
1812 * We cannot rely on the vgic maintenance interrupt to be
1813 * delivered synchronously. This means we can only use it to
1814 * exit the VM, and we perform the handling of EOIed
1815 * interrupts on the exit path (see vgic_process_maintenance).
1820 void kvm_vgic_vcpu_destroy(struct kvm_vcpu
*vcpu
)
1822 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1824 kfree(vgic_cpu
->pending_shared
);
1825 kfree(vgic_cpu
->vgic_irq_lr_map
);
1826 vgic_cpu
->pending_shared
= NULL
;
1827 vgic_cpu
->vgic_irq_lr_map
= NULL
;
1830 static int vgic_vcpu_init_maps(struct kvm_vcpu
*vcpu
, int nr_irqs
)
1832 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1834 int sz
= (nr_irqs
- VGIC_NR_PRIVATE_IRQS
) / 8;
1835 vgic_cpu
->pending_shared
= kzalloc(sz
, GFP_KERNEL
);
1836 vgic_cpu
->vgic_irq_lr_map
= kmalloc(nr_irqs
, GFP_KERNEL
);
1838 if (!vgic_cpu
->pending_shared
|| !vgic_cpu
->vgic_irq_lr_map
) {
1839 kvm_vgic_vcpu_destroy(vcpu
);
1843 memset(vgic_cpu
->vgic_irq_lr_map
, LR_EMPTY
, nr_irqs
);
1846 * Store the number of LRs per vcpu, so we don't have to go
1847 * all the way to the distributor structure to find out. Only
1848 * assembly code should use this one.
1850 vgic_cpu
->nr_lr
= vgic
->nr_lr
;
1856 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
1858 * The host's GIC naturally limits the maximum amount of VCPUs a guest
1861 int kvm_vgic_get_max_vcpus(void)
1863 return vgic
->max_gic_vcpus
;
1866 void kvm_vgic_destroy(struct kvm
*kvm
)
1868 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1869 struct kvm_vcpu
*vcpu
;
1872 kvm_for_each_vcpu(i
, vcpu
, kvm
)
1873 kvm_vgic_vcpu_destroy(vcpu
);
1875 vgic_free_bitmap(&dist
->irq_enabled
);
1876 vgic_free_bitmap(&dist
->irq_level
);
1877 vgic_free_bitmap(&dist
->irq_pending
);
1878 vgic_free_bitmap(&dist
->irq_soft_pend
);
1879 vgic_free_bitmap(&dist
->irq_queued
);
1880 vgic_free_bitmap(&dist
->irq_cfg
);
1881 vgic_free_bytemap(&dist
->irq_priority
);
1882 if (dist
->irq_spi_target
) {
1883 for (i
= 0; i
< dist
->nr_cpus
; i
++)
1884 vgic_free_bitmap(&dist
->irq_spi_target
[i
]);
1886 kfree(dist
->irq_sgi_sources
);
1887 kfree(dist
->irq_spi_cpu
);
1888 kfree(dist
->irq_spi_target
);
1889 kfree(dist
->irq_pending_on_cpu
);
1890 dist
->irq_sgi_sources
= NULL
;
1891 dist
->irq_spi_cpu
= NULL
;
1892 dist
->irq_spi_target
= NULL
;
1893 dist
->irq_pending_on_cpu
= NULL
;
1897 static int vgic_v2_init_model(struct kvm
*kvm
)
1901 for (i
= VGIC_NR_PRIVATE_IRQS
; i
< kvm
->arch
.vgic
.nr_irqs
; i
+= 4)
1902 vgic_set_target_reg(kvm
, 0, i
);
1908 * Allocate and initialize the various data structures. Must be called
1909 * with kvm->lock held!
1911 int vgic_init(struct kvm
*kvm
)
1913 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1914 struct kvm_vcpu
*vcpu
;
1915 int nr_cpus
, nr_irqs
;
1916 int ret
, i
, vcpu_id
;
1918 if (vgic_initialized(kvm
))
1921 nr_cpus
= dist
->nr_cpus
= atomic_read(&kvm
->online_vcpus
);
1922 if (!nr_cpus
) /* No vcpus? Can't be good... */
1926 * If nobody configured the number of interrupts, use the
1930 dist
->nr_irqs
= VGIC_NR_IRQS_LEGACY
;
1932 nr_irqs
= dist
->nr_irqs
;
1934 ret
= vgic_init_bitmap(&dist
->irq_enabled
, nr_cpus
, nr_irqs
);
1935 ret
|= vgic_init_bitmap(&dist
->irq_level
, nr_cpus
, nr_irqs
);
1936 ret
|= vgic_init_bitmap(&dist
->irq_pending
, nr_cpus
, nr_irqs
);
1937 ret
|= vgic_init_bitmap(&dist
->irq_soft_pend
, nr_cpus
, nr_irqs
);
1938 ret
|= vgic_init_bitmap(&dist
->irq_queued
, nr_cpus
, nr_irqs
);
1939 ret
|= vgic_init_bitmap(&dist
->irq_cfg
, nr_cpus
, nr_irqs
);
1940 ret
|= vgic_init_bytemap(&dist
->irq_priority
, nr_cpus
, nr_irqs
);
1945 dist
->irq_sgi_sources
= kzalloc(nr_cpus
* VGIC_NR_SGIS
, GFP_KERNEL
);
1946 dist
->irq_spi_cpu
= kzalloc(nr_irqs
- VGIC_NR_PRIVATE_IRQS
, GFP_KERNEL
);
1947 dist
->irq_spi_target
= kzalloc(sizeof(*dist
->irq_spi_target
) * nr_cpus
,
1949 dist
->irq_pending_on_cpu
= kzalloc(BITS_TO_LONGS(nr_cpus
) * sizeof(long),
1951 if (!dist
->irq_sgi_sources
||
1952 !dist
->irq_spi_cpu
||
1953 !dist
->irq_spi_target
||
1954 !dist
->irq_pending_on_cpu
) {
1959 for (i
= 0; i
< nr_cpus
; i
++)
1960 ret
|= vgic_init_bitmap(&dist
->irq_spi_target
[i
],
1966 ret
= kvm
->arch
.vgic
.vm_ops
.init_model(kvm
);
1970 kvm_for_each_vcpu(vcpu_id
, vcpu
, kvm
) {
1971 ret
= vgic_vcpu_init_maps(vcpu
, nr_irqs
);
1973 kvm_err("VGIC: Failed to allocate vcpu memory\n");
1977 for (i
= 0; i
< dist
->nr_irqs
; i
++) {
1978 if (i
< VGIC_NR_PPIS
)
1979 vgic_bitmap_set_irq_val(&dist
->irq_enabled
,
1980 vcpu
->vcpu_id
, i
, 1);
1981 if (i
< VGIC_NR_PRIVATE_IRQS
)
1982 vgic_bitmap_set_irq_val(&dist
->irq_cfg
,
1992 kvm_vgic_destroy(kvm
);
1998 * kvm_vgic_map_resources - Configure global VGIC state before running any VCPUs
1999 * @kvm: pointer to the kvm struct
2001 * Map the virtual CPU interface into the VM before running any VCPUs. We
2002 * can't do this at creation time, because user space must first set the
2003 * virtual CPU interface address in the guest physical address space.
2005 static int vgic_v2_map_resources(struct kvm
*kvm
,
2006 const struct vgic_params
*params
)
2010 if (!irqchip_in_kernel(kvm
))
2013 mutex_lock(&kvm
->lock
);
2015 if (vgic_ready(kvm
))
2018 if (IS_VGIC_ADDR_UNDEF(kvm
->arch
.vgic
.vgic_dist_base
) ||
2019 IS_VGIC_ADDR_UNDEF(kvm
->arch
.vgic
.vgic_cpu_base
)) {
2020 kvm_err("Need to set vgic cpu and dist addresses first\n");
2026 * Initialize the vgic if this hasn't already been done on demand by
2027 * accessing the vgic state from userspace.
2029 ret
= vgic_init(kvm
);
2031 kvm_err("Unable to allocate maps\n");
2035 ret
= kvm_phys_addr_ioremap(kvm
, kvm
->arch
.vgic
.vgic_cpu_base
,
2036 params
->vcpu_base
, KVM_VGIC_V2_CPU_SIZE
,
2039 kvm_err("Unable to remap VGIC CPU to VCPU\n");
2043 kvm
->arch
.vgic
.ready
= true;
2046 kvm_vgic_destroy(kvm
);
2047 mutex_unlock(&kvm
->lock
);
2051 void vgic_v2_init_emulation(struct kvm
*kvm
)
2053 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
2055 dist
->vm_ops
.handle_mmio
= vgic_v2_handle_mmio
;
2056 dist
->vm_ops
.queue_sgi
= vgic_v2_queue_sgi
;
2057 dist
->vm_ops
.add_sgi_source
= vgic_v2_add_sgi_source
;
2058 dist
->vm_ops
.init_model
= vgic_v2_init_model
;
2059 dist
->vm_ops
.map_resources
= vgic_v2_map_resources
;
2061 kvm
->arch
.max_vcpus
= VGIC_V2_MAX_CPUS
;
2064 static int init_vgic_model(struct kvm
*kvm
, int type
)
2067 case KVM_DEV_TYPE_ARM_VGIC_V2
:
2068 vgic_v2_init_emulation(kvm
);
2074 if (atomic_read(&kvm
->online_vcpus
) > kvm
->arch
.max_vcpus
)
2080 int kvm_vgic_create(struct kvm
*kvm
, u32 type
)
2082 int i
, vcpu_lock_idx
= -1, ret
;
2083 struct kvm_vcpu
*vcpu
;
2085 mutex_lock(&kvm
->lock
);
2087 if (irqchip_in_kernel(kvm
)) {
2093 * Any time a vcpu is run, vcpu_load is called which tries to grab the
2094 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
2095 * that no other VCPUs are run while we create the vgic.
2098 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
2099 if (!mutex_trylock(&vcpu
->mutex
))
2104 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
2105 if (vcpu
->arch
.has_run_once
)
2110 ret
= init_vgic_model(kvm
, type
);
2114 spin_lock_init(&kvm
->arch
.vgic
.lock
);
2115 kvm
->arch
.vgic
.in_kernel
= true;
2116 kvm
->arch
.vgic
.vgic_model
= type
;
2117 kvm
->arch
.vgic
.vctrl_base
= vgic
->vctrl_base
;
2118 kvm
->arch
.vgic
.vgic_dist_base
= VGIC_ADDR_UNDEF
;
2119 kvm
->arch
.vgic
.vgic_cpu_base
= VGIC_ADDR_UNDEF
;
2122 for (; vcpu_lock_idx
>= 0; vcpu_lock_idx
--) {
2123 vcpu
= kvm_get_vcpu(kvm
, vcpu_lock_idx
);
2124 mutex_unlock(&vcpu
->mutex
);
2128 mutex_unlock(&kvm
->lock
);
2132 static int vgic_ioaddr_overlap(struct kvm
*kvm
)
2134 phys_addr_t dist
= kvm
->arch
.vgic
.vgic_dist_base
;
2135 phys_addr_t cpu
= kvm
->arch
.vgic
.vgic_cpu_base
;
2137 if (IS_VGIC_ADDR_UNDEF(dist
) || IS_VGIC_ADDR_UNDEF(cpu
))
2139 if ((dist
<= cpu
&& dist
+ KVM_VGIC_V2_DIST_SIZE
> cpu
) ||
2140 (cpu
<= dist
&& cpu
+ KVM_VGIC_V2_CPU_SIZE
> dist
))
2145 static int vgic_ioaddr_assign(struct kvm
*kvm
, phys_addr_t
*ioaddr
,
2146 phys_addr_t addr
, phys_addr_t size
)
2150 if (addr
& ~KVM_PHYS_MASK
)
2153 if (addr
& (SZ_4K
- 1))
2156 if (!IS_VGIC_ADDR_UNDEF(*ioaddr
))
2158 if (addr
+ size
< addr
)
2162 ret
= vgic_ioaddr_overlap(kvm
);
2164 *ioaddr
= VGIC_ADDR_UNDEF
;
2170 * kvm_vgic_addr - set or get vgic VM base addresses
2171 * @kvm: pointer to the vm struct
2172 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
2173 * @addr: pointer to address value
2174 * @write: if true set the address in the VM address space, if false read the
2177 * Set or get the vgic base addresses for the distributor and the virtual CPU
2178 * interface in the VM physical address space. These addresses are properties
2179 * of the emulated core/SoC and therefore user space initially knows this
2182 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
)
2185 struct vgic_dist
*vgic
= &kvm
->arch
.vgic
;
2187 mutex_lock(&kvm
->lock
);
2189 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
2191 r
= vgic_ioaddr_assign(kvm
, &vgic
->vgic_dist_base
,
2192 *addr
, KVM_VGIC_V2_DIST_SIZE
);
2194 *addr
= vgic
->vgic_dist_base
;
2197 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
2199 r
= vgic_ioaddr_assign(kvm
, &vgic
->vgic_cpu_base
,
2200 *addr
, KVM_VGIC_V2_CPU_SIZE
);
2202 *addr
= vgic
->vgic_cpu_base
;
2209 mutex_unlock(&kvm
->lock
);
2213 static bool handle_cpu_mmio_misc(struct kvm_vcpu
*vcpu
,
2214 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
2216 bool updated
= false;
2217 struct vgic_vmcr vmcr
;
2221 vgic_get_vmcr(vcpu
, &vmcr
);
2223 switch (offset
& ~0x3) {
2225 vmcr_field
= &vmcr
.ctlr
;
2227 case GIC_CPU_PRIMASK
:
2228 vmcr_field
= &vmcr
.pmr
;
2230 case GIC_CPU_BINPOINT
:
2231 vmcr_field
= &vmcr
.bpr
;
2233 case GIC_CPU_ALIAS_BINPOINT
:
2234 vmcr_field
= &vmcr
.abpr
;
2240 if (!mmio
->is_write
) {
2242 mmio_data_write(mmio
, ~0, reg
);
2244 reg
= mmio_data_read(mmio
, ~0);
2245 if (reg
!= *vmcr_field
) {
2247 vgic_set_vmcr(vcpu
, &vmcr
);
2254 static bool handle_mmio_abpr(struct kvm_vcpu
*vcpu
,
2255 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
2257 return handle_cpu_mmio_misc(vcpu
, mmio
, GIC_CPU_ALIAS_BINPOINT
);
2260 static bool handle_cpu_mmio_ident(struct kvm_vcpu
*vcpu
,
2261 struct kvm_exit_mmio
*mmio
,
2270 reg
= (PRODUCT_ID_KVM
<< 20) |
2271 (GICC_ARCH_VERSION_V2
<< 16) |
2272 (IMPLEMENTER_ARM
<< 0);
2273 mmio_data_write(mmio
, ~0, reg
);
2278 * CPU Interface Register accesses - these are not accessed by the VM, but by
2279 * user space for saving and restoring VGIC state.
2281 static const struct kvm_mmio_range vgic_cpu_ranges
[] = {
2283 .base
= GIC_CPU_CTRL
,
2285 .handle_mmio
= handle_cpu_mmio_misc
,
2288 .base
= GIC_CPU_ALIAS_BINPOINT
,
2290 .handle_mmio
= handle_mmio_abpr
,
2293 .base
= GIC_CPU_ACTIVEPRIO
,
2295 .handle_mmio
= handle_mmio_raz_wi
,
2298 .base
= GIC_CPU_IDENT
,
2300 .handle_mmio
= handle_cpu_mmio_ident
,
2304 static int vgic_attr_regs_access(struct kvm_device
*dev
,
2305 struct kvm_device_attr
*attr
,
2306 u32
*reg
, bool is_write
)
2308 const struct kvm_mmio_range
*r
= NULL
, *ranges
;
2311 struct kvm_vcpu
*vcpu
, *tmp_vcpu
;
2312 struct vgic_dist
*vgic
;
2313 struct kvm_exit_mmio mmio
;
2315 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
2316 cpuid
= (attr
->attr
& KVM_DEV_ARM_VGIC_CPUID_MASK
) >>
2317 KVM_DEV_ARM_VGIC_CPUID_SHIFT
;
2319 mutex_lock(&dev
->kvm
->lock
);
2321 ret
= vgic_init(dev
->kvm
);
2325 if (cpuid
>= atomic_read(&dev
->kvm
->online_vcpus
)) {
2330 vcpu
= kvm_get_vcpu(dev
->kvm
, cpuid
);
2331 vgic
= &dev
->kvm
->arch
.vgic
;
2334 mmio
.is_write
= is_write
;
2336 mmio_data_write(&mmio
, ~0, *reg
);
2337 switch (attr
->group
) {
2338 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
2339 mmio
.phys_addr
= vgic
->vgic_dist_base
+ offset
;
2340 ranges
= vgic_dist_ranges
;
2342 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
:
2343 mmio
.phys_addr
= vgic
->vgic_cpu_base
+ offset
;
2344 ranges
= vgic_cpu_ranges
;
2349 r
= vgic_find_range(ranges
, &mmio
, offset
);
2351 if (unlikely(!r
|| !r
->handle_mmio
)) {
2357 spin_lock(&vgic
->lock
);
2360 * Ensure that no other VCPU is running by checking the vcpu->cpu
2361 * field. If no other VPCUs are running we can safely access the VGIC
2362 * state, because even if another VPU is run after this point, that
2363 * VCPU will not touch the vgic state, because it will block on
2364 * getting the vgic->lock in kvm_vgic_sync_hwstate().
2366 kvm_for_each_vcpu(c
, tmp_vcpu
, dev
->kvm
) {
2367 if (unlikely(tmp_vcpu
->cpu
!= -1)) {
2369 goto out_vgic_unlock
;
2374 * Move all pending IRQs from the LRs on all VCPUs so the pending
2375 * state can be properly represented in the register state accessible
2378 kvm_for_each_vcpu(c
, tmp_vcpu
, dev
->kvm
)
2379 vgic_unqueue_irqs(tmp_vcpu
);
2382 r
->handle_mmio(vcpu
, &mmio
, offset
);
2385 *reg
= mmio_data_read(&mmio
, ~0);
2389 spin_unlock(&vgic
->lock
);
2391 mutex_unlock(&dev
->kvm
->lock
);
2395 int vgic_set_common_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2399 switch (attr
->group
) {
2400 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
2401 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
2403 unsigned long type
= (unsigned long)attr
->attr
;
2405 if (copy_from_user(&addr
, uaddr
, sizeof(addr
)))
2408 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, true);
2409 return (r
== -ENODEV
) ? -ENXIO
: r
;
2411 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
: {
2412 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2416 if (get_user(val
, uaddr
))
2421 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
2422 * - at most 1024 interrupts
2423 * - a multiple of 32 interrupts
2425 if (val
< (VGIC_NR_PRIVATE_IRQS
+ 32) ||
2426 val
> VGIC_MAX_IRQS
||
2430 mutex_lock(&dev
->kvm
->lock
);
2432 if (vgic_ready(dev
->kvm
) || dev
->kvm
->arch
.vgic
.nr_irqs
)
2435 dev
->kvm
->arch
.vgic
.nr_irqs
= val
;
2437 mutex_unlock(&dev
->kvm
->lock
);
2441 case KVM_DEV_ARM_VGIC_GRP_CTRL
: {
2442 switch (attr
->attr
) {
2443 case KVM_DEV_ARM_VGIC_CTRL_INIT
:
2444 r
= vgic_init(dev
->kvm
);
2454 static int vgic_set_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2458 ret
= vgic_set_common_attr(dev
, attr
);
2462 switch (attr
->group
) {
2463 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
2464 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
: {
2465 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2468 if (get_user(reg
, uaddr
))
2471 return vgic_attr_regs_access(dev
, attr
, ®
, true);
2479 int vgic_get_common_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2483 switch (attr
->group
) {
2484 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
2485 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
2487 unsigned long type
= (unsigned long)attr
->attr
;
2489 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, false);
2491 return (r
== -ENODEV
) ? -ENXIO
: r
;
2493 if (copy_to_user(uaddr
, &addr
, sizeof(addr
)))
2497 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
: {
2498 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2500 r
= put_user(dev
->kvm
->arch
.vgic
.nr_irqs
, uaddr
);
2509 static int vgic_get_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2513 ret
= vgic_get_common_attr(dev
, attr
);
2517 switch (attr
->group
) {
2518 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
2519 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
: {
2520 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2523 ret
= vgic_attr_regs_access(dev
, attr
, ®
, false);
2526 return put_user(reg
, uaddr
);
2534 int vgic_has_attr_regs(const struct kvm_mmio_range
*ranges
, phys_addr_t offset
)
2536 struct kvm_exit_mmio dev_attr_mmio
;
2538 dev_attr_mmio
.len
= 4;
2539 if (vgic_find_range(ranges
, &dev_attr_mmio
, offset
))
2545 static int vgic_has_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2549 switch (attr
->group
) {
2550 case KVM_DEV_ARM_VGIC_GRP_ADDR
:
2551 switch (attr
->attr
) {
2552 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
2553 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
2557 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
2558 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
2559 return vgic_has_attr_regs(vgic_dist_ranges
, offset
);
2560 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
:
2561 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
2562 return vgic_has_attr_regs(vgic_cpu_ranges
, offset
);
2563 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
:
2565 case KVM_DEV_ARM_VGIC_GRP_CTRL
:
2566 switch (attr
->attr
) {
2567 case KVM_DEV_ARM_VGIC_CTRL_INIT
:
2574 void vgic_destroy(struct kvm_device
*dev
)
2579 int vgic_create(struct kvm_device
*dev
, u32 type
)
2581 return kvm_vgic_create(dev
->kvm
, type
);
2584 struct kvm_device_ops kvm_arm_vgic_v2_ops
= {
2585 .name
= "kvm-arm-vgic",
2586 .create
= vgic_create
,
2587 .destroy
= vgic_destroy
,
2588 .set_attr
= vgic_set_attr
,
2589 .get_attr
= vgic_get_attr
,
2590 .has_attr
= vgic_has_attr
,
2593 static void vgic_init_maintenance_interrupt(void *info
)
2595 enable_percpu_irq(vgic
->maint_irq
, 0);
2598 static int vgic_cpu_notify(struct notifier_block
*self
,
2599 unsigned long action
, void *cpu
)
2603 case CPU_STARTING_FROZEN
:
2604 vgic_init_maintenance_interrupt(NULL
);
2607 case CPU_DYING_FROZEN
:
2608 disable_percpu_irq(vgic
->maint_irq
);
2615 static struct notifier_block vgic_cpu_nb
= {
2616 .notifier_call
= vgic_cpu_notify
,
2619 static const struct of_device_id vgic_ids
[] = {
2620 { .compatible
= "arm,cortex-a15-gic", .data
= vgic_v2_probe
, },
2621 { .compatible
= "arm,gic-v3", .data
= vgic_v3_probe
, },
2625 int kvm_vgic_hyp_init(void)
2627 const struct of_device_id
*matched_id
;
2628 const int (*vgic_probe
)(struct device_node
*,const struct vgic_ops
**,
2629 const struct vgic_params
**);
2630 struct device_node
*vgic_node
;
2633 vgic_node
= of_find_matching_node_and_match(NULL
,
2634 vgic_ids
, &matched_id
);
2636 kvm_err("error: no compatible GIC node found\n");
2640 vgic_probe
= matched_id
->data
;
2641 ret
= vgic_probe(vgic_node
, &vgic_ops
, &vgic
);
2645 ret
= request_percpu_irq(vgic
->maint_irq
, vgic_maintenance_handler
,
2646 "vgic", kvm_get_running_vcpus());
2648 kvm_err("Cannot register interrupt %d\n", vgic
->maint_irq
);
2652 ret
= __register_cpu_notifier(&vgic_cpu_nb
);
2654 kvm_err("Cannot register vgic CPU notifier\n");
2658 /* Callback into for arch code for setup */
2659 vgic_arch_setup(vgic
);
2661 on_each_cpu(vgic_init_maintenance_interrupt
, NULL
, 1);
2666 free_percpu_irq(vgic
->maint_irq
, kvm_get_running_vcpus());