ARC Dependent Features
**********************

Options
=======

The following options control the type of CPU for which code is assembled, and generic constraints on the code generated:

-mcpu=CPU
     Set architecture type and register usage for CPU.  There are also shortcut alias options available for backward compatibility and convenience.  Supported values for CPU are

     arc600
          Assemble for ARC 600.  Aliases: -mA6, -mARC600.

     arc601
          Assemble for ARC 601.  Alias: -mARC601.

     arc700
          Assemble for ARC 700.  Aliases: -mA7, -mARC700.

     nps400
          Assemble for NPS400.

     arcem
          Assemble for ARC EM.  Aliases: -mEM

     archs
          Assemble for ARC HS.  Aliases: -mHS, -mav2hs.

     Note: the .cpu directive (see ARC Directives) can to be used to select a core variant from within assembly code.

-EB
     This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL
     This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor - this is the default.

-mcode-density
     This option turns on Code Density instructions.  Only valid for ARC EM processors.

-mrelax
     Enable support for assembly-time relaxation.  The assembler will replace a longer version of an instruction with a shorter one, whenever it is possible.

Syntax
======

Special Characters
------------------

%
     A register name can optionally be prefixed by a % character.  So register %r0 is equivalent to r0 in the assembly code.

#
     The presence of a # character within a line (but not at the start of a line) indicates the start of a comment that extends to the end of the current line.

     Note: if a line starts with a # character then it can also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).

@
     Prefixing an operand with an @ specifies that the operand is a symbol and not a register.  This is how the assembler disambiguates the use of an ARC register name as a symbol.  So the instruction

          mov r0, @r0

     moves the address of symbol r0 into register r0.

`
     The ` (backtick) character is used to separate statements on a single line.

-
     Used as a separator to obtain a sequence of commands from a C preprocessor macro.

Register Names
--------------

The ARC assembler uses the following register names for its core registers:

r0-r31
     The core general registers.  Registers r26 through r31 have special functions, and are usually referred to by those synonyms.

gp
     The global pointer and a synonym for r26.

fp
     The frame pointer and a synonym for r27.

sp
     The stack pointer and a synonym for r28.

ilink1
     For ARC 600 and ARC 700, the level 1 interrupt link register and a synonym for r29.  Not supported for ARCv2.

ilink
     For ARCv2, the interrupt link register and a synonym for r29. Not supported for ARC 600 and ARC 700.

ilink2
     For ARC 600 and ARC 700, the level 2 interrupt link register and a synonym for r30.  Not supported for ARC v2.

blink
     The link register and a synonym for r31.

r32-r59
     The extension core registers.

lp_count
     The loop count register.

pcl
     The word aligned program counter.

In addition the ARC processor has a large number of auxiliary registers.  The precise set depends on the extensions being supported, but the following baseline set are always defined:

identity
     Processor Identification register.  Auxiliary register address 0x4.

pc
     Program Counter.  Auxiliary register address 0x6.

status32
     Status register.  Auxiliary register address 0x0a.

bta
     Branch Target Address.  Auxiliary register address 0x412.

ecr
     Exception Cause Register.  Auxiliary register address 0x403.

int_vector_base
     Interrupt Vector Base address.  Auxiliary register address 0x25.

status32_p0
     Stored STATUS32 register on entry to level P0 interrupts.  Auxiliary register address 0xb.

aux_user_sp
     Saved User Stack Pointer.  Auxiliary register address 0xd.

eret
     Exception Return Address.  Auxiliary register address 0x400.

erbta
     BTA saved on exception entry.  Auxiliary register address 0x401.

erstatus
     STATUS32 saved on exception.  Auxiliary register address 0x402.

bcr_ver
     Build Configuration Registers Version.  Auxiliary register address 0x60.

bta_link_build
     Build configuration for: BTA Registers.  Auxiliary register address 0x63.

vecbase_ac_build
     Build configuration for: Interrupts.  Auxiliary register address 0x68.

rf_build
     Build configuration for: Core Registers.  Auxiliary register address 0x6e.

dccm_build
     DCCM RAM Configuration Register.  Auxiliary register address 0xc1.

Additional auxiliary register names are defined according to the processor architecture version and extensions selected by the options.

ARC Machine Directives
======================

The ARC version of AS supports the following additional machine directives:

.lcomm SYMBOL, LENGTH[, ALIGNMENT]
     Reserve LENGTH (an absolute expression) bytes for a local common denoted by SYMBOL.  The section and value of SYMBOL are those of the new local common.  The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed.  Since SYMBOL is not declared global, it is normally not visible to LD.  The optional third parameter, ALIGNMENT, specifies the desired alignment of the symbol in the bss section, specified as a byte boundary (for example, an alignment of 16 means that the least significant 4 bits of the address should be zero).  The alignment must be an absolute expression, and it must be a power of two.  If no alignment is specified, as will set the alignment to the largest power of two less than or equal to the size of the symbol, up to a maximum of 16.

.lcommon SYMBOL, LENGTH[, ALIGNMENT]
     The same as lcomm directive.

.cpu CPU
     The .cpu directive must be followed by the desired core version.  Permitted values for CPU are:

     ARC600
          Assemble for the ARC600 instruction set.

     ARC700
          Assemble for the ARC700 instruction set.

     NPS400
          Assemble for the NPS400 instruction set.

     EM
          Assemble for the ARC EM instruction set.

     HS
          Assemble for the ARC HS instruction set.

     Note: the .cpu directive overrides the command line option -mcpu=CPU; a warning is emitted when the version is not consistent between the two.

.extAuxRegister NAME, ADDR, MODE
     Auxiliary registers can be defined in the assembler source code by using this directive.  The first parameter, NAME, is the name of the new auxiliary register.  The second parameter, ADDR, is address the of the auxiliary register.  The third parameter, MODE, specifies whether the register is readable and/or writable and is one of:

     r
          Read only;

     w
          Write only;

     r|w
          Read and write.

     For example:

          	.extAuxRegister mulhi, 0x12, w

     specifies a write only extension auxiliary register, MULHI at address 0x12.

.extCondCode SUFFIX, VAL
     ARC supports extensible condition codes.  This directive defines a new condition code, to be known by the suffix, SUFFIX and will depend on the value, VAL in the condition code.

     For example:

          	.extCondCode is_busy,0x14
          	add.is_busy  r1,r2,r3

     will only execute the add instruction if the condition code value is 0x14.

.extCoreRegister NAME, REGNUM, MODE, SHORTCUT
     Specifies an extension core register named NAME as a synonym for the register numbered REGNUM.  The register number must be between 32 and 59.  The third argument, MODE, indicates whether the register is readable and/or writable and is one of:

     r
          Read only;

     w
          Write only;

     r|w
          Read and write.

     The final parameter, SHORTCUT indicates whether the register has a short cut in the pipeline.  The valid values are:

     can_shortcut
          The register has a short cut in the pipeline;

     cannot_shortcut
          The register does not have a short cut in the pipeline.

     For example:

          	.extCoreRegister mlo, 57, r , can_shortcut

     defines a read only extension core register, mlo, which is register 57, and can short cut the pipeline.

.extInstruction NAME, OPCODE, SUBOPCODE, SUFFIXCLASS, SYNTAXCLASS
     ARC allows the user to specify extension instructions.  These extension instructions are not macros; the assembler creates encodings for use of these instructions according to the specification by the user.

     The first argument, NAME, gives the name of the instruction.

     The second argument, OPCODE, is the opcode to be used (bits 31:27 in the encoding).

     The third argument, SUBOPCODE, is the sub-opcode to be used, but the correct value also depends on the fifth argument, SYNTAXCLASS

     The fourth argument, SUFFIXCLASS, determines the kinds of suffixes to be allowed.  Valid values are:

     SUFFIX_NONE
          No suffixes are permitted;

     SUFFIX_COND
          Conditional suffixes are permitted;

     SUFFIX_FLAG
          Flag setting suffixes are permitted.

     SUFFIX_COND|SUFFIX_FLAG
          Both conditional and flag setting suffices are permitted.

     The fifth and final argument, SYNTAXCLASS, determines the syntax class for the instruction.  It can have the following values:

     SYNTAX_2OP
          Two Operand Instruction;

     SYNTAX_3OP
          Three Operand Instruction.

     SYNTAX_1OP
          One Operand Instruction.

     SYNTAX_NOP
          No Operand Instruction.

     The syntax class may be followed by | and one of the following modifiers.

     OP1_MUST_BE_IMM
          Modifies syntax class SYNTAX_3OP, specifying that the first operand of a three-operand instruction must be an immediate (i.e., the result is discarded).  This is usually used to set the flags using specific instructions and not retain results.

     OP1_IMM_IMPLIED
          Modifies syntax class SYNTAX_20P, specifying that there is an implied immediate destination operand which does not appear in the syntax.

          For example, if the source code contains an instruction like:

               inst r1,r2

          the first argument is an implied immediate (that is, the result is discarded).  This is the same as though the source code were: inst 0,r1,r2.

     For example, defining a 64-bit multiplier with immediate operands:

          	.extInstruction  mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
          			 SYNTAX_3OP|OP1_MUST_BE_IMM

     which specifies an extension instruction named mp64 with 3 operands.  It sets the flags and can be used with a condition code, for which the first operand is an immediate, i.e. equivalent to discarding the result of the operation.

     A two operands instruction variant would be:

          	.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
          	SYNTAX_2OP|OP1_IMM_IMPLIED

     which describes a two operand instruction with an implicit first immediate operand.  The result of this operation would be discarded.

ARC Assembler Modifiers
=======================

The following additional assembler modifiers have been added for position-independent code.  These modifiers are available only with the ARC 700 and above processors and generate relocation entries, which are interpreted by the linker as follows:

@pcl(SYMBOL)
     Relative distance of SYMBOL's from the current program counter location.

@gotpc(SYMBOL)
     Relative distance of SYMBOL's Global Offset Table entry from the current program counter location.

@gotoff(SYMBOL)
     Distance of SYMBOL from the base of the Global Offset Table.

@plt(SYMBOL)
     Distance of SYMBOL's Procedure Linkage Table entry from the current program counter.  This is valid only with branch and link instructions and PC-relative calls.

@sda(SYMBOL)
     Relative distance of SYMBOL from the base of the Small Data Pointer.

ARC Pre-defined Symbols
=======================

The following assembler symbols will prove useful when developing position-independent code.  These symbols are available only with the ARC 700 and above processors.

__GLOBAL_OFFSET_TABLE__
     Symbol referring to the base of the Global Offset Table.

__DYNAMIC__
     An alias for the Global Offset Table Base__GLOBAL_OFFSET_TABLE__.  It can be used only with @gotpc modifiers.

Opcodes
=======

For information on the ARC instruction set, see ARC Programmers Reference Manual, available where you download the processor IP library.