D10V Dependent Features
***********************

D10V Options
============

The Mitsubishi D10V version of AS has a few machine dependent options.

-O
     The D10V can often execute two sub-instructions in parallel. When this option is used, AS will attempt to optimize its output by detecting when instructions can be executed in parallel.

Syntax
======

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.

Register Names
--------------

You can use the predefined symbols r0 through r15 to refer to the D10V registers.  You can also use sp as an alias for r15.  The accumulators are a0 and a1.  Register names are not case sensitive.

The D10V also has predefined symbols for these control registers and status bits:

psw
     Processor Status Word

bpsw
     Backup Processor Status Word

pc
     Program Counter

bpc
     Backup Program Counter

rpt_c
     Repeat Count

rpt_s
     Repeat Start address

rpt_e
     Repeat End address

mod_s
     Modulo Start address

mod_e
     Modulo End address

iba
     Instruction Break Address

f0
     Flag 0

f1
     Flag 1

c
     Carry flag

Size Modifiers
--------------

The D10V version of AS uses the instruction names in the D10V Architecture Manual.  However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form?  AS will always pick the smallest form if it can.  When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form.  If you need to force the assembler to use either the short or long form of the instruction, you can append either .s (short) or .l (long) to it.  For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write bra.s   foo. Objdump and GDB will always append .s or .l to instructions which have both short and long forms.

Sub-Instructions
----------------

The D10V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section.  Some of these instructions will be short-form or sub-instructions.  These sub-instructions can be packed into a single instruction.  The assembler will do this automatically.  It will also detect when it should not pack instructions.  For example, when a label is defined, the next instruction will never be packaged with the previous one.  Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid.  Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

Special Characters
------------------

; and # are the line comment characters. Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially. To specify the executing order, use the following symbols:

->
     Sequential with instruction on the left first.

<-
     Sequential with instruction on the right first.

||
     Parallel

The D10V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line.  For example

abs       a1      ->      abs     r0
     Execute these sequentially.  The instruction on the right is in the right container and is executed second.

abs       r0      <-      abs     a1
     Execute these reverse-sequentially.  The instruction on the right is in the right container, and is executed first.

ld2w    r2,@r8+         ||      mac     a0,r0,r7
     Execute these in parallel.

ld2w    r2,@r8+         ||
mac     a0,r0,r7
     Two-line format. Execute these in parallel.

ld2w    r2,@r8+
mac     a0,r0,r7
     Two-line format. Execute these sequentially.  Assembler will put them in the proper containers.

ld2w    r2,@r8+         ->
mac     a0,r0,r7
     Two-line format. Execute these sequentially.  Same as above but second instruction will always go into right container.

Since $ has no special meaning, you may use it in symbol names.

Addressing Modes
----------------

AS understands the following addressing modes for the D10V. RN in the following refers to any of the numbered registers, but not the control registers.

RN
     Register direct

@RN
     Register indirect

@RN+
     Register indirect with post-increment

@RN-
     Register indirect with post-decrement

@-SP
     Register indirect with pre-decrement

@(DISP, RN)
     Register indirect with displacement

ADDR
     PC relative address (for branch or rep).

#IMM
     Immediate data

Floating Point
==============

The D10V has no hardware floating point, but the .float and .double directives generates IEEE floating-point numbers for compatibility with other development tools.

Opcodes
=======

For detailed information on the D10V machine instruction set, see D10V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). AS implements all the standard D10V opcodes.  The only changes are those described in the section on size modifiers