Intel i860 Dependent Features
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i860 Notes
==========

This is a fairly complete i860 assembler which is compatible with the UNIX System V/860 Release 4 assembler. However, it does not currently support SVR4 PIC (i.e., @GOT, @GOTOFF, @PLT).

Like the SVR4/860 assembler, the output object format is ELF32. Currently, this is the only supported object format. If there is sufficient interest, other formats such as COFF may be implemented.

Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter being the default.  One difference is that AT&T syntax requires the '%' prefix on register names while Intel syntax does not.  Another difference is in the specification of relocatable expressions.  The Intel syntax is ha%expression whereas the SVR4 syntax is [expression]@ha (and similarly for the "l" and "h" selectors).

i860 Command-line Options
=========================

SVR4 compatibility options
--------------------------

-V
     Print assembler version.

-Qy
     Ignored.

-Qn
     Ignored.

Other options
-------------

-EL
     Select little endian output (this is the default).

-EB
     Select big endian output. Note that the i860 always reads instructions as little endian data, so this option only effects data and not instructions.

-mwarn-expand
     Emit a warning message if any pseudo-instruction expansions occurred. For example, a or instruction with an immediate larger than 16-bits will be expanded into two instructions. This is a very undesirable feature to rely on, so this flag can help detect any code where it happens. One use of it, for instance, has been to find and eliminate any place where gcc may emit these pseudo-instructions.

-mxp
     Enable support for the i860XP instructions and control registers.  By default, this option is disabled so that only the base instruction set (i.e., i860XR) is supported.

-mintel-syntax
     The i860 assembler defaults to AT&T/SVR4 syntax.  This option enables the Intel syntax.

i860 Machine Directives
=======================

.dual
     Enter dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code the dual bit with the d. prefix.

.enddual
     Exit dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code the dual bit with the d. prefix.

.atmp
     Change the temporary register used when expanding pseudo operations. The default register is r31.

i860 Opcodes
============

All of the Intel i860XR and i860XP machine instructions are supported. Please see either i860 Microprocessor Programmer's Reference Manual or i860 Microprocessor Architecture for more information.

Other instruction support (pseudo-instructions)
-----------------------------------------------

For compatibility with some other i860 assemblers, a number of pseudo-instructions are supported. While these are supported, they are a very undesirable feature that should be avoided -- in particular, when they result in an expansion to multiple actual i860 instructions. Below are the pseudo-instructions that result in expansions.

  * Load large immediate into general register:

     The pseudo-instruction mov imm,%rn (where the immediate does not fit within a signed 16-bit field) will be expanded into:

          orh large_imm@h,%r0,%rn
          or large_imm@l,%rn,%rn

  * Load/store with relocatable address expression:

     For example, the pseudo-instruction ld.b addr,%rn will be expanded into:

          orh addr_exp@ha,%r0,%r31
          ld.l addr_exp@l(%r31),%rn

     The analogous expansions apply to ld.x, st.x, fld.x, pfld.x, fst.x, and pst.x as well.

  * Signed large immediate with add/subtract:

     If any of the arithmetic operations adds, addu, subs, subu are used with an immediate larger than 16-bits (signed), then they will be expanded. For instance, the pseudo-instruction adds large_imm,%rx,%rn expands to:

          orh large_imm@h,%r0,%r31
          or large_imm@l,%r31,%r31
          adds %r31,%rx,%rn

  * Unsigned large immediate with logical operations:

     Logical operations (or, andnot, or, xor) also result in expansions. The pseudo-instruction or large_imm,%rx,%rn results in:

          orh large_imm@h,%rx,%r31
          or large_imm@l,%r31,%rn

     Similarly for the others, except for and which expands to:

          andnot (-1 - large_imm)@h,%rx,%r31
          andnot (-1 - large_imm)@l,%r31,%rn