RISC-V Dependent Features
*************************

RISC-V Options
==============

The following table lists all available RISC-V specific options.

-fpic
-fPIC
     Generate position-independent code

-fno-pic
     Don't generate position-independent code (default)

-march=ISA
     Select the base isa, as specified by ISA.  For example -march=rv32ima.

-mabi=ABI
     Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none to indicate the soft-float calling convention.

RISC-V Directives
=================

The following table lists all available RISC-V specific directives.

.align SIZE-LOG-2
     Align to the given boundary, with the size given as log2 the number of bytes to align to.

.half VALUE
.word VALUE
.dword VALUE
     Emits a half-word, word, or double-word value at the current position.

.dtprelword VALUE
.dtpreldword VALUE
     Emits a DTP-relative word (or double-word) at the current position.  This is meant to be used by the compiler in shared libraries for DWARF debug info for thread local variables.

.bss
     Sets the current section to the BSS section.

.uleb128 VALUE
.sleb128 VALUE
     Emits a signed or unsigned LEB128 value at the current position.  This only accepts constant expressions, because symbol addresses can change with relaxation, and we don't support relocations to modify LEB128 values at link time.

.option ARGUMENT
     Modifies RISC-V specific assembler options inline with the assembly code. This is used when particular instruction sequences must be assembled with a specific set of options.  For example, since we relax addressing sequences to shorter GP-relative sequences when possible the initial load of GP must not be relaxed and should be emitted as something like

          	.option push
          	.option norelax
          	la gp, __global_pointer$
          	.option pop

     in order to produce after linker relaxation the expected

          	auipc gp, %pcrel_hi(__global_pointer$)
          	addi gp, gp, %pcrel_lo(__global_pointer$)

     instead of just

          	addi gp, gp, 0

     It's not expected that options are changed in this manner during regular use, but there are a handful of esoteric cases like the one above where users need to disable particular features of the assembler for particular code sequences. The complete list of option arguments is shown below:

     push
     pop
          Pushes or pops the current option stack.  These should be used whenever changing an option in line with assembly code in order to ensure the user's command-line options are respected for the bulk of the file being assembled.

     rvc
     norvc
          Enables or disables the generation of compressed instructions.  Instructions are opportunistically compressed by the RISC-V assembler when possible, but sometimes this behavior is not desirable.

     pic
     nopic
          Enables or disables position-independent code generation.  Unless you really know what you're doing, this should only be at the top of a file.

     relax
     norelax
          Enables or disables relaxation.  The RISC-V assembler and linker opportunistically relax some code sequences, but sometimes this behavior is not desirable.

.insn VALUE
.insn VALUE
     This directive permits the numeric representation of an instructions and makes the assembler insert the operands according to one of the instruction formats for .insn (RISC-V-Formats). For example, the instruction add a0, a1, a2 could be written as .insn r 0x33, 0, 0, a0, a1, a2.

Instruction Formats
===================

The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12 instruction formats where some of the formats have multiple variants. For the .insn pseudo directive the assembler recognizes some of the formats. Typically, the most general variant of the instruction format is used by the .insn directive.

The following table lists the abbreviations used in the table of instruction formats:

     opcode   Unsigned immediate or opcode name for 7-bits opcode.
     opcode2   Unsigned immediate or opcode name for 2-bits opcode.
     func7   Unsigned immediate for 7-bits function code.
     func4   Unsigned immediate for 4-bits function code.
     func3   Unsigned immediate for 3-bits function code.
     func2   Unsigned immediate for 2-bits function code.
     rd   Destination register number for operand x, can be GPR or FPR.
     rd'   Destination register number for operand x,
     only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
     rs1   First source register number for operand x, can be GPR or FPR.
     rs1'   First source register number for operand x,
     only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
     rs2   Second source register number for operand x, can be GPR or FPR.
     rs2'   Second source register number for operand x,
     only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
     simm12   Sign-extended 12-bit immediate for operand x.
     simm20   Sign-extended 20-bit immediate for operand x.
     simm6   Sign-extended 6-bit immediate for operand x.
     uimm8   Unsigned 8-bit immediate for operand x.
     symbol   Symbol or lable reference for operand x.

The following table lists all available opcode name:

C0

C1

C2
     Opcode space for compressed instructions.

LOAD
     Opcode space for load instructions.

LOAD_FP
     Opcode space for floating-point load instructions.

STORE
     Opcode space for store instructions.

STORE_FP
     Opcode space for floating-point store instructions.

AUIPC
     Opcode space for auipc instruction.

LUI
     Opcode space for lui instruction.

BRANCH
     Opcode space for branch instructions.

JAL
     Opcode space for jal instruction.

JALR
     Opcode space for jalr instruction.

OP
     Opcode space for ALU instructions.

OP_32
     Opcode space for 32-bits ALU instructions.

OP_IMM
     Opcode space for ALU with immediate instructions.

OP_IMM_32
     Opcode space for 32-bits ALU with immediate instructions.

OP_FP
     Opcode space for floating-point operation instructions.

MADD
     Opcode space for madd instruction.

MSUB
     Opcode space for msub instruction.

NMADD
     Opcode space for nmadd instruction.

NMSUB
     Opcode space for msub instruction.

AMO
     Opcode space for atomic memory operation instructions.

MISC_IMM
     Opcode space for misc instructions.

SYSTEM
     Opcode space for system instructions.

CUSTOM_0

CUSTOM_1

CUSTOM_2

CUSTOM_3
     Opcode space for customize instructions.

An instruction is two or four bytes in length and must be aligned on a 2 byte boundary. The first two bits of the instruction specify the length of the instruction, 00, 01 and 10 indicates a two byte instruction, 11 indicates a four byte instruction.

The following table lists the RISC-V instruction formats that are available with the .insn pseudo directive:

R type: .insn r opcode, func3, func7, rd, rs1, rs2
     +-------+-----+-----+-------+----+-------------+
     | func7 | rs2 | rs1 | func3 | rd |      opcode |
     +-------+-----+-----+-------+----+-------------+
     31      25    20    15      12   7             0

R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
     +-----+-------+-----+-----+-------+----+-------------+
     | rs3 | func2 | rs2 | rs1 | func3 | rd |      opcode |
     +-----+-------+-----+-----+-------+----+-------------+
     31    27      25    20    15      12   7             0

I type: .insn i opcode, func3, rd, rs1, simm12
     +-------------+-----+-------+----+-------------+
     |      simm12 | rs1 | func3 | rd |      opcode |
     +-------------+-----+-------+----+-------------+
     31            20    15      12   7             0

S type: .insn s opcode, func3, rd, rs1, simm12
     +--------------+-----+-----+-------+-------------+-------------+
     | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] |      opcode |
     +--------------+-----+-----+-------+-------------+-------------+
     31             25    20    15      12            7             0

SB type: .insn sb opcode, func3, rd, rs1, symbol
SB type: .insn sb opcode, func3, rd, simm12(rs1)
     +--------------+-----+-----+-------+-------------+-------------+
     | simm21[11:5] | rs2 | rs1 | func3 | simm12[4:0] |      opcode |
     +--------------+-----+-----+-------+-------------+-------------+
     31             25    20    15      12            7             0

U type: .insn u opcode, rd, simm20
     +---------------------------+----+-------------+
     |                    simm20 | rd |      opcode |
     +---------------------------+----+-------------+
     31                          12   7             0

UJ type: .insn uj opcode, rd, symbol
     +------------+--------------+------------+---------------+----+-------------+
     | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd |      opcode |
     +------------+--------------+------------+---------------+----+-------------+
     31           30             21           20              12   7             0

CR type: .insn cr opcode2, func4, rd, rs1
     +---------+--------+-----+---------+
     |   func4 | rd/rs1 | rs2 | opcode2 |
     +---------+--------+-----+---------+
     15        12       7     2        0

CI type: .insn ci opcode2, func3, rd, simm6
     +---------+-----+--------+-----+---------+
     |   func3 | imm | rd/rs1 | imm | opcode2 |
     +---------+-----+--------+-----+---------+
     15        13    12       7     2         0

CIW type: .insn ciw opcode2, func3, rd, uimm8
     +---------+--------------+-----+---------+
     |   func3 |          imm | rd' | opcode2 |
     +---------+--------------+-----+---------+
     15        13             7     2         0

CB type: .insn cb opcode2, func3, rs1, symbol
     +---------+--------+------+--------+---------+
     |   func3 | offset | rs1' | offset | opcode2 |
     +---------+--------+------+--------+---------+
     15        13       10     7        2         0

CJ type: .insn cj opcode2, symbol
     +---------+--------------------+---------+
     |   func3 |        jump target | opcode2 |
     +---------+--------------------+---------+
     15        13             7     2         0

For the complete list of all instruction format variants see The RISC-V Instruction Set Manual Volume I: User-Level ISA.