// -*- C -*-
//
//
// MIPS Architecture:
//
//        CPU Instruction Set (mips16)
//

// The instructions in this section are ordered according
// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.


// The MIPS16 codes registers in a special way, map from one to the other.
// :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)


// FIXME:
//
// Only the `LB' instruction is implemented.  It should be used as a guideline
// when implementing other instructions.
//
// How to handle delayslots (for jumps) and extended lwpc instructions
// has not been resolved.


011101,26.INSTR_INDEX:NORMAL:32::JALX
*r3900:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
/// {
/// }


// Load and Store Instructions


10000,3.RX,3.RY,5.IMMED:RRI:16::LB
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
}


10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
}


10001,3.RX,3.RY,5.IMMED:RRI:16::LH
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
}


10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
}


10011,3.RX,3.RY,5.IMMED:RRI:16::LW
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
}


10110,3.RX,8.IMMED:RI:16::LWPC
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
				basepc (SD_) & ~3, IMMED << 2));
}


10010,3.RX,8.IMMED:RI:16::LWSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
}


10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
}


00111,3.RX,3.RY,5.IMMED:RRI:16,64::LD
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
}


11111,100,3.RY,5.IMMED:RI64:16::LDPC
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
		      basepc (SD_) & ~7, IMMED << 3);
}


11111,000,3.RY,5.IMMED:RI64:16::LDSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
}


11000,3.RX,3.RY,5.IMMED:RRI:16::SB
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
}


11001,3.RX,3.RY,5.IMMED:RRI:16::SH
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
}


11011,3.RX,3.RY,5.IMMED:RRI:16::SW
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
}


11010,3.RX,8.IMMED:RI:16::SWSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
}


01100,010,8.IMMED:I8:16::SWRASP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
}


01111,3.RX,3.RY,5.IMMED:RRI:16::SD
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
}


11111,001,3.RY,5.IMMED:RI64:16::SDSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
}


11111,010,8.IMMED:I64:16::SDRASP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
}


// ALU Immediate Instructions


01101,3.RX,8.IMMED::RI:16::LI
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_ori (SD_, 0, TRX, IMMED);
}


01000,3.RX,3.RY,0,4.IMMED:RRI_A:16::ADDIU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}


01001,3.RX,8.IMMED:RI:16::ADDIU8
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
}


01100,011,8.IMMED:I8:16::ADJSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}


00001,3.RX,8.IMMED:RI:16::ADDIUPC
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  unsigned32 temp = (basepc (SD_) & ~3) + (EXTEND8 (IMMED) << 2);
  GPR[TRX] = EXTEND32 (temp);
}


00000,3.RX,8.IMMED:RI:16::ADDIUSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addiu (SD_, SPIDX, TRX, EXTEND8 (IMMED) << 2);
}


01000,3.RX,3.RY,1,4.IMMED:RRI_A:16,64::DADDIU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
}


11111,101,3.RY,5.IMMED:RI64:16,64::DADDIU5
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
}


11111,011,8.IMMED:I64:16,64::DADJSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
}


11111,110,3.RY,5.IMMED:RI64:16,64::DADDIUPC
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  GPR[TRY] = (basepc (SD_) & ~3) + (EXTEND5 (IMMED) << 2);
}


11111,111,3.RY,5.IMMED:RI64:16,64::DADDIUSP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddiu (SD_, SPIDX, TRY, EXTEND5 (IMMED) << 2);
}


01010,3.RX,8.IMMED:RI:16::SLTI
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_slti (SD_, TRX, T8IDX, IMMED);
}


01011,3.RX,8.IMMED:RI:16::SLTIU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sltiu (SD_, TRX, T8IDX, IMMED);
}


11101,3.RX,3.RY,01010:RR:16::CMP
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_xor (SD_, TRX, TRY, T8IDX);
}


01110,3.RX,8.IMMED:RI:16::CMPI
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_xori (SD_, TRX, T8IDX, IMMED);
}


// Two/Three Operand, Register-Type


11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_addu (SD_, TRX, TRY, TRZ);
}


11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_subu (SD_, TRX, TRY, TRZ);
}


11100,3.RX,3.RY,3.RZ,00:RRR:16,64::DADDU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_daddu (SD_, TRX, TRY, TRZ);
}


11100,3.RX,3.RY,3.RZ,10:RRR:16,64::DSUBU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsubu (SD_, TRX, TRY, TRZ);
}


11101,3.RX,3.RY,00010:RR:16::SLT
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_slt (SD_, TRX, TRY, T8IDX);
}


11101,3.RX,3.RY,00011:RR:16::SLTU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sltu (SD_, TRX, TRY, T8IDX);
}


11101,3.RX,3.RY,01011:RR:16::NEG
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_subu (SD_, 0, TRY, TRX);
}


11101,3.RX,3.RY,01100:RR:16::AND
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_and (SD_, TRX, TRY, TRX);
}


11101,3.RX,3.RY,01101:RR:16::OR
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_or (SD_, TRX, TRY, TRX);
}


11101,3.RX,3.RY,01110:RR:16::XOR
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_xor (SD_, TRX, TRY, TRX);
}


11101,3.RX,3.RY,01111:RR:16::NOT
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_nor (SD_, 0, TRY, TRX);
}


01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_or (SD_, R32, 0, TRY);
}


01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_or (SD_, TRZ, 0, (R32H << 3) | R32L);
}


00110,3.RX,3.RY,3.SHAMT,00:ISHIFT:16::SLL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sll (SD_, TRY, TRX, SHIFT);
}


00110,3.RX,3.RY,3.SHAMT,10:ISHIFT:16::SRL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_srl (SD_, TRY, TRX, SHIFT);
}


00110,3.RX,3.RY,3.SHAMT,11:ISHIFT:16::SRA
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sra (SD_, TRY, TRX, SHIFT);
}


11101,3.RX,3.RY,00100:RR:16::SLLV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_sllv (SD_, TRX, TRY, TRY);
}


11101,3.RX,3.RY,00110:RR:16::SRLV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_srlv (SD_, TRX, TRY, TRY);
}


11101,3.RX,3.RY,00111:RR:16::SRAV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_srav (SD_, TRX, TRY, TRY);
}


00110,3.RX,3.RY,3.SHAMT,01:ISHIFT:16,64::DSLL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsll (SD_, 0, TRY, TRX, SHIFT);
}
  
  
11101,3.SHAMT,3.RY,01000:RR:16,64::DSRL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsrl (SD_, 0, TRY, TRY, SHIFT);
}


11101,3.SHAMT,3.RY,10011:RR:16,64::DSRA
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsra (SD_, 0, TRY, TRY, SHIFT);
}


11101,3.RX,3.RY,10100:RR:16,64::DSLLV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsllv (SD_, TRX, TRY, TRY);
}


11101,3.RX,3.RY,10110:RR:16,64::DSRLV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsrlv (SD_, TRX, TRY, TRY);
}


11101,3.RX,3.RY,10111:RR:16,64::DSRAV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dsrav (SD_, TRX, TRY, TRY);
}


// Multiply /Divide Instructions


11101,3.RX,3.RY,11000:RR:16::MULT
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_mult (SD_, TRX, TRY, 0);
}


11101,3.RX,3.RY,11001:RR:16::MULTU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_multu (SD_, TRX, TRY, 0);
}


11101,3.RX,3.RY,11010:RR:16::DIV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_div (SD_, TRX, TRY);
}


11101,3.RX,3.RY,11011:RR:16::DIVU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_divu (SD_, TRX, TRY);
}


11101,3.RX,000,10000:RR:16::MFHI
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_mfhi (SD_, TRX);
}


11101,3.RX,000,10010:RR:16::MFLO
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_mflo (SD_, TRX);
}


11101,3.RX,3.RY,11100:RR:16,64::DMULT
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dmult (SD_, TRX, TRY);
}


11101,3.RX,3.RY,11101:RR:16,64::DMULTU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_dmultu (SD_, TRX, TRY);
}


11101,3.RX,3.RY,11110:RR:16,64::DDIV
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_ddiv (SD_, TRX, TRY);
}


11101,3.RX,3.RY,11111:RR:16,64::DDIVU
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  do_ddivu (SD_, TRX, TRY);
}


// Jump and Branch Instructions



// Issue instruction in delay slot of branch
:function:::address_word:delayslot16:address_word target
{
  instruction_word delay_insn;
  sim_events_slip (SD, 1);
  DSPC = CIA; /* save current PC somewhere */
  CIA = CIA + 2; /* NOTE: mips16 */
  STATE |= simDELAYSLOT;
  delay_insn = IMEM16 (CIA); /* NOTE: mips16 */
  idecode_issue (CPU_, delay_insn, (CIA));
  STATE &= ~simDELAYSLOT;
  return target;
}
  
// compute basepc dependant on us being in a delay slot
:function:::address_word:basepc:
{
  if (STATE & simDELAYSLOT)
    {
      return DSPC; /* return saved address of preceeding jmp */
    }
  else
    {
      return CIA;
    }
}


// JAL
00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JAL
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = delayslot16 (SD_,
		     (LSMASKED (NIA, 31, 26)
		      | LSINSERTED (IMM_25_21, 25, 21)
		      | LSINSERTED (IMM_20_16, 20, 16)
		      | LSINSERTED (IMMED_15_0, 15, 0)));
}


// JALX
00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JALX
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = delayslot16 (SD_,
		     (LSMASKED (NIA, 31, 26)
		      | LSINSERTED (IMM_25_21, 25, 21)
		      | LSINSERTED (IMM_20_16, 20, 16)
		      | LSINSERTED (IMMED_15_0, 15, 0)));
  NIA = NIA ^ 1;
}


11101,3.RX,000,00000:RR:16::JR
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = delayslot16 (SD_, GPR[TRX]);
}


11101,000,001,00000:RR:16::JRRA
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = delayslot16 (SD_, RA);
}


11101,3.RX,010,00000:RR:16::JALR
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  RA = NIA + 2;
  NIA = delayslot16 (SD_, GPR[TRX]);
}


00100,3.RX,8.IMMED:RI:16::BEQZ
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  if (GPR[RX] == 0)
    NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


00101,3.RX,8.IMMED:RI:16::BNEZ
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  if (GPR[RX] != 0)
    NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


01100,000,8.IMMED:I8:16::BTEQZ
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  if (T8 == 0)
    NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


01100,001,8.IMMED:I8:16::BTNEZ
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  if (T8 != 0)
    NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


00010,11.IMMED:I:16::B
*mips16:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
  NIA = (NIA + (EXTEND8 (IMMED) << 2));
}


// Special Instructions


// See the front of the mips16 doc
//     -> FIXME need this for most instructions
// 11110,eeeeeeeeeee:I:16::EXTEND
// *mips16:
// // start-sanitize-tx19
// *tx19:
// // end-sanitize-tx19


// 11101,3.RX,3.RY,00101:RR:16::BREAK
// *mips16:
// // start-sanitize-tx19
// *tx19:
// // end-sanitize-tx19