// -*- C -*-
//
// NEC specific instructions
//

// Integer Instructions
// --------------------
//
// MulAcc is the Multiply Accumulator.
//     This register is mapped on the the HI and LO registers.
//     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
//     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.


:function:::unsigned64:MulAcc:
*vr4100:
// start-sanitize-vr4xxx
*vr4121:
// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
{
  unsigned64 result = U8_4 (HI, LO);
  return result;
}

:function:::void:SET_MulAcc:unsigned64 value
*vr4100:
// start-sanitize-vr4xxx
*vr4121:
// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
{
  /* 64 bit specific */
  *AL4_8 (&HI) = VH4_8 (value);
  *AL4_8 (&LO) = VL4_8 (value);
}

:function:::signed64:SignedMultiply:signed32 l, signed32 r
*vr4100:
// start-sanitize-vr4xxx
*vr4121:
// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
{
  signed64 result = (signed64) l * (signed64) r;
  return result;
}

:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
*vr4100:
// start-sanitize-vr4xxx
*vr4121:
// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
{
  unsigned64 result = (unsigned64) l * (unsigned64) r;
  return result;
}

// start-sanitize-vr4xxx
:function:::signed64:SaturatedAdd:signed32 l, signed32 r
*vr4121:
{
  signed64 result = (signed64) l + (signed64) r;
  if (result < 0)
    result = 0xFFFFFFFF8000000LL;
  else if (result > 0x000000007FFFFFFFLL)
    result = 0x000000007FFFFFFFLL;
  return result;
}

:function:::unsigned64:SaturatedUnsignedAdd:unsigned32 l, unsigned32 r
*vr4121:
{
  unsigned64 result = (unsigned64) l + (unsigned64) r;
  if (result > 0x000000007FFFFFFFLL)
    result = 0xFFFFFFFFFFFFFFFFLL;
  return result;
}


// end-sanitize-vr4xxx
:function:::unsigned64:Low32Bits:unsigned64 value
*vr4100:
// start-sanitize-vr4xxx
*vr4121:
// end-sanitize-vr4xxx
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
{
  unsigned64 result = (signed64) (signed32) VL4_8 (value);
  return result;
}

:function:::unsigned64:High32Bits:unsigned64 value
*vr4100:
// start-sanitize-vr4xxx
*vr4121:
// end-sanitize-vr4xxx
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
{
  unsigned64 result = (signed64) (signed32) VH4_8 (value);
  return result;
}



// Multiply, Accumulate
000000,5.RS,5.RT,00000,00000,101000::64::MAC
"mac r<RS>, r<RT>"
*vr4100:
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
{
  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
}


// D-Multiply, Accumulate
000000,5.RS,5.RT,00000,00000,101001::64::DMAC
"dmac r<RS>, r<RT>"
*vr4100:
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
{
  LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
}


// start-sanitize-vr4320
// Count Leading Zeros
000000,5.RS,00000,5.RD,00000,110101::64::CLZ
"clz r<RD>, r<RS>"
// end-sanitize-vr4320
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-vr4320
{
  unsigned32 t = Low32Bits (SD_, GPR[RS]);
  signed64 c = 0;

  while (! (t & ( 1 << 31))
	&& c < 32)
    {
    c++;
    t <<= 1;
    }

  GPR[RD] = c;
}


// end-sanitize-vr4320
// start-sanitize-vr4320
// D-Count Leading Zeros
000000,5.RS,00000,5.RD,00000,111101::64::DCLZ
"dclz r<RD>, r<RS>"
// end-sanitize-vr4320
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-vr4320
{
  unsigned64 t = GPR[RS];
  signed64 c = 0;

  while (! (t & ( (unsigned64)1 << 63))
	&& c < 64)
    {
    c++;
    t <<= 1;
    }

  printf("lo %d\n", (int) c);
  GPR[RD] = c;
}







// end-sanitize-vr4320
// start-sanitize-cygnus
// Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00100,101000::64::MUL
"mul r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Unsigned Multiply and Move LO.
000000,5.RS,5.RT,5.RD,00101,101000::64::MULU
"mulu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01100,101000::64::MULHI
"mulhi r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Unsigned Multiply and Move HI.
000000,5.RS,5.RT,5.RD,01101,101000::64::MULHIU
"mulhiu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Multiply, Negate and Move LO.
000000,5.RS,5.RT,5.RD,00011,011000::64::MULS
"muls r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Unsigned Multiply, Negate and Move LO.
000000,5.RS,5.RT,5.RD,00011,011001::64::MULSU
"mulsu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Multiply, Negate and Move HI.
000000,5.RS,5.RT,5.RD,01011,011000::64::MULSHI
"mulshi r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Unsigned Multiply, Negate and Move HI.
000000,5.RS,5.RT,5.RD,01011,011001::64::MULSHIU
"mulshiu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
//
// Multiply, Accumulate and Move LO.
//
000000,5.RS,5.RT,5.RD,00010,101000::64::MACC
"macc r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}
// end-sanitize-cygnus

// start-sanitize-vr4xxx
000000,5.RS,5.RT,5.RD,00000,101000::::MACC
"macc r<RD>, r<RS>, r<RT>"
*vr4121:
{
  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

000000,5.RS,5.RT,5.RD,00000,101001::::DMACC
"dmacc r<RD>, r<RS>, r<RT>"
*vr4121:
{
  LO =  LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
  GPR[RD] = LO;
}

000000,5.RS,5.RT,5.RD,10000,101000::::MACCS
"maccs r<RD>, r<RS>, r<RT>"
*vr4121:
{
  SET_MulAcc (SD_, SaturatedAdd (SD_, MulAcc (SD_), 
				 SignedMultiply (SD_, GPR[RS], GPR[RT])));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

000000,5.RS,5.RT,5.RD,10000,101001::::DMACCS
"dmaccs r<RD>, r<RS>, r<RT>"
*vr4121:
{
  LO = SaturatedAdd (SD_, LO, SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = LO;
}





// end-sanitize-vr4xxx
// start-sanitize-cygnus
//
// Unsigned Multiply, Accumulate and Move LO.
//
000000,5.RS,5.RT,5.RD,00011,101000::64::MACCU
"maccu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

// end-sanitize-cygnus
// start-sanitize-vr4xxx
000000,5.RS,5.RT,5.RD,00001,101000::64::MACCU
"maccu r<RD>, r<RS>, r<RT>"
*vr4121:
{
  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

000000,5.RS,5.RT,5.RD,00001,101001::64::DMACCU
"dmaccu r<RD>, r<RS>, r<RT>"
*vr4121:
{
  LO = LO + UnsignedMultiply (SD_, GPR[RS], GPR[RT]);
  GPR[RD] = LO;
}

000000,5.RS,5.RT,5.RD,10001,101000::64::MACCUS
"maccus r<RD>, r<RS>, r<RT>"
*vr4121:
{
  SET_MulAcc (SD_, 
	      SaturatedUnsignedAdd (SD_, MulAcc (SD_),
				    UnsignedMultiply (SD_, GPR[RS], GPR[RT])));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}

000000,5.RS,5.RT,5.RD,10001,101001::64::DMACCUS
"dmaccus r<RD>, r<RS>, r<RT>"
*vr4121:
{
  LO = SaturatedUnsignedAdd (SD_, LO, 
			     UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = LO;
}



// end-sanitize-vr4xxx
// start-sanitize-cygnus
//
// Multiply, Accumulate and Move HI.
//
000000,5.RS,5.RT,5.RD,01010,101000::64::MACCHI
"macchi r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}

// end-sanitize-cygnus
// start-sanitize-vr4xxx
000000,5.RS,5.RT,5.RD,01000,101000::64::MACCHI
"macchi r<RD>, r<RS>, r<RT>"
*vr4121:
{
  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}

000000,5.RS,5.RT,5.RD,11000,101000::64::MACCHIS
"macchis r<RD>, r<RS>, r<RT>"
*vr4121:
{
  SET_MulAcc (SD_, SaturatedAdd (SD_, MulAcc (SD_),
				 SignedMultiply (SD_, GPR[RS], GPR[RT])));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}



// end-sanitize-vr4xxx
// start-sanitize-cygnus
//
// Unsigned Multiply, Accumulate and Move HI.
//
000000,5.RS,5.RT,5.RD,01011,101000::64::MACCHIU
"macchiu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-vr4320
*vr4320:
// end-sanitize-vr4320
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));

}

// end-sanitize-cygnus
// start-sanitize-vr4xxx
000000,5.RS,5.RT,5.RD,01001,101000::64::MACCHIU
"macchiu r<RD>, r<RS>, r<RT>"
*vr4121:
{
  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));

}

000000,5.RS,5.RT,5.RD,11001,101000::64::MACCHIUS
"macchius r<RD>, r<RS>, r<RT>"
*vr4121:
{
  SET_MulAcc (SD_, 
	      SaturatedUnsignedAdd (SD_, MulAcc (SD_),
				    UnsignedMultiply (SD_, GPR[RS], GPR[RT])));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));

}



// end-sanitize-vr4xxx
// start-sanitize-cygnus
// Unsigned Multiply, Negate, Accumulate and Move LO.
000000,5.RS,5.RT,5.RD,00111,011001::64::MSACU
"msacu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Multiply, Negate, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
"msachi r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}

// end-sanitize-cygnus
// start-sanitize-cygnus
// Unsigned Multiply, Negate, Accumulate and Move HI.
000000,5.RS,5.RT,5.RD,01111,011001::64::MSACHIU
"msachiu r<RD>, r<RS>, r<RT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Rotate Right.
000000,00001,5.RT,5.RD,5.SHIFT,000010::64::ROR
"ror r<RD>, r<RT>, <SHIFT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  int s = SHIFT;
  GPR[RD] = ROTR32 (GPR[RT], s);
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Rotate Right Variable.
000000,5.RS,5.RT,5.RD,00001,000110::64::RORV
"rorv r<RD>, r<RT>, <RS>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  int s = MASKED (GPR[RS], 4, 0);
  GPR[RD] = ROTR32 (GPR[RT], s);
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Double Rotate Right.
000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
"dror r<RD>, r<RT>, <SHIFT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  int s = SHIFT;
  GPR[RD] = ROTR64 (GPR[RT], s);
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Double Rotate Right Plus 32.
000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
"dror32 r<RD>, r<RT>, <SHIFT>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  int s = SHIFT + 32;
  GPR[RD] = ROTR64 (GPR[RT], s);
}


// end-sanitize-cygnus
// start-sanitize-cygnus
// Double Rotate Right Variable.
000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
"drorv r<RD>, r<RT>, <RS>"
// end-sanitize-cygnus
// start-sanitize-cygnus
*vr5400:
// end-sanitize-cygnus
// start-sanitize-cygnus
{
  int s = MASKED (GPR[RS], 5, 0);
  GPR[RD] = ROTR64 (GPR[RT], s);
}


// end-sanitize-cygnus